1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <arch_helpers.h> 9 #include <common/debug.h> 10 #include <drivers/delay_timer.h> 11 #include <lib/mmio.h> 12 #include <lib/psci/psci.h> 13 #include <plat/common/platform.h> 14 15 #include <bpmp.h> 16 #include <flowctrl.h> 17 #include <pmc.h> 18 #include <platform_def.h> 19 #include <security_engine.h> 20 #include <tegra_def.h> 21 #include <tegra_private.h> 22 #include <tegra_platform.h> 23 24 /* 25 * Register used to clear CPU reset signals. Each CPU has two reset 26 * signals: CPU reset (3:0) and Core reset (19:16). 27 */ 28 #define CPU_CMPLX_RESET_CLR 0x454 29 #define CPU_CORE_RESET_MASK 0x10001 30 31 /* Clock and Reset controller registers for system clock's settings */ 32 #define SCLK_RATE 0x30 33 #define SCLK_BURST_POLICY 0x28 34 #define SCLK_BURST_POLICY_DEFAULT 0x10000000 35 36 static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER]; 37 38 int32_t tegra_soc_validate_power_state(unsigned int power_state, 39 psci_power_state_t *req_state) 40 { 41 int state_id = psci_get_pstate_id(power_state); 42 43 /* Sanity check the requested state id */ 44 switch (state_id) { 45 case PSTATE_ID_CORE_POWERDN: 46 /* 47 * Core powerdown request only for afflvl 0 48 */ 49 req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id & 0xff; 50 51 break; 52 53 case PSTATE_ID_CLUSTER_IDLE: 54 case PSTATE_ID_CLUSTER_POWERDN: 55 /* 56 * Cluster powerdown/idle request only for afflvl 1 57 */ 58 req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id; 59 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PSTATE_ID_CORE_POWERDN; 60 61 break; 62 63 case PSTATE_ID_SOC_POWERDN: 64 /* 65 * System powerdown request only for afflvl 2 66 */ 67 for (uint32_t i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++) 68 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; 69 70 req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = 71 PLAT_SYS_SUSPEND_STATE_ID; 72 73 break; 74 75 default: 76 ERROR("%s: unsupported state id (%d)\n", __func__, state_id); 77 return PSCI_E_INVALID_PARAMS; 78 } 79 80 return PSCI_E_SUCCESS; 81 } 82 83 /******************************************************************************* 84 * Platform handler to calculate the proper target power level at the 85 * specified affinity level 86 ******************************************************************************/ 87 plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl, 88 const plat_local_state_t *states, 89 unsigned int ncpu) 90 { 91 plat_local_state_t target = PSCI_LOCAL_STATE_RUN; 92 int cpu = plat_my_core_pos(); 93 int core_pos = read_mpidr() & MPIDR_CPU_MASK; 94 uint32_t bpmp_reply, data[3]; 95 int ret; 96 97 /* get the power state at this level */ 98 if (lvl == MPIDR_AFFLVL1) 99 target = *(states + core_pos); 100 if (lvl == MPIDR_AFFLVL2) 101 target = *(states + cpu); 102 103 if ((lvl == MPIDR_AFFLVL1) && (target == PSTATE_ID_CLUSTER_IDLE)) { 104 105 /* initialize the bpmp interface */ 106 (void)tegra_bpmp_init(); 107 108 /* Cluster idle */ 109 data[0] = (uint32_t)cpu; 110 data[1] = TEGRA_PM_CC6; 111 data[2] = TEGRA_PM_SC1; 112 ret = tegra_bpmp_send_receive_atomic(MRQ_DO_IDLE, 113 (void *)&data, (int)sizeof(data), 114 (void *)&bpmp_reply, (int)sizeof(bpmp_reply)); 115 116 /* check if cluster idle entry is allowed */ 117 if ((ret != 0L) || (bpmp_reply != BPMP_CCx_ALLOWED)) { 118 119 /* Cluster idle not allowed */ 120 target = PSCI_LOCAL_STATE_RUN; 121 } 122 123 } else if ((lvl == MPIDR_AFFLVL1) && (target == PSTATE_ID_CLUSTER_POWERDN)) { 124 125 /* initialize the bpmp interface */ 126 (void)tegra_bpmp_init(); 127 128 /* Cluster power-down */ 129 data[0] = (uint32_t)cpu; 130 data[1] = TEGRA_PM_CC7; 131 data[2] = TEGRA_PM_SC1; 132 ret = tegra_bpmp_send_receive_atomic(MRQ_DO_IDLE, 133 (void *)&data, (int)sizeof(data), 134 (void *)&bpmp_reply, (int)sizeof(bpmp_reply)); 135 136 /* check if cluster power down is allowed */ 137 if ((ret != 0L) || (bpmp_reply != BPMP_CCx_ALLOWED)) { 138 139 /* Cluster power down not allowed */ 140 target = PSCI_LOCAL_STATE_RUN; 141 } 142 143 } else if (((lvl == MPIDR_AFFLVL2) || (lvl == MPIDR_AFFLVL1)) && 144 (target == PSTATE_ID_SOC_POWERDN)) { 145 146 /* System Suspend */ 147 target = PSTATE_ID_SOC_POWERDN; 148 149 } else { 150 ; /* do nothing */ 151 } 152 153 return target; 154 } 155 156 int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) 157 { 158 u_register_t mpidr = read_mpidr(); 159 const plat_local_state_t *pwr_domain_state = 160 target_state->pwr_domain_state; 161 unsigned int stateid_afflvl2 = pwr_domain_state[MPIDR_AFFLVL2]; 162 unsigned int stateid_afflvl1 = pwr_domain_state[MPIDR_AFFLVL1]; 163 unsigned int stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0]; 164 int ret = PSCI_E_SUCCESS; 165 166 if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { 167 168 assert((stateid_afflvl0 == PLAT_MAX_OFF_STATE) || 169 (stateid_afflvl0 == PSTATE_ID_SOC_POWERDN)); 170 assert((stateid_afflvl1 == PLAT_MAX_OFF_STATE) || 171 (stateid_afflvl1 == PSTATE_ID_SOC_POWERDN)); 172 173 if (tegra_chipid_is_t210_b01()) { 174 175 /* Suspend se/se2 and pka1 */ 176 if (tegra_se_suspend() != 0) { 177 ret = PSCI_E_INTERN_FAIL; 178 } 179 180 /* Save tzram contents */ 181 if (tegra_se_save_tzram() != 0) { 182 ret = PSCI_E_INTERN_FAIL; 183 } 184 } 185 186 /* enter system suspend */ 187 if (ret == PSCI_E_SUCCESS) { 188 tegra_fc_soc_powerdn(mpidr); 189 } 190 191 } else if (stateid_afflvl1 == PSTATE_ID_CLUSTER_IDLE) { 192 193 assert(stateid_afflvl0 == PSTATE_ID_CORE_POWERDN); 194 195 /* Prepare for cluster idle */ 196 tegra_fc_cluster_idle(mpidr); 197 198 } else if (stateid_afflvl1 == PSTATE_ID_CLUSTER_POWERDN) { 199 200 assert(stateid_afflvl0 == PSTATE_ID_CORE_POWERDN); 201 202 /* Prepare for cluster powerdn */ 203 tegra_fc_cluster_powerdn(mpidr); 204 205 } else if (stateid_afflvl0 == PSTATE_ID_CORE_POWERDN) { 206 207 /* Prepare for cpu powerdn */ 208 tegra_fc_cpu_powerdn(mpidr); 209 210 } else { 211 ERROR("%s: Unknown state id (%d, %d, %d)\n", __func__, 212 stateid_afflvl2, stateid_afflvl1, stateid_afflvl0); 213 ret = PSCI_E_NOT_SUPPORTED; 214 } 215 216 return ret; 217 } 218 219 int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) 220 { 221 uint32_t val; 222 223 /* 224 * Check if we are exiting from SOC_POWERDN. 225 */ 226 if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] == 227 PLAT_SYS_SUSPEND_STATE_ID) { 228 229 /* 230 * Security engine resume 231 */ 232 if (tegra_chipid_is_t210_b01()) { 233 tegra_se_resume(); 234 } 235 236 /* 237 * Lock scratch registers which hold the CPU vectors 238 */ 239 tegra_pmc_lock_cpu_vectors(); 240 241 /* 242 * Enable WRAP to INCR burst type conversions for 243 * incoming requests on the AXI slave ports. 244 */ 245 val = mmio_read_32(TEGRA_MSELECT_BASE + MSELECT_CONFIG); 246 val &= ~ENABLE_UNSUP_TX_ERRORS; 247 val |= ENABLE_WRAP_TO_INCR_BURSTS; 248 mmio_write_32(TEGRA_MSELECT_BASE + MSELECT_CONFIG, val); 249 250 /* 251 * Restore Boot and Power Management Processor (BPMP) reset 252 * address and reset it. 253 */ 254 tegra_fc_reset_bpmp(); 255 } 256 257 /* 258 * T210 has a dedicated ARMv7 boot and power mgmt processor, BPMP. It's 259 * used for power management and boot purposes. Inform the BPMP that 260 * we have completed the cluster power up. 261 */ 262 tegra_fc_lock_active_cluster(); 263 264 return PSCI_E_SUCCESS; 265 } 266 267 int tegra_soc_pwr_domain_on(u_register_t mpidr) 268 { 269 int cpu = mpidr & MPIDR_CPU_MASK; 270 uint32_t mask = CPU_CORE_RESET_MASK << cpu; 271 272 /* Deassert CPU reset signals */ 273 mmio_write_32(TEGRA_CAR_RESET_BASE + CPU_CMPLX_RESET_CLR, mask); 274 275 /* Turn on CPU using flow controller or PMC */ 276 if (cpu_powergate_mask[cpu] == 0) { 277 tegra_pmc_cpu_on(cpu); 278 cpu_powergate_mask[cpu] = 1; 279 } else { 280 tegra_fc_cpu_on(cpu); 281 } 282 283 return PSCI_E_SUCCESS; 284 } 285 286 int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) 287 { 288 tegra_fc_cpu_off(read_mpidr() & MPIDR_CPU_MASK); 289 return PSCI_E_SUCCESS; 290 } 291 292 int tegra_soc_prepare_system_reset(void) 293 { 294 /* 295 * Set System Clock (SCLK) to POR default so that the clock source 296 * for the PMC APB clock would not be changed due to system reset. 297 */ 298 mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_BURST_POLICY, 299 SCLK_BURST_POLICY_DEFAULT); 300 mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_RATE, 0); 301 302 /* Wait 1 ms to make sure clock source/device logic is stabilized. */ 303 mdelay(1); 304 305 return PSCI_E_SUCCESS; 306 } 307