1 /* 2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <assert.h> 33 #include <debug.h> 34 #include <mmio.h> 35 #include <platform.h> 36 #include <platform_def.h> 37 #include <psci.h> 38 #include <pmc.h> 39 #include <flowctrl.h> 40 #include <tegra_def.h> 41 #include <tegra_private.h> 42 43 /* 44 * Register used to clear CPU reset signals. Each CPU has two reset 45 * signals: CPU reset (3:0) and Core reset (19:16). 46 */ 47 #define CPU_CMPLX_RESET_CLR 0x454 48 #define CPU_CORE_RESET_MASK 0x10001 49 50 static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER]; 51 52 int tegra_prepare_cpu_suspend(unsigned int id, unsigned int afflvl) 53 { 54 /* There's nothing to be done for affinity level 1 */ 55 if (afflvl == MPIDR_AFFLVL1) 56 return PSCI_E_SUCCESS; 57 58 switch (id) { 59 /* Prepare for cpu idle */ 60 case PSTATE_ID_CORE_POWERDN: 61 tegra_fc_cpu_idle(read_mpidr()); 62 return PSCI_E_SUCCESS; 63 64 /* Prepare for cluster idle */ 65 case PSTATE_ID_CLUSTER_IDLE: 66 tegra_fc_cluster_idle(read_mpidr()); 67 return PSCI_E_SUCCESS; 68 69 /* Prepare for cluster powerdn */ 70 case PSTATE_ID_CLUSTER_POWERDN: 71 tegra_fc_cluster_powerdn(read_mpidr()); 72 return PSCI_E_SUCCESS; 73 74 /* Prepare for system idle */ 75 case PSTATE_ID_SOC_POWERDN: 76 77 /* Enter system suspend state */ 78 tegra_pm_system_suspend_entry(); 79 80 /* suspend the entire soc */ 81 tegra_fc_soc_powerdn(read_mpidr()); 82 83 return PSCI_E_SUCCESS; 84 85 default: 86 ERROR("Unknown state id (%d)\n", id); 87 break; 88 } 89 90 return PSCI_E_NOT_SUPPORTED; 91 } 92 93 int tegra_prepare_cpu_on_finish(unsigned long mpidr) 94 { 95 /* 96 * Check if we are exiting from SOC_POWERDN. 97 */ 98 if (tegra_system_suspended()) { 99 100 /* 101 * Restore Boot and Power Management Processor (BPMP) reset 102 * address and reset it. 103 */ 104 tegra_fc_reset_bpmp(); 105 106 /* 107 * System resume complete. 108 */ 109 tegra_pm_system_suspend_exit(); 110 } 111 112 /* 113 * T210 has a dedicated ARMv7 boot and power mgmt processor, BPMP. It's 114 * used for power management and boot purposes. Inform the BPMP that 115 * we have completed the cluster power up. 116 */ 117 if (psci_get_max_phys_off_afflvl() == MPIDR_AFFLVL1) 118 tegra_fc_lock_active_cluster(); 119 120 return PSCI_E_SUCCESS; 121 } 122 123 int tegra_prepare_cpu_on(unsigned long mpidr) 124 { 125 int cpu = mpidr & MPIDR_CPU_MASK; 126 uint32_t mask = CPU_CORE_RESET_MASK << cpu; 127 128 /* Deassert CPU reset signals */ 129 mmio_write_32(TEGRA_CAR_RESET_BASE + CPU_CMPLX_RESET_CLR, mask); 130 131 /* Turn on CPU using flow controller or PMC */ 132 if (cpu_powergate_mask[cpu] == 0) { 133 tegra_pmc_cpu_on(cpu); 134 cpu_powergate_mask[cpu] = 1; 135 } else { 136 tegra_fc_cpu_on(cpu); 137 } 138 139 return PSCI_E_SUCCESS; 140 } 141 142 int tegra_prepare_cpu_off(unsigned long mpidr) 143 { 144 tegra_fc_cpu_off(mpidr & MPIDR_CPU_MASK); 145 return PSCI_E_SUCCESS; 146 } 147