1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <cortex_a57.h> 9 #include <arch_helpers.h> 10 #include <common/debug.h> 11 #include <drivers/delay_timer.h> 12 #include <lib/mmio.h> 13 #include <lib/psci/psci.h> 14 #include <plat/common/platform.h> 15 16 #include <bpmp.h> 17 #include <flowctrl.h> 18 #include <memctrl.h> 19 #include <pmc.h> 20 #include <platform_def.h> 21 #include <security_engine.h> 22 #include <tegra_def.h> 23 #include <tegra_private.h> 24 #include <tegra_platform.h> 25 #include <utils.h> 26 27 /* 28 * Register used to clear CPU reset signals. Each CPU has two reset 29 * signals: CPU reset (3:0) and Core reset (19:16). 30 */ 31 #define CPU_CMPLX_RESET_CLR 0x454 32 #define CPU_CORE_RESET_MASK 0x10001 33 34 /* Clock and Reset controller registers for system clock's settings */ 35 #define SCLK_RATE 0x30 36 #define SCLK_BURST_POLICY 0x28 37 #define SCLK_BURST_POLICY_DEFAULT 0x10000000 38 39 static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER]; 40 static bool tegra_bpmp_available = true; 41 42 int32_t tegra_soc_validate_power_state(unsigned int power_state, 43 psci_power_state_t *req_state) 44 { 45 int state_id = psci_get_pstate_id(power_state); 46 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); 47 48 /* Sanity check the requested state id */ 49 switch (state_id) { 50 case PSTATE_ID_CORE_POWERDN: 51 /* 52 * Core powerdown request only for afflvl 0 53 */ 54 req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id & 0xff; 55 56 break; 57 58 case PSTATE_ID_CLUSTER_IDLE: 59 60 /* 61 * Cluster idle request for afflvl 0 62 */ 63 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PSTATE_ID_CORE_POWERDN; 64 req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id; 65 break; 66 67 case PSTATE_ID_SOC_POWERDN: 68 69 /* 70 * sc7entry-fw must be present in the system when the bpmp 71 * firmware is not present, for a successful System Suspend 72 * entry. 73 */ 74 if (!tegra_bpmp_init() && !plat_params->sc7entry_fw_base) 75 return PSCI_E_NOT_SUPPORTED; 76 77 /* 78 * System powerdown request only for afflvl 2 79 */ 80 for (uint32_t i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++) 81 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; 82 83 req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = 84 PLAT_SYS_SUSPEND_STATE_ID; 85 86 break; 87 88 default: 89 ERROR("%s: unsupported state id (%d)\n", __func__, state_id); 90 return PSCI_E_INVALID_PARAMS; 91 } 92 93 return PSCI_E_SUCCESS; 94 } 95 96 /******************************************************************************* 97 * Platform handler to calculate the proper target power level at the 98 * specified affinity level. 99 ******************************************************************************/ 100 plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl, 101 const plat_local_state_t *states, 102 unsigned int ncpu) 103 { 104 plat_local_state_t target = PSCI_LOCAL_STATE_RUN; 105 int cpu = plat_my_core_pos(); 106 int core_pos = read_mpidr() & MPIDR_CPU_MASK; 107 uint32_t bpmp_reply, data[3], val; 108 int ret; 109 110 /* get the power state at this level */ 111 if (lvl == MPIDR_AFFLVL1) 112 target = *(states + core_pos); 113 if (lvl == MPIDR_AFFLVL2) 114 target = *(states + cpu); 115 116 if ((lvl == MPIDR_AFFLVL1) && (target == PSTATE_ID_CLUSTER_IDLE)) { 117 118 /* initialize the bpmp interface */ 119 ret = tegra_bpmp_init(); 120 if (ret != 0U) { 121 122 /* 123 * flag to indicate that BPMP firmware is not 124 * available and the CPU has to handle entry/exit 125 * for all power states 126 */ 127 tegra_bpmp_available = false; 128 129 /* Cluster idle not allowed */ 130 target = PSCI_LOCAL_STATE_RUN; 131 132 /******************************************* 133 * BPMP is not present, so handle CC6 entry 134 * from the CPU 135 ******************************************/ 136 137 /* check if cluster idle state has been enabled */ 138 val = mmio_read_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_CTRL); 139 if (val == ENABLE_CLOSED_LOOP) { 140 /* 141 * Acquire the cluster idle lock to stop 142 * other CPUs from powering up. 143 */ 144 tegra_fc_ccplex_pgexit_lock(); 145 146 /* Cluster idle only from the last standing CPU */ 147 if (tegra_pmc_is_last_on_cpu() && tegra_fc_is_ccx_allowed()) { 148 /* Cluster idle allowed */ 149 target = PSTATE_ID_CLUSTER_IDLE; 150 } else { 151 /* release cluster idle lock */ 152 tegra_fc_ccplex_pgexit_unlock(); 153 } 154 } 155 } else { 156 157 /* Cluster power-down */ 158 data[0] = (uint32_t)cpu; 159 data[1] = TEGRA_PM_CC6; 160 data[2] = TEGRA_PM_SC1; 161 ret = tegra_bpmp_send_receive_atomic(MRQ_DO_IDLE, 162 (void *)&data, (int)sizeof(data), 163 (void *)&bpmp_reply, 164 (int)sizeof(bpmp_reply)); 165 166 /* check if cluster power down is allowed */ 167 if ((ret != 0L) || (bpmp_reply != BPMP_CCx_ALLOWED)) { 168 169 /* Cluster power down not allowed */ 170 target = PSCI_LOCAL_STATE_RUN; 171 } 172 } 173 174 } else if (((lvl == MPIDR_AFFLVL2) || (lvl == MPIDR_AFFLVL1)) && 175 (target == PSTATE_ID_SOC_POWERDN)) { 176 177 /* System Suspend */ 178 target = PSTATE_ID_SOC_POWERDN; 179 180 } else { 181 ; /* do nothing */ 182 } 183 184 return target; 185 } 186 187 int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) 188 { 189 u_register_t mpidr = read_mpidr(); 190 const plat_local_state_t *pwr_domain_state = 191 target_state->pwr_domain_state; 192 unsigned int stateid_afflvl2 = pwr_domain_state[MPIDR_AFFLVL2]; 193 unsigned int stateid_afflvl1 = pwr_domain_state[MPIDR_AFFLVL1]; 194 unsigned int stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0]; 195 uint32_t cfg; 196 int ret = PSCI_E_SUCCESS; 197 uint32_t val; 198 199 if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { 200 201 assert((stateid_afflvl0 == PLAT_MAX_OFF_STATE) || 202 (stateid_afflvl0 == PSTATE_ID_SOC_POWERDN)); 203 assert((stateid_afflvl1 == PLAT_MAX_OFF_STATE) || 204 (stateid_afflvl1 == PSTATE_ID_SOC_POWERDN)); 205 206 if (tegra_chipid_is_t210_b01()) { 207 208 /* Suspend se/se2 and pka1 */ 209 if (tegra_se_suspend() != 0) { 210 ret = PSCI_E_INTERN_FAIL; 211 } 212 } 213 214 } else if (stateid_afflvl1 == PSTATE_ID_CLUSTER_IDLE) { 215 216 assert(stateid_afflvl0 == PSTATE_ID_CORE_POWERDN); 217 218 if (!tegra_bpmp_available) { 219 220 /* 221 * When disabled, DFLL loses its state. Enable 222 * open loop state for the DFLL as we dont want 223 * garbage values being written to the pmic 224 * when we enter cluster idle state. 225 */ 226 mmio_write_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_CTRL, 227 ENABLE_OPEN_LOOP); 228 229 /* Find if the platform uses OVR2/MAX77621 PMIC */ 230 cfg = mmio_read_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_OUTPUT_CFG); 231 if (cfg & DFLL_OUTPUT_CFG_CLK_EN_BIT) { 232 /* OVR2 */ 233 234 /* PWM tristate */ 235 val = mmio_read_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM); 236 val |= PINMUX_PWM_TRISTATE; 237 mmio_write_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM, val); 238 239 /* 240 * SCRATCH201[1] is being used to identify CPU 241 * PMIC in warmboot code. 242 * 0 : OVR2 243 * 1 : MAX77621 244 */ 245 tegra_pmc_write_32(PMC_SCRATCH201, 0x0); 246 } else { 247 /* MAX77621 */ 248 tegra_pmc_write_32(PMC_SCRATCH201, 0x2); 249 } 250 } 251 252 /* Prepare for cluster idle */ 253 tegra_fc_cluster_idle(mpidr); 254 255 } else if (stateid_afflvl0 == PSTATE_ID_CORE_POWERDN) { 256 257 /* Prepare for cpu powerdn */ 258 tegra_fc_cpu_powerdn(mpidr); 259 260 } else { 261 ERROR("%s: Unknown state id (%d, %d, %d)\n", __func__, 262 stateid_afflvl2, stateid_afflvl1, stateid_afflvl0); 263 ret = PSCI_E_NOT_SUPPORTED; 264 } 265 266 return ret; 267 } 268 269 static void tegra_reset_all_dma_masters(void) 270 { 271 uint32_t val, mask; 272 273 /* 274 * Reset all possible DMA masters in the system. 275 */ 276 val = GPU_RESET_BIT; 277 mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_GPU_RESET_REG_OFFSET, val); 278 279 val = NVENC_RESET_BIT | TSECB_RESET_BIT | APE_RESET_BIT | 280 NVJPG_RESET_BIT | NVDEC_RESET_BIT; 281 mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_Y, val); 282 283 val = HOST1X_RESET_BIT | ISP_RESET_BIT | USBD_RESET_BIT | 284 VI_RESET_BIT | SDMMC4_RESET_BIT | SDMMC1_RESET_BIT | 285 SDMMC2_RESET_BIT; 286 mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_L, val); 287 288 val = USB2_RESET_BIT | APBDMA_RESET_BIT | AHBDMA_RESET_BIT; 289 mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_H, val); 290 291 val = XUSB_DEV_RESET_BIT | XUSB_HOST_RESET_BIT | TSEC_RESET_BIT | 292 PCIE_RESET_BIT | SDMMC3_RESET_BIT; 293 mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_U, val); 294 295 val = SE_RESET_BIT | HDA_RESET_BIT | SATA_RESET_BIT; 296 mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_V, val); 297 298 /* 299 * If any of the DMA masters are still alive, assume 300 * that the system has been compromised and reboot. 301 */ 302 val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_GPU_RESET_REG_OFFSET); 303 mask = GPU_RESET_BIT; 304 if ((val & mask) != mask) 305 tegra_pmc_system_reset(); 306 307 mask = NVENC_RESET_BIT | TSECB_RESET_BIT | APE_RESET_BIT | 308 NVJPG_RESET_BIT | NVDEC_RESET_BIT; 309 val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_Y); 310 if ((val & mask) != mask) 311 tegra_pmc_system_reset(); 312 313 mask = HOST1X_RESET_BIT | ISP_RESET_BIT | USBD_RESET_BIT | 314 VI_RESET_BIT | SDMMC4_RESET_BIT | SDMMC1_RESET_BIT | 315 SDMMC2_RESET_BIT; 316 val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_L); 317 if ((val & mask) != mask) 318 tegra_pmc_system_reset(); 319 320 mask = USB2_RESET_BIT | APBDMA_RESET_BIT | AHBDMA_RESET_BIT; 321 val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_H); 322 if ((val & mask) != mask) 323 tegra_pmc_system_reset(); 324 325 mask = XUSB_DEV_RESET_BIT | XUSB_HOST_RESET_BIT | TSEC_RESET_BIT | 326 PCIE_RESET_BIT | SDMMC3_RESET_BIT; 327 val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_U); 328 if ((val & mask) != mask) 329 tegra_pmc_system_reset(); 330 331 val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_V); 332 mask = SE_RESET_BIT | HDA_RESET_BIT | SATA_RESET_BIT; 333 if ((val & mask) != mask) 334 tegra_pmc_system_reset(); 335 } 336 337 int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) 338 { 339 u_register_t mpidr = read_mpidr(); 340 const plat_local_state_t *pwr_domain_state = 341 target_state->pwr_domain_state; 342 unsigned int stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL]; 343 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); 344 uint32_t val; 345 346 if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { 347 348 if (tegra_chipid_is_t210_b01()) { 349 /* Save tzram contents */ 350 tegra_se_save_tzram(); 351 } 352 353 /* de-init the interface */ 354 tegra_bpmp_suspend(); 355 356 /* 357 * The CPU needs to load the System suspend entry firmware 358 * if nothing is running on the BPMP. 359 */ 360 if (!tegra_bpmp_available) { 361 362 /* 363 * BPMP firmware is not running on the co-processor, so 364 * we need to explicitly load the firmware to enable 365 * entry/exit to/from System Suspend and set the BPMP 366 * on its way. 367 */ 368 369 /* Power off BPMP before we proceed */ 370 tegra_fc_bpmp_off(); 371 372 /* bond out IRAM banks B, C and D */ 373 mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_BOND_OUT_U, 374 IRAM_B_LOCK_BIT | IRAM_C_LOCK_BIT | 375 IRAM_D_LOCK_BIT); 376 377 /* bond out APB/AHB DMAs */ 378 mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_BOND_OUT_H, 379 APB_DMA_LOCK_BIT | AHB_DMA_LOCK_BIT); 380 381 /* Power off BPMP before we proceed */ 382 tegra_fc_bpmp_off(); 383 384 /* 385 * Reset all the hardware blocks that can act as DMA 386 * masters on the bus. 387 */ 388 tegra_reset_all_dma_masters(); 389 390 /* clean up IRAM of any cruft */ 391 zeromem((void *)(uintptr_t)TEGRA_IRAM_BASE, 392 TEGRA_IRAM_A_SIZE); 393 394 /* Copy the firmware to BPMP's internal RAM */ 395 (void)memcpy((void *)(uintptr_t)TEGRA_IRAM_BASE, 396 (const void *)(plat_params->sc7entry_fw_base + SC7ENTRY_FW_HEADER_SIZE_BYTES), 397 plat_params->sc7entry_fw_size - SC7ENTRY_FW_HEADER_SIZE_BYTES); 398 399 /* Power on the BPMP and execute from IRAM base */ 400 tegra_fc_bpmp_on(TEGRA_IRAM_BASE); 401 402 /* Wait until BPMP powers up */ 403 do { 404 val = mmio_read_32(TEGRA_RES_SEMA_BASE + STA_OFFSET); 405 } while (val != SIGN_OF_LIFE); 406 } 407 408 /* enter system suspend */ 409 tegra_fc_soc_powerdn(mpidr); 410 } 411 412 return PSCI_E_SUCCESS; 413 } 414 415 int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) 416 { 417 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); 418 uint32_t cfg; 419 uint32_t val, entrypoint = 0; 420 uint64_t offset; 421 422 /* platform parameter passed by the previous bootloader */ 423 if (plat_params->l2_ecc_parity_prot_dis != 1) { 424 /* Enable ECC Parity Protection for Cortex-A57 CPUs */ 425 val = read_l2ctlr_el1(); 426 val |= (uint64_t)CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT; 427 write_l2ctlr_el1(val); 428 } 429 430 /* 431 * Check if we are exiting from SOC_POWERDN. 432 */ 433 if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] == 434 PLAT_SYS_SUSPEND_STATE_ID) { 435 436 /* 437 * Security engine resume 438 */ 439 if (tegra_chipid_is_t210_b01()) { 440 tegra_se_resume(); 441 } 442 443 /* 444 * Lock scratch registers which hold the CPU vectors 445 */ 446 tegra_pmc_lock_cpu_vectors(); 447 448 /* 449 * Enable WRAP to INCR burst type conversions for 450 * incoming requests on the AXI slave ports. 451 */ 452 val = mmio_read_32(TEGRA_MSELECT_BASE + MSELECT_CONFIG); 453 val &= ~ENABLE_UNSUP_TX_ERRORS; 454 val |= ENABLE_WRAP_TO_INCR_BURSTS; 455 mmio_write_32(TEGRA_MSELECT_BASE + MSELECT_CONFIG, val); 456 457 /* 458 * Restore Boot and Power Management Processor (BPMP) reset 459 * address and reset it, if it is supported by the platform. 460 */ 461 if (!tegra_bpmp_available) { 462 tegra_fc_bpmp_off(); 463 } else { 464 entrypoint = tegra_pmc_read_32(PMC_SCRATCH39); 465 tegra_fc_bpmp_on(entrypoint); 466 467 /* initialise the interface */ 468 tegra_bpmp_resume(); 469 } 470 471 /* sc7entry-fw is part of TZDRAM area */ 472 if (plat_params->sc7entry_fw_base != 0U) { 473 offset = plat_params->tzdram_base - plat_params->sc7entry_fw_base; 474 tegra_memctrl_tzdram_setup(plat_params->sc7entry_fw_base, 475 plat_params->tzdram_size + offset); 476 477 /* restrict PMC access to secure world */ 478 val = mmio_read_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE); 479 val |= PMC_SECURITY_EN_BIT; 480 mmio_write_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE, val); 481 } 482 } 483 484 /* 485 * Check if we are exiting cluster idle state 486 */ 487 if (target_state->pwr_domain_state[MPIDR_AFFLVL1] == 488 PSTATE_ID_CLUSTER_IDLE) { 489 490 if (!tegra_bpmp_available) { 491 492 /* PWM un-tristate */ 493 cfg = mmio_read_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_OUTPUT_CFG); 494 if (cfg & DFLL_OUTPUT_CFG_CLK_EN_BIT) { 495 val = mmio_read_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM); 496 val &= ~PINMUX_PWM_TRISTATE; 497 mmio_write_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM, val); 498 499 /* make sure the setting took effect */ 500 val = mmio_read_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM); 501 assert((val & PINMUX_PWM_TRISTATE) == 0U); 502 } 503 504 /* 505 * Restore operation mode for the DFLL ring 506 * oscillator 507 */ 508 mmio_write_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_CTRL, 509 ENABLE_CLOSED_LOOP); 510 511 /* release cluster idle lock */ 512 tegra_fc_ccplex_pgexit_unlock(); 513 } 514 } 515 516 /* 517 * T210 has a dedicated ARMv7 boot and power mgmt processor, BPMP. It's 518 * used for power management and boot purposes. Inform the BPMP that 519 * we have completed the cluster power up. 520 */ 521 tegra_fc_lock_active_cluster(); 522 523 /* 524 * Resume PMC hardware block for Tegra210 platforms supporting sc7entry-fw 525 */ 526 if (!tegra_chipid_is_t210_b01() && (plat_params->sc7entry_fw_base != 0U)) 527 tegra_pmc_resume(); 528 529 return PSCI_E_SUCCESS; 530 } 531 532 int tegra_soc_pwr_domain_on(u_register_t mpidr) 533 { 534 int cpu = mpidr & MPIDR_CPU_MASK; 535 uint32_t mask = CPU_CORE_RESET_MASK << cpu; 536 537 /* Deassert CPU reset signals */ 538 mmio_write_32(TEGRA_CAR_RESET_BASE + CPU_CMPLX_RESET_CLR, mask); 539 540 /* Turn on CPU using flow controller or PMC */ 541 if (cpu_powergate_mask[cpu] == 0) { 542 tegra_pmc_cpu_on(cpu); 543 cpu_powergate_mask[cpu] = 1; 544 } else { 545 tegra_fc_cpu_on(cpu); 546 } 547 548 return PSCI_E_SUCCESS; 549 } 550 551 int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) 552 { 553 tegra_fc_cpu_off(read_mpidr() & MPIDR_CPU_MASK); 554 return PSCI_E_SUCCESS; 555 } 556 557 int tegra_soc_prepare_system_reset(void) 558 { 559 /* 560 * Set System Clock (SCLK) to POR default so that the clock source 561 * for the PMC APB clock would not be changed due to system reset. 562 */ 563 mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_BURST_POLICY, 564 SCLK_BURST_POLICY_DEFAULT); 565 mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_RATE, 0); 566 567 /* Wait 1 ms to make sure clock source/device logic is stabilized. */ 568 mdelay(1); 569 570 return PSCI_E_SUCCESS; 571 } 572