1 /* 2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <assert.h> 33 #include <debug.h> 34 #include <delay_timer.h> 35 #include <mmio.h> 36 #include <platform.h> 37 #include <platform_def.h> 38 #include <psci.h> 39 #include <pmc.h> 40 #include <flowctrl.h> 41 #include <tegra_def.h> 42 #include <tegra_private.h> 43 44 /* 45 * Register used to clear CPU reset signals. Each CPU has two reset 46 * signals: CPU reset (3:0) and Core reset (19:16). 47 */ 48 #define CPU_CMPLX_RESET_CLR 0x454 49 #define CPU_CORE_RESET_MASK 0x10001 50 51 /* Clock and Reset controller registers for system clock's settings */ 52 #define SCLK_RATE 0x30 53 #define SCLK_BURST_POLICY 0x28 54 #define SCLK_BURST_POLICY_DEFAULT 0x10000000 55 56 static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER]; 57 58 int32_t tegra_soc_validate_power_state(unsigned int power_state) 59 { 60 /* Sanity check the requested afflvl */ 61 if (psci_get_pstate_type(power_state) == PSTATE_TYPE_STANDBY) { 62 /* 63 * It's possible to enter standby only on affinity level 0 i.e. 64 * a cpu on Tegra. Ignore any other affinity level. 65 */ 66 if (psci_get_pstate_afflvl(power_state) != MPIDR_AFFLVL0) 67 return PSCI_E_INVALID_PARAMS; 68 } 69 70 /* Sanity check the requested state id */ 71 switch (psci_get_pstate_id(power_state)) { 72 case PSTATE_ID_CORE_POWERDN: 73 case PSTATE_ID_CLUSTER_IDLE: 74 case PSTATE_ID_CLUSTER_POWERDN: 75 case PSTATE_ID_SOC_POWERDN: 76 break; 77 78 default: 79 ERROR("unsupported state id\n"); 80 return PSCI_E_NOT_SUPPORTED; 81 } 82 83 return PSCI_E_SUCCESS; 84 } 85 86 int tegra_soc_prepare_cpu_suspend(unsigned int id, unsigned int afflvl) 87 { 88 /* There's nothing to be done for affinity level 1 */ 89 if (afflvl == MPIDR_AFFLVL1) 90 return PSCI_E_SUCCESS; 91 92 switch (id) { 93 /* Prepare for cpu idle */ 94 case PSTATE_ID_CORE_POWERDN: 95 tegra_fc_cpu_idle(read_mpidr()); 96 return PSCI_E_SUCCESS; 97 98 /* Prepare for cluster idle */ 99 case PSTATE_ID_CLUSTER_IDLE: 100 tegra_fc_cluster_idle(read_mpidr()); 101 return PSCI_E_SUCCESS; 102 103 /* Prepare for cluster powerdn */ 104 case PSTATE_ID_CLUSTER_POWERDN: 105 tegra_fc_cluster_powerdn(read_mpidr()); 106 return PSCI_E_SUCCESS; 107 108 /* Prepare for system idle */ 109 case PSTATE_ID_SOC_POWERDN: 110 111 /* Enter system suspend state */ 112 tegra_pm_system_suspend_entry(); 113 114 /* suspend the entire soc */ 115 tegra_fc_soc_powerdn(read_mpidr()); 116 117 return PSCI_E_SUCCESS; 118 119 default: 120 ERROR("Unknown state id (%d)\n", id); 121 break; 122 } 123 124 return PSCI_E_NOT_SUPPORTED; 125 } 126 127 int tegra_soc_prepare_cpu_on_finish(unsigned long mpidr) 128 { 129 uint32_t val; 130 131 /* 132 * Check if we are exiting from SOC_POWERDN. 133 */ 134 if (tegra_system_suspended()) { 135 136 /* 137 * Enable WRAP to INCR burst type conversions for 138 * incoming requests on the AXI slave ports. 139 */ 140 val = mmio_read_32(TEGRA_MSELECT_BASE + MSELECT_CONFIG); 141 val &= ~ENABLE_UNSUP_TX_ERRORS; 142 val |= ENABLE_WRAP_TO_INCR_BURSTS; 143 mmio_write_32(TEGRA_MSELECT_BASE + MSELECT_CONFIG, val); 144 145 /* 146 * Restore Boot and Power Management Processor (BPMP) reset 147 * address and reset it. 148 */ 149 tegra_fc_reset_bpmp(); 150 151 /* 152 * System resume complete. 153 */ 154 tegra_pm_system_suspend_exit(); 155 } 156 157 /* 158 * T210 has a dedicated ARMv7 boot and power mgmt processor, BPMP. It's 159 * used for power management and boot purposes. Inform the BPMP that 160 * we have completed the cluster power up. 161 */ 162 if (psci_get_max_phys_off_afflvl() == MPIDR_AFFLVL1) 163 tegra_fc_lock_active_cluster(); 164 165 return PSCI_E_SUCCESS; 166 } 167 168 int tegra_soc_prepare_cpu_on(unsigned long mpidr) 169 { 170 int cpu = mpidr & MPIDR_CPU_MASK; 171 uint32_t mask = CPU_CORE_RESET_MASK << cpu; 172 173 /* Deassert CPU reset signals */ 174 mmio_write_32(TEGRA_CAR_RESET_BASE + CPU_CMPLX_RESET_CLR, mask); 175 176 /* Turn on CPU using flow controller or PMC */ 177 if (cpu_powergate_mask[cpu] == 0) { 178 tegra_pmc_cpu_on(cpu); 179 cpu_powergate_mask[cpu] = 1; 180 } else { 181 tegra_fc_cpu_on(cpu); 182 } 183 184 return PSCI_E_SUCCESS; 185 } 186 187 int tegra_soc_prepare_cpu_off(unsigned long mpidr) 188 { 189 tegra_fc_cpu_off(mpidr & MPIDR_CPU_MASK); 190 return PSCI_E_SUCCESS; 191 } 192 193 int tegra_soc_prepare_system_reset(void) 194 { 195 /* 196 * Set System Clock (SCLK) to POR default so that the clock source 197 * for the PMC APB clock would not be changed due to system reset. 198 */ 199 mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_BURST_POLICY, 200 SCLK_BURST_POLICY_DEFAULT); 201 mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_RATE, 0); 202 203 /* Wait 1 ms to make sure clock source/device logic is stabilized. */ 204 mdelay(1); 205 206 return PSCI_E_SUCCESS; 207 } 208