1 /* 2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <assert.h> 33 #include <debug.h> 34 #include <delay_timer.h> 35 #include <mmio.h> 36 #include <platform.h> 37 #include <platform_def.h> 38 #include <psci.h> 39 #include <pmc.h> 40 #include <flowctrl.h> 41 #include <tegra_def.h> 42 #include <tegra_private.h> 43 44 /* 45 * Register used to clear CPU reset signals. Each CPU has two reset 46 * signals: CPU reset (3:0) and Core reset (19:16). 47 */ 48 #define CPU_CMPLX_RESET_CLR 0x454 49 #define CPU_CORE_RESET_MASK 0x10001 50 51 /* Clock and Reset controller registers for system clock's settings */ 52 #define SCLK_RATE 0x30 53 #define SCLK_BURST_POLICY 0x28 54 #define SCLK_BURST_POLICY_DEFAULT 0x10000000 55 56 static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER]; 57 58 int32_t tegra_soc_validate_power_state(unsigned int power_state, 59 psci_power_state_t *req_state) 60 { 61 int pwr_lvl = psci_get_pstate_pwrlvl(power_state); 62 int state_id = psci_get_pstate_id(power_state); 63 64 if (pwr_lvl > PLAT_MAX_PWR_LVL) { 65 ERROR("%s: unsupported power_state (0x%x)\n", __func__, 66 power_state); 67 return PSCI_E_INVALID_PARAMS; 68 } 69 70 /* Sanity check the requested afflvl */ 71 if (psci_get_pstate_type(power_state) == PSTATE_TYPE_STANDBY) { 72 /* 73 * It's possible to enter standby only on affinity level 0 i.e. 74 * a cpu on Tegra. Ignore any other affinity level. 75 */ 76 if (pwr_lvl != MPIDR_AFFLVL0) 77 return PSCI_E_INVALID_PARAMS; 78 79 /* power domain in standby state */ 80 req_state->pwr_domain_state[pwr_lvl] = PLAT_MAX_RET_STATE; 81 82 return PSCI_E_SUCCESS; 83 } 84 85 /* Sanity check the requested state id */ 86 switch (state_id) { 87 case PSTATE_ID_CORE_POWERDN: 88 /* 89 * Core powerdown request only for afflvl 0 90 */ 91 if (pwr_lvl != MPIDR_AFFLVL0) 92 goto error; 93 94 req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id & 0xff; 95 96 break; 97 98 case PSTATE_ID_CLUSTER_IDLE: 99 case PSTATE_ID_CLUSTER_POWERDN: 100 /* 101 * Cluster powerdown/idle request only for afflvl 1 102 */ 103 if (pwr_lvl != MPIDR_AFFLVL1) 104 goto error; 105 106 req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id; 107 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; 108 109 break; 110 111 case PSTATE_ID_SOC_POWERDN: 112 /* 113 * System powerdown request only for afflvl 2 114 */ 115 if (pwr_lvl != PLAT_MAX_PWR_LVL) 116 goto error; 117 118 for (int i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++) 119 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; 120 121 req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = 122 PLAT_SYS_SUSPEND_STATE_ID; 123 124 break; 125 126 default: 127 ERROR("%s: unsupported state id (%d)\n", __func__, state_id); 128 return PSCI_E_INVALID_PARAMS; 129 } 130 131 return PSCI_E_SUCCESS; 132 133 error: 134 ERROR("%s: unsupported state id (%d)\n", __func__, state_id); 135 return PSCI_E_INVALID_PARAMS; 136 } 137 138 int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) 139 { 140 u_register_t mpidr = read_mpidr(); 141 const plat_local_state_t *pwr_domain_state = 142 target_state->pwr_domain_state; 143 unsigned int stateid_afflvl2 = pwr_domain_state[MPIDR_AFFLVL2]; 144 unsigned int stateid_afflvl1 = pwr_domain_state[MPIDR_AFFLVL1]; 145 unsigned int stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0]; 146 147 if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { 148 149 assert(stateid_afflvl0 == PLAT_MAX_OFF_STATE); 150 assert(stateid_afflvl1 == PLAT_MAX_OFF_STATE); 151 152 /* suspend the entire soc */ 153 tegra_fc_soc_powerdn(mpidr); 154 155 } else if (stateid_afflvl1 == PSTATE_ID_CLUSTER_IDLE) { 156 157 assert(stateid_afflvl0 == PLAT_MAX_OFF_STATE); 158 159 /* Prepare for cluster idle */ 160 tegra_fc_cluster_idle(mpidr); 161 162 } else if (stateid_afflvl1 == PSTATE_ID_CLUSTER_POWERDN) { 163 164 assert(stateid_afflvl0 == PLAT_MAX_OFF_STATE); 165 166 /* Prepare for cluster powerdn */ 167 tegra_fc_cluster_powerdn(mpidr); 168 169 } else if (stateid_afflvl0 == PSTATE_ID_CORE_POWERDN) { 170 171 /* Prepare for cpu powerdn */ 172 tegra_fc_cpu_powerdn(mpidr); 173 174 } else { 175 ERROR("%s: Unknown state id\n", __func__); 176 return PSCI_E_NOT_SUPPORTED; 177 } 178 179 return PSCI_E_SUCCESS; 180 } 181 182 int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) 183 { 184 uint32_t val; 185 186 /* 187 * Check if we are exiting from SOC_POWERDN. 188 */ 189 if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] == 190 PLAT_SYS_SUSPEND_STATE_ID) { 191 192 /* 193 * Enable WRAP to INCR burst type conversions for 194 * incoming requests on the AXI slave ports. 195 */ 196 val = mmio_read_32(TEGRA_MSELECT_BASE + MSELECT_CONFIG); 197 val &= ~ENABLE_UNSUP_TX_ERRORS; 198 val |= ENABLE_WRAP_TO_INCR_BURSTS; 199 mmio_write_32(TEGRA_MSELECT_BASE + MSELECT_CONFIG, val); 200 201 /* 202 * Restore Boot and Power Management Processor (BPMP) reset 203 * address and reset it. 204 */ 205 tegra_fc_reset_bpmp(); 206 } 207 208 /* 209 * T210 has a dedicated ARMv7 boot and power mgmt processor, BPMP. It's 210 * used for power management and boot purposes. Inform the BPMP that 211 * we have completed the cluster power up. 212 */ 213 tegra_fc_lock_active_cluster(); 214 215 return PSCI_E_SUCCESS; 216 } 217 218 int tegra_soc_pwr_domain_on(u_register_t mpidr) 219 { 220 int cpu = mpidr & MPIDR_CPU_MASK; 221 uint32_t mask = CPU_CORE_RESET_MASK << cpu; 222 223 /* Deassert CPU reset signals */ 224 mmio_write_32(TEGRA_CAR_RESET_BASE + CPU_CMPLX_RESET_CLR, mask); 225 226 /* Turn on CPU using flow controller or PMC */ 227 if (cpu_powergate_mask[cpu] == 0) { 228 tegra_pmc_cpu_on(cpu); 229 cpu_powergate_mask[cpu] = 1; 230 } else { 231 tegra_fc_cpu_on(cpu); 232 } 233 234 return PSCI_E_SUCCESS; 235 } 236 237 int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) 238 { 239 tegra_fc_cpu_off(read_mpidr() & MPIDR_CPU_MASK); 240 return PSCI_E_SUCCESS; 241 } 242 243 int tegra_soc_prepare_system_reset(void) 244 { 245 /* 246 * Set System Clock (SCLK) to POR default so that the clock source 247 * for the PMC APB clock would not be changed due to system reset. 248 */ 249 mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_BURST_POLICY, 250 SCLK_BURST_POLICY_DEFAULT); 251 mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_RATE, 0); 252 253 /* Wait 1 ms to make sure clock source/device logic is stabilized. */ 254 mdelay(1); 255 256 return PSCI_E_SUCCESS; 257 } 258