1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef SE_PRIVATE_H 9 #define SE_PRIVATE_H 10 11 #include <stdbool.h> 12 #include <security_engine.h> 13 14 /* 15 * PMC registers 16 */ 17 18 /* Secure scratch registers */ 19 #define PMC_SECURE_SCRATCH4_OFFSET 0xC0U 20 #define PMC_SECURE_SCRATCH5_OFFSET 0xC4U 21 #define PMC_SECURE_SCRATCH6_OFFSET 0x224U 22 #define PMC_SECURE_SCRATCH7_OFFSET 0x228U 23 #define PMC_SECURE_SCRATCH116_OFFSET 0xB28U 24 #define PMC_SECURE_SCRATCH117_OFFSET 0xB2CU 25 #define PMC_SECURE_SCRATCH120_OFFSET 0xB38U 26 #define PMC_SECURE_SCRATCH121_OFFSET 0xB3CU 27 #define PMC_SECURE_SCRATCH122_OFFSET 0xB40U 28 #define PMC_SECURE_SCRATCH123_OFFSET 0xB44U 29 30 /* 31 * AHB arbitration memory write queue 32 */ 33 #define ARAHB_MEM_WRQUE_MST_ID_OFFSET 0xFCU 34 #define ARAHB_MST_ID_SE2_MASK (0x1U << 13) 35 #define ARAHB_MST_ID_SE_MASK (0x1U << 14) 36 37 /** 38 * SE registers 39 */ 40 #define TEGRA_SE_AES_KEYSLOT_COUNT 16 41 #define SE_MAX_LAST_BLOCK_SIZE 0xFFFFF 42 43 /* SE Status register */ 44 #define SE_STATUS_OFFSET 0x800U 45 #define SE_STATUS_SHIFT 0 46 #define SE_STATUS_IDLE \ 47 ((0U) << SE_STATUS_SHIFT) 48 #define SE_STATUS_BUSY \ 49 ((1U) << SE_STATUS_SHIFT) 50 #define SE_STATUS(x) \ 51 ((x) & ((0x3U) << SE_STATUS_SHIFT)) 52 53 #define SE_MEM_INTERFACE_SHIFT 2 54 #define SE_MEM_INTERFACE_IDLE 0 55 #define SE_MEM_INTERFACE_BUSY 1 56 #define SE_MEM_INTERFACE(x) ((x) << SE_STATUS_SHIFT) 57 58 /* SE register definitions */ 59 #define SE_SECURITY_REG_OFFSET 0x0 60 #define SE_SECURITY_TZ_LOCK_SOFT_SHIFT 5 61 #define SE_SECURE 0x0 62 #define SE_SECURITY_TZ_LOCK_SOFT(x) ((x) << SE_SECURITY_TZ_LOCK_SOFT_SHIFT) 63 64 #define SE_SEC_ENG_DIS_SHIFT 1 65 #define SE_DISABLE_FALSE 0 66 #define SE_DISABLE_TRUE 1 67 #define SE_SEC_ENG_DISABLE(x)((x) << SE_SEC_ENG_DIS_SHIFT) 68 69 /* SE config register */ 70 #define SE_CONFIG_REG_OFFSET 0x14U 71 #define SE_CONFIG_ENC_ALG_SHIFT 12 72 #define SE_CONFIG_ENC_ALG_AES_ENC \ 73 ((1U) << SE_CONFIG_ENC_ALG_SHIFT) 74 #define SE_CONFIG_ENC_ALG_RNG \ 75 ((2U) << SE_CONFIG_ENC_ALG_SHIFT) 76 #define SE_CONFIG_ENC_ALG_SHA \ 77 ((3U) << SE_CONFIG_ENC_ALG_SHIFT) 78 #define SE_CONFIG_ENC_ALG_RSA \ 79 ((4U) << SE_CONFIG_ENC_ALG_SHIFT) 80 #define SE_CONFIG_ENC_ALG_NOP \ 81 ((0U) << SE_CONFIG_ENC_ALG_SHIFT) 82 #define SE_CONFIG_ENC_ALG(x) \ 83 ((x) & ((0xFU) << SE_CONFIG_ENC_ALG_SHIFT)) 84 85 #define SE_CONFIG_DEC_ALG_SHIFT 8 86 #define SE_CONFIG_DEC_ALG_AES \ 87 ((1U) << SE_CONFIG_DEC_ALG_SHIFT) 88 #define SE_CONFIG_DEC_ALG_NOP \ 89 ((0U) << SE_CONFIG_DEC_ALG_SHIFT) 90 #define SE_CONFIG_DEC_ALG(x) \ 91 ((x) & ((0xFU) << SE_CONFIG_DEC_ALG_SHIFT)) 92 93 #define SE_CONFIG_DST_SHIFT 2 94 #define SE_CONFIG_DST_MEMORY \ 95 ((0U) << SE_CONFIG_DST_SHIFT) 96 #define SE_CONFIG_DST_HASHREG \ 97 ((1U) << SE_CONFIG_DST_SHIFT) 98 #define SE_CONFIG_DST_KEYTAB \ 99 ((2U) << SE_CONFIG_DST_SHIFT) 100 #define SE_CONFIG_DST_SRK \ 101 ((3U) << SE_CONFIG_DST_SHIFT) 102 #define SE_CONFIG_DST_RSAREG \ 103 ((4U) << SE_CONFIG_DST_SHIFT) 104 #define SE_CONFIG_DST(x) \ 105 ((x) & ((0x7U) << SE_CONFIG_DST_SHIFT)) 106 107 #define SE_CONFIG_ENC_MODE_SHIFT 24 108 #define SE_CONFIG_ENC_MODE_KEY128 \ 109 ((0UL) << SE_CONFIG_ENC_MODE_SHIFT) 110 #define SE_CONFIG_ENC_MODE_KEY192 \ 111 ((1UL) << SE_CONFIG_ENC_MODE_SHIFT) 112 #define SE_CONFIG_ENC_MODE_KEY256 \ 113 ((2UL) << SE_CONFIG_ENC_MODE_SHIFT) 114 #define SE_CONFIG_ENC_MODE_SHA1 \ 115 ((0UL) << SE_CONFIG_ENC_MODE_SHIFT) 116 #define SE_CONFIG_ENC_MODE_SHA224 \ 117 ((4UL) << SE_CONFIG_ENC_MODE_SHIFT) 118 #define SE_CONFIG_ENC_MODE_SHA256 \ 119 ((5UL) << SE_CONFIG_ENC_MODE_SHIFT) 120 #define SE_CONFIG_ENC_MODE_SHA384 \ 121 ((6UL) << SE_CONFIG_ENC_MODE_SHIFT) 122 #define SE_CONFIG_ENC_MODE_SHA512 \ 123 ((7UL) << SE_CONFIG_ENC_MODE_SHIFT) 124 #define SE_CONFIG_ENC_MODE(x)\ 125 ((x) & ((0xFFUL) << SE_CONFIG_ENC_MODE_SHIFT)) 126 127 #define SE_CONFIG_DEC_MODE_SHIFT 16 128 #define SE_CONFIG_DEC_MODE_KEY128 \ 129 ((0UL) << SE_CONFIG_DEC_MODE_SHIFT) 130 #define SE_CONFIG_DEC_MODE_KEY192 \ 131 ((1UL) << SE_CONFIG_DEC_MODE_SHIFT) 132 #define SE_CONFIG_DEC_MODE_KEY256 \ 133 ((2UL) << SE_CONFIG_DEC_MODE_SHIFT) 134 #define SE_CONFIG_DEC_MODE_SHA1 \ 135 ((0UL) << SE_CONFIG_DEC_MODE_SHIFT) 136 #define SE_CONFIG_DEC_MODE_SHA224 \ 137 ((4UL) << SE_CONFIG_DEC_MODE_SHIFT) 138 #define SE_CONFIG_DEC_MODE_SHA256 \ 139 ((5UL) << SE_CONFIG_DEC_MODE_SHIFT) 140 #define SE_CONFIG_DEC_MODE_SHA384 \ 141 ((6UL) << SE_CONFIG_DEC_MODE_SHIFT) 142 #define SE_CONFIG_DEC_MODE_SHA512 \ 143 ((7UL) << SE_CONFIG_DEC_MODE_SHIFT) 144 #define SE_CONFIG_DEC_MODE(x)\ 145 ((x) & ((0xFFUL) << SE_CONFIG_DEC_MODE_SHIFT)) 146 147 148 /* DRBG random number generator config */ 149 #define SE_RNG_CONFIG_REG_OFFSET 0x340 150 151 #define DRBG_MODE_SHIFT 0 152 #define DRBG_MODE_NORMAL \ 153 ((0U) << DRBG_MODE_SHIFT) 154 #define DRBG_MODE_FORCE_INSTANTION \ 155 ((1U) << DRBG_MODE_SHIFT) 156 #define DRBG_MODE_FORCE_RESEED \ 157 ((2U) << DRBG_MODE_SHIFT) 158 #define SE_RNG_CONFIG_MODE(x) \ 159 ((x) & ((0x3U) << DRBG_MODE_SHIFT)) 160 161 #define DRBG_SRC_SHIFT 2 162 #define DRBG_SRC_NONE \ 163 ((0U) << DRBG_SRC_SHIFT) 164 #define DRBG_SRC_ENTROPY \ 165 ((1U) << DRBG_SRC_SHIFT) 166 #define DRBG_SRC_LFSR \ 167 ((2U) << DRBG_SRC_SHIFT) 168 #define SE_RNG_SRC_CONFIG_MODE(x) \ 169 ((x) & ((0x3U) << DRBG_SRC_SHIFT)) 170 171 /* DRBG random number generator entropy config */ 172 173 #define SE_RNG_SRC_CONFIG_REG_OFFSET 0x344U 174 175 #define DRBG_RO_ENT_SRC_SHIFT 1 176 #define DRBG_RO_ENT_SRC_ENABLE \ 177 ((1U) << DRBG_RO_ENT_SRC_SHIFT) 178 #define DRBG_RO_ENT_SRC_DISABLE \ 179 ((0U) << DRBG_RO_ENT_SRC_SHIFT) 180 #define SE_RNG_SRC_CONFIG_RO_ENT_SRC(x) \ 181 ((x) & ((0x1U) << DRBG_RO_ENT_SRC_SHIFT)) 182 183 #define DRBG_RO_ENT_SRC_LOCK_SHIFT 0 184 #define DRBG_RO_ENT_SRC_LOCK_ENABLE \ 185 ((1U) << DRBG_RO_ENT_SRC_LOCK_SHIFT) 186 #define DRBG_RO_ENT_SRC_LOCK_DISABLE \ 187 ((0U) << DRBG_RO_ENT_SRC_LOCK_SHIFT) 188 #define SE_RNG_SRC_CONFIG_RO_ENT_SRC_LOCK(x) \ 189 ((x) & ((0x1U) << DRBG_RO_ENT_SRC_LOCK_SHIFT)) 190 191 #define DRBG_RO_ENT_IGNORE_MEM_SHIFT 12 192 #define DRBG_RO_ENT_IGNORE_MEM_ENABLE \ 193 ((1U) << DRBG_RO_ENT_IGNORE_MEM_SHIFT) 194 #define DRBG_RO_ENT_IGNORE_MEM_DISABLE \ 195 ((0U) << DRBG_RO_ENT_IGNORE_MEM_SHIFT) 196 #define SE_RNG_SRC_CONFIG_RO_ENT_IGNORE_MEM(x) \ 197 ((x) & ((0x1U) << DRBG_RO_ENT_IGNORE_MEM_SHIFT)) 198 199 #define SE_RNG_RESEED_INTERVAL_REG_OFFSET 0x348 200 201 /* SE CRYPTO */ 202 #define SE_CRYPTO_REG_OFFSET 0x304 203 #define SE_CRYPTO_HASH_SHIFT 0 204 #define SE_CRYPTO_HASH_DISABLE \ 205 ((0U) << SE_CRYPTO_HASH_SHIFT) 206 #define SE_CRYPTO_HASH_ENABLE \ 207 ((1U) << SE_CRYPTO_HASH_SHIFT) 208 209 #define SE_CRYPTO_XOR_POS_SHIFT 1 210 #define SE_CRYPTO_XOR_BYPASS \ 211 ((0U) << SE_CRYPTO_XOR_POS_SHIFT) 212 #define SE_CRYPTO_XOR_TOP \ 213 ((2U) << SE_CRYPTO_XOR_POS_SHIFT) 214 #define SE_CRYPTO_XOR_BOTTOM \ 215 ((3U) << SE_CRYPTO_XOR_POS_SHIFT) 216 217 #define SE_CRYPTO_INPUT_SEL_SHIFT 3 218 #define SE_CRYPTO_INPUT_AHB \ 219 ((0U) << SE_CRYPTO_INPUT_SEL_SHIFT) 220 #define SE_CRYPTO_INPUT_RANDOM \ 221 ((1U) << SE_CRYPTO_INPUT_SEL_SHIFT) 222 #define SE_CRYPTO_INPUT_AESOUT \ 223 ((2U) << SE_CRYPTO_INPUT_SEL_SHIFT) 224 #define SE_CRYPTO_INPUT_LNR_CTR \ 225 ((3U) << SE_CRYPTO_INPUT_SEL_SHIFT) 226 227 #define SE_CRYPTO_VCTRAM_SEL_SHIFT 5 228 #define SE_CRYPTO_VCTRAM_AHB \ 229 ((0U) << SE_CRYPTO_VCTRAM_SEL_SHIFT) 230 #define SE_CRYPTO_VCTRAM_AESOUT \ 231 ((2U) << SE_CRYPTO_VCTRAM_SEL_SHIFT) 232 #define SE_CRYPTO_VCTRAM_PREVAHB \ 233 ((3U) << SE_CRYPTO_VCTRAM_SEL_SHIFT) 234 235 #define SE_CRYPTO_IV_SEL_SHIFT 7 236 #define SE_CRYPTO_IV_ORIGINAL \ 237 ((0U) << SE_CRYPTO_IV_SEL_SHIFT) 238 #define SE_CRYPTO_IV_UPDATED \ 239 ((1U) << SE_CRYPTO_IV_SEL_SHIFT) 240 241 #define SE_CRYPTO_CORE_SEL_SHIFT 8 242 #define SE_CRYPTO_CORE_DECRYPT \ 243 ((0U) << SE_CRYPTO_CORE_SEL_SHIFT) 244 #define SE_CRYPTO_CORE_ENCRYPT \ 245 ((1U) << SE_CRYPTO_CORE_SEL_SHIFT) 246 247 #define SE_CRYPTO_KEY_INDEX_SHIFT 24 248 #define SE_CRYPTO_KEY_INDEX(x) (x << SE_CRYPTO_KEY_INDEX_SHIFT) 249 250 #define SE_CRYPTO_MEMIF_AHB \ 251 ((0U) << SE_CRYPTO_MEMIF_SHIFT) 252 #define SE_CRYPTO_MEMIF_MCCIF \ 253 ((1U) << SE_CRYPTO_MEMIF_SHIFT) 254 #define SE_CRYPTO_MEMIF_SHIFT 31 255 256 /* KEY TABLE */ 257 #define SE_KEYTABLE_REG_OFFSET 0x31C 258 259 /* KEYIV PKT - key slot */ 260 #define SE_KEYTABLE_SLOT_SHIFT 4 261 #define SE_KEYTABLE_SLOT(x) (x << SE_KEYTABLE_SLOT_SHIFT) 262 263 /* KEYIV PKT - KEYIV select */ 264 #define SE_KEYIV_PKT_KEYIV_SEL_SHIFT 3 265 #define SE_CRYPTO_KEYIV_KEY \ 266 ((0U) << SE_KEYIV_PKT_KEYIV_SEL_SHIFT) 267 #define SE_CRYPTO_KEYIV_IVS \ 268 ((1U) << SE_KEYIV_PKT_KEYIV_SEL_SHIFT) 269 270 /* KEYIV PKT - IV select */ 271 #define SE_KEYIV_PKT_IV_SEL_SHIFT 2 272 #define SE_CRYPTO_KEYIV_IVS_OIV \ 273 ((0U) << SE_KEYIV_PKT_IV_SEL_SHIFT) 274 #define SE_CRYPTO_KEYIV_IVS_UIV \ 275 ((1U) << SE_KEYIV_PKT_IV_SEL_SHIFT) 276 277 /* KEYIV PKT - key word */ 278 #define SE_KEYIV_PKT_KEY_WORD_SHIFT 0 279 #define SE_KEYIV_PKT_KEY_WORD(x) \ 280 ((x) << SE_KEYIV_PKT_KEY_WORD_SHIFT) 281 282 /* KEYIV PKT - iv word */ 283 #define SE_KEYIV_PKT_IV_WORD_SHIFT 0 284 #define SE_KEYIV_PKT_IV_WORD(x) \ 285 ((x) << SE_KEYIV_PKT_IV_WORD_SHIFT) 286 287 /* SE OPERATION */ 288 #define SE_OPERATION_REG_OFFSET 0x8U 289 #define SE_OPERATION_SHIFT 0 290 #define SE_OP_ABORT \ 291 ((0x0U) << SE_OPERATION_SHIFT) 292 #define SE_OP_START \ 293 ((0x1U) << SE_OPERATION_SHIFT) 294 #define SE_OP_RESTART \ 295 ((0x2U) << SE_OPERATION_SHIFT) 296 #define SE_OP_CTX_SAVE \ 297 ((0x3U) << SE_OPERATION_SHIFT) 298 #define SE_OP_RESTART_IN \ 299 ((0x4U) << SE_OPERATION_SHIFT) 300 #define SE_OPERATION(x) \ 301 ((x) & ((0x7U) << SE_OPERATION_SHIFT)) 302 303 /* SE CONTEXT */ 304 #define SE_CTX_SAVE_CONFIG_REG_OFFSET 0x70 305 #define SE_CTX_SAVE_WORD_QUAD_SHIFT 0 306 #define SE_CTX_SAVE_WORD_QUAD(x) \ 307 (x << SE_CTX_SAVE_WORD_QUAD_SHIFT) 308 #define SE_CTX_SAVE_WORD_QUAD_KEYS_0_3 \ 309 ((0U) << SE_CTX_SAVE_WORD_QUAD_SHIFT) 310 #define SE_CTX_SAVE_WORD_QUAD_KEYS_4_7 \ 311 ((1U) << SE_CTX_SAVE_WORD_QUAD_SHIFT) 312 #define SE_CTX_SAVE_WORD_QUAD_ORIG_IV \ 313 ((2U) << SE_CTX_SAVE_WORD_QUAD_SHIFT) 314 #define SE_CTX_SAVE_WORD_QUAD_UPD_IV \ 315 ((3U) << SE_CTX_SAVE_WORD_QUAD_SHIFT) 316 317 #define SE_CTX_SAVE_KEY_INDEX_SHIFT 8 318 #define SE_CTX_SAVE_KEY_INDEX(x) (x << SE_CTX_SAVE_KEY_INDEX_SHIFT) 319 320 #define SE_CTX_SAVE_STICKY_WORD_QUAD_SHIFT 24 321 #define SE_CTX_SAVE_STICKY_WORD_QUAD_STICKY_0_3 \ 322 ((0U) << SE_CTX_SAVE_STICKY_WORD_QUAD_SHIFT) 323 #define SE_CTX_SAVE_STICKY_WORD_QUAD_STICKY_4_7 \ 324 ((1U) << SE_CTX_SAVE_STICKY_WORD_QUAD_SHIFT) 325 #define SE_CTX_SAVE_STICKY_WORD_QUAD(x) \ 326 (x << SE_CTX_SAVE_STICKY_WORD_QUAD_SHIFT) 327 328 #define SE_CTX_SAVE_SRC_SHIFT 29 329 #define SE_CTX_SAVE_SRC_STICKY_BITS \ 330 ((0U) << SE_CTX_SAVE_SRC_SHIFT) 331 #define SE_CTX_SAVE_SRC_RSA_KEYTABLE \ 332 ((1U) << SE_CTX_SAVE_SRC_SHIFT) 333 #define SE_CTX_SAVE_SRC_AES_KEYTABLE \ 334 ((2U) << SE_CTX_SAVE_SRC_SHIFT) 335 #define SE_CTX_SAVE_SRC_PKA1_STICKY_BITS \ 336 ((3U) << SE_CTX_SAVE_SRC_SHIFT) 337 #define SE_CTX_SAVE_SRC_MEM \ 338 ((4U) << SE_CTX_SAVE_SRC_SHIFT) 339 #define SE_CTX_SAVE_SRC_SRK \ 340 ((6U) << SE_CTX_SAVE_SRC_SHIFT) 341 #define SE_CTX_SAVE_SRC_PKA1_KEYTABLE \ 342 ((7U) << SE_CTX_SAVE_SRC_SHIFT) 343 344 #define SE_CTX_STICKY_WORD_QUAD_SHIFT 24 345 #define SE_CTX_STICKY_WORD_QUAD_WORDS_0_3 \ 346 ((0U) << SE_CTX_STICKY_WORD_QUAD_SHIFT) 347 #define SE_CTX_STICKY_WORD_QUAD_WORDS_4_7 \ 348 ((1U) << SE_CTX_STICKY_WORD_QUAD_SHIFT) 349 #define SE_CTX_STICKY_WORD_QUAD(x) (x << SE_CTX_STICKY_WORD_QUAD_SHIFT) 350 351 #define SE_CTX_SAVE_RSA_KEY_INDEX_SHIFT 16 352 #define SE_CTX_SAVE_RSA_KEY_INDEX(x) \ 353 (x << SE_CTX_SAVE_RSA_KEY_INDEX_SHIFT) 354 355 #define SE_CTX_RSA_WORD_QUAD_SHIFT 12 356 #define SE_CTX_RSA_WORD_QUAD(x) \ 357 (x << SE_CTX_RSA_WORD_QUAD_SHIFT) 358 359 #define SE_CTX_PKA1_WORD_QUAD_L_SHIFT 0 360 #define SE_CTX_PKA1_WORD_QUAD_L_SIZE \ 361 ((true ? 4:0) - \ 362 (false ? 4:0) + 1) 363 #define SE_CTX_PKA1_WORD_QUAD_L(x)\ 364 (((x) << SE_CTX_PKA1_WORD_QUAD_L_SHIFT) & 0x1f) 365 366 #define SE_CTX_PKA1_WORD_QUAD_H_SHIFT 12 367 #define SE_CTX_PKA1_WORD_QUAD_H(x)\ 368 ((((x) >> SE_CTX_PKA1_WORD_QUAD_L_SIZE) & 0xf) \ 369 << SE_CTX_PKA1_WORD_QUAD_H_SHIFT) 370 371 #define SE_RSA_KEY_INDEX_SLOT0_EXP 0 372 #define SE_RSA_KEY_INDEX_SLOT0_MOD 1 373 #define SE_RSA_KEY_INDEX_SLOT1_EXP 2 374 #define SE_RSA_KEY_INDEX_SLOT1_MOD 3 375 376 377 /* SE_CTX_SAVE_AUTO */ 378 #define SE_CTX_SAVE_AUTO_REG_OFFSET 0x74U 379 380 /* Enable */ 381 #define SE_CTX_SAVE_AUTO_ENABLE_SHIFT 0 382 #define SE_CTX_SAVE_AUTO_DIS \ 383 ((0U) << SE_CTX_SAVE_AUTO_ENABLE_SHIFT) 384 #define SE_CTX_SAVE_AUTO_EN \ 385 ((1U) << SE_CTX_SAVE_AUTO_ENABLE_SHIFT) 386 #define SE_CTX_SAVE_AUTO_ENABLE(x) \ 387 ((x) & ((0x1U) << SE_CTX_SAVE_AUTO_ENABLE_SHIFT)) 388 389 /* Lock */ 390 #define SE_CTX_SAVE_AUTO_LOCK_SHIFT 8 391 #define SE_CTX_SAVE_AUTO_LOCK_EN \ 392 ((1U) << SE_CTX_SAVE_AUTO_LOCK_SHIFT) 393 #define SE_CTX_SAVE_AUTO_LOCK_DIS \ 394 ((0U) << SE_CTX_SAVE_AUTO_LOCK_SHIFT) 395 #define SE_CTX_SAVE_AUTO_LOCK(x) \ 396 ((x) & ((0x1U) << SE_CTX_SAVE_AUTO_LOCK_SHIFT)) 397 398 /* Current context save number of blocks*/ 399 #define SE_CTX_SAVE_AUTO_CURR_CNT_SHIFT 16 400 #define SE_CTX_SAVE_AUTO_CURR_CNT_MASK 0x3FFU 401 #define SE_CTX_SAVE_GET_BLK_COUNT(x) \ 402 (((x) >> SE_CTX_SAVE_AUTO_CURR_CNT_SHIFT) & \ 403 SE_CTX_SAVE_AUTO_CURR_CNT_MASK) 404 405 #define SE_CTX_SAVE_SIZE_BLOCKS_SE1 133 406 #define SE_CTX_SAVE_SIZE_BLOCKS_SE2 646 407 408 /* SE TZRAM OPERATION - only for SE1 */ 409 #define SE_TZRAM_OPERATION 0x540U 410 411 #define SE_TZRAM_OP_MODE_SHIFT 1 412 #define SE_TZRAM_OP_COMMAND_INIT 1 413 #define SE_TZRAM_OP_COMMAND_SHIFT 0 414 #define SE_TZRAM_OP_MODE_SAVE \ 415 ((0U) << SE_TZRAM_OP_MODE_SHIFT) 416 #define SE_TZRAM_OP_MODE_RESTORE \ 417 ((1U) << SE_TZRAM_OP_MODE_SHIFT) 418 #define SE_TZRAM_OP_MODE(x) \ 419 ((x) & ((0x1U) << SE_TZRAM_OP_MODE_SHIFT)) 420 421 #define SE_TZRAM_OP_BUSY_SHIFT 2 422 #define SE_TZRAM_OP_BUSY_OFF \ 423 ((0U) << SE_TZRAM_OP_BUSY_SHIFT) 424 #define SE_TZRAM_OP_BUSY_ON \ 425 ((1U) << SE_TZRAM_OP_BUSY_SHIFT) 426 #define SE_TZRAM_OP_BUSY(x) \ 427 ((x) & ((0x1U) << SE_TZRAM_OP_BUSY_SHIFT)) 428 429 #define SE_TZRAM_OP_REQ_SHIFT 0 430 #define SE_TZRAM_OP_REQ_IDLE \ 431 ((0U) << SE_TZRAM_OP_REQ_SHIFT) 432 #define SE_TZRAM_OP_REQ_INIT \ 433 ((1U) << SE_TZRAM_OP_REQ_SHIFT) 434 #define SE_TZRAM_OP_REQ(x) \ 435 ((x) & ((0x1U) << SE_TZRAM_OP_REQ_SHIFT)) 436 437 /* SE Interrupt */ 438 #define SE_INT_STATUS_REG_OFFSET 0x10U 439 #define SE_INT_OP_DONE_SHIFT 4 440 #define SE_INT_OP_DONE_CLEAR \ 441 ((0U) << SE_INT_OP_DONE_SHIFT) 442 #define SE_INT_OP_DONE_ACTIVE \ 443 ((1U) << SE_INT_OP_DONE_SHIFT) 444 #define SE_INT_OP_DONE(x) \ 445 ((x) & ((0x1U) << SE_INT_OP_DONE_SHIFT)) 446 447 /* SE TZRAM SECURITY */ 448 #define SE_TZRAM_SEC_REG_OFFSET 0x4 449 450 #define SE_TZRAM_SEC_SETTING_SHIFT 0 451 #define SE_TZRAM_SECURE \ 452 ((0UL) << SE_TZRAM_SEC_SETTING_SHIFT) 453 #define SE_TZRAM_NONSECURE \ 454 ((1UL) << SE_TZRAM_SEC_SETTING_SHIFT) 455 #define SE_TZRAM_SEC_SETTING(x) \ 456 ((x) & ((0x1UL) << SE_TZRAM_SEC_SETTING_SHIFT)) 457 458 /* PKA1 KEY SLOTS */ 459 #define TEGRA_SE_PKA1_KEYSLOT_COUNT 4 460 461 462 /* SE error status */ 463 #define SE_ERR_STATUS_REG_OFFSET 0x804U 464 #define SE_CRYPTO_KEYTABLE_DST_REG_OFFSET 0x330 465 #define SE_CRYPTO_KEYTABLE_DST_WORD_QUAD_SHIFT 0 466 #define SE_CRYPTO_KEYTABLE_DST_WORD_QUAD(x) \ 467 (x << SE_CRYPTO_KEYTABLE_DST_WORD_QUAD_SHIFT) 468 469 #define SE_KEY_INDEX_SHIFT 8 470 #define SE_CRYPTO_KEYTABLE_DST_KEY_INDEX(x) (x << SE_KEY_INDEX_SHIFT) 471 472 473 /* SE linked list (LL) register */ 474 #define SE_IN_LL_ADDR_REG_OFFSET 0x18U 475 #define SE_OUT_LL_ADDR_REG_OFFSET 0x24U 476 #define SE_BLOCK_COUNT_REG_OFFSET 0x318U 477 478 /* AES data sizes */ 479 #define TEGRA_SE_KEY_256_SIZE 32 480 #define TEGRA_SE_KEY_192_SIZE 24 481 #define TEGRA_SE_KEY_128_SIZE 16 482 #define TEGRA_SE_AES_BLOCK_SIZE 16 483 #define TEGRA_SE_AES_MIN_KEY_SIZE 16 484 #define TEGRA_SE_AES_MAX_KEY_SIZE 32 485 #define TEGRA_SE_AES_IV_SIZE 16 486 487 #define TEGRA_SE_RNG_IV_SIZE 16 488 #define TEGRA_SE_RNG_DT_SIZE 16 489 #define TEGRA_SE_RNG_KEY_SIZE 16 490 #define TEGRA_SE_RNG_SEED_SIZE (TEGRA_SE_RNG_IV_SIZE + \ 491 TEGRA_SE_RNG_KEY_SIZE + \ 492 TEGRA_SE_RNG_DT_SIZE) 493 #define TEGRA_SE_RSA512_DIGEST_SIZE 64 494 #define TEGRA_SE_RSA1024_DIGEST_SIZE 128 495 #define TEGRA_SE_RSA1536_DIGEST_SIZE 192 496 #define TEGRA_SE_RSA2048_DIGEST_SIZE 256 497 498 #define SE_KEY_TABLE_ACCESS_REG_OFFSET 0x284 499 #define SE_KEY_READ_DISABLE_SHIFT 0 500 501 #define SE_CTX_BUFER_SIZE 1072 502 #define SE_CTX_DRBG_BUFER_SIZE 2112 503 504 /* SE blobs size in bytes */ 505 #define SE_CTX_SAVE_RSA_KEY_LENGTH 1024 506 #define SE_CTX_SAVE_RANDOM_DATA_SIZE 16 507 #define SE_CTX_SAVE_STICKY_BITS_SIZE 16 508 #define SE2_CONTEXT_SAVE_PKA1_STICKY_BITS_LENGTH 16 509 #define SE2_CONTEXT_SAVE_PKA1_KEYS_LENGTH 8192 510 #define SE_CTX_KNOWN_PATTERN_SIZE 16 511 #define SE_CTX_KNOWN_PATTERN_SIZE_WORDS (SE_CTX_KNOWN_PATTERN_SIZE/4) 512 513 /* SE RSA */ 514 #define TEGRA_SE_RSA_KEYSLOT_COUNT 2 515 #define SE_RSA_KEY_SIZE_REG_OFFSET 0x404 516 #define SE_RSA_EXP_SIZE_REG_OFFSET 0x408 517 #define SE_RSA_MAX_EXP_BIT_SIZE 2048 518 #define SE_RSA_MAX_EXP_SIZE32 \ 519 (SE_RSA_MAX_EXP_BIT_SIZE >> 5) 520 #define SE_RSA_MAX_MOD_BIT_SIZE 2048 521 #define SE_RSA_MAX_MOD_SIZE32 \ 522 (SE_RSA_MAX_MOD_BIT_SIZE >> 5) 523 524 /* SE_RSA_KEYTABLE_ADDR */ 525 #define SE_RSA_KEYTABLE_ADDR 0x420 526 #define RSA_KEY_PKT_WORD_ADDR_SHIFT 0 527 #define RSA_KEY_PKT_EXPMOD_SEL_SHIFT \ 528 ((6U) << RSA_KEY_PKT_WORD_ADDR_SHIFT) 529 #define RSA_KEY_MOD \ 530 ((1U) << RSA_KEY_PKT_EXPMOD_SEL_SHIFT) 531 #define RSA_KEY_EXP \ 532 ((0U) << RSA_KEY_PKT_EXPMOD_SEL_SHIFT) 533 #define RSA_KEY_PKT_SLOT_SHIFT 7 534 #define RSA_KEY_SLOT_1 \ 535 ((0U) << RSA_KEY_PKT_SLOT_SHIFT) 536 #define RSA_KEY_SLOT_2 \ 537 ((1U) << RSA_KEY_PKT_SLOT_SHIFT) 538 #define RSA_KEY_PKT_INPUT_MODE_SHIFT 8 539 #define RSA_KEY_REG_INPUT \ 540 ((0U) << RSA_KEY_PKT_INPUT_MODE_SHIFT) 541 #define RSA_KEY_DMA_INPUT \ 542 ((1U) << RSA_KEY_PKT_INPUT_MODE_SHIFT) 543 544 /* SE_RSA_KEYTABLE_DATA */ 545 #define SE_RSA_KEYTABLE_DATA 0x424 546 547 /* SE_RSA_CONFIG register */ 548 #define SE_RSA_CONFIG 0x400 549 #define RSA_KEY_SLOT_SHIFT 24 550 #define RSA_KEY_SLOT(x) \ 551 ((x) << RSA_KEY_SLOT_SHIFT) 552 553 /******************************************************************************* 554 * Structure definition 555 ******************************************************************************/ 556 557 /* SE context blob */ 558 #pragma pack(push, 1) 559 typedef struct tegra_aes_key_slot { 560 /* 0 - 7 AES key */ 561 uint32_t key[8]; 562 /* 8 - 11 Original IV */ 563 uint32_t oiv[4]; 564 /* 12 - 15 Updated IV */ 565 uint32_t uiv[4]; 566 } tegra_se_aes_key_slot_t; 567 #pragma pack(pop) 568 569 #pragma pack(push, 1) 570 typedef struct tegra_se_context { 571 /* random number */ 572 unsigned char rand_data[SE_CTX_SAVE_RANDOM_DATA_SIZE]; 573 /* Sticky bits */ 574 unsigned char sticky_bits[SE_CTX_SAVE_STICKY_BITS_SIZE * 2]; 575 /* AES key slots */ 576 tegra_se_aes_key_slot_t key_slots[TEGRA_SE_AES_KEYSLOT_COUNT]; 577 /* RSA key slots */ 578 unsigned char rsa_keys[SE_CTX_SAVE_RSA_KEY_LENGTH]; 579 } tegra_se_context_t; 580 #pragma pack(pop) 581 582 /* PKA context blob */ 583 #pragma pack(push, 1) 584 typedef struct tegra_pka_context { 585 unsigned char sticky_bits[SE2_CONTEXT_SAVE_PKA1_STICKY_BITS_LENGTH]; 586 unsigned char pka_keys[SE2_CONTEXT_SAVE_PKA1_KEYS_LENGTH]; 587 } tegra_pka_context_t; 588 #pragma pack(pop) 589 590 /* SE context blob */ 591 #pragma pack(push, 1) 592 typedef struct tegra_se_context_blob { 593 /* SE context */ 594 tegra_se_context_t se_ctx; 595 /* Known Pattern */ 596 unsigned char known_pattern[SE_CTX_KNOWN_PATTERN_SIZE]; 597 } tegra_se_context_blob_t; 598 #pragma pack(pop) 599 600 /* SE2 and PKA1 context blob */ 601 #pragma pack(push, 1) 602 typedef struct tegra_se2_context_blob { 603 /* SE2 context */ 604 tegra_se_context_t se_ctx; 605 /* PKA1 context */ 606 tegra_pka_context_t pka_ctx; 607 /* Known Pattern */ 608 unsigned char known_pattern[SE_CTX_KNOWN_PATTERN_SIZE]; 609 } tegra_se2_context_blob_t; 610 #pragma pack(pop) 611 612 /* SE AES key type 128bit, 192bit, 256bit */ 613 typedef enum { 614 SE_AES_KEY128, 615 SE_AES_KEY192, 616 SE_AES_KEY256, 617 } tegra_se_aes_key_type_t; 618 619 /* SE RSA key slot */ 620 typedef struct tegra_se_rsa_key_slot { 621 /* 0 - 63 exponent key */ 622 uint32_t exponent[SE_RSA_MAX_EXP_SIZE32]; 623 /* 64 - 127 modulus key */ 624 uint32_t modulus[SE_RSA_MAX_MOD_SIZE32]; 625 } tegra_se_rsa_key_slot_t; 626 627 628 /******************************************************************************* 629 * Inline functions definition 630 ******************************************************************************/ 631 632 static inline uint32_t tegra_se_read_32(const tegra_se_dev_t *dev, uint32_t offset) 633 { 634 return mmio_read_32(dev->se_base + offset); 635 } 636 637 static inline void tegra_se_write_32(const tegra_se_dev_t *dev, uint32_t offset, uint32_t val) 638 { 639 mmio_write_32(dev->se_base + offset, val); 640 } 641 642 static inline uint32_t tegra_pka_read_32(tegra_pka_dev_t *dev, uint32_t offset) 643 { 644 return mmio_read_32(dev->pka_base + offset); 645 } 646 647 static inline void tegra_pka_write_32(tegra_pka_dev_t *dev, uint32_t offset, 648 uint32_t val) 649 { 650 mmio_write_32(dev->pka_base + offset, val); 651 } 652 653 /******************************************************************************* 654 * Prototypes 655 ******************************************************************************/ 656 int tegra_se_start_normal_operation(const tegra_se_dev_t *, uint32_t); 657 int tegra_se_start_ctx_save_operation(const tegra_se_dev_t *, uint32_t); 658 659 #endif /* SE_PRIVATE_H */ 660