1# 2# Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# platform configs 8ENABLE_CONSOLE_SPE := 0 9$(eval $(call add_define,ENABLE_CONSOLE_SPE)) 10 11ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS := 0 12$(eval $(call add_define,ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS)) 13 14RELOCATE_TO_BL31_BASE := 1 15$(eval $(call add_define,RELOCATE_TO_BL31_BASE)) 16 17ENABLE_CHIP_VERIFICATION_HARNESS := 0 18$(eval $(call add_define,ENABLE_CHIP_VERIFICATION_HARNESS)) 19 20ENABLE_SMMU_DEVICE := 1 21$(eval $(call add_define,ENABLE_SMMU_DEVICE)) 22 23RESET_TO_BL31 := 1 24 25PROGRAMMABLE_RESET_ADDRESS := 1 26 27COLD_BOOT_SINGLE_CPU := 1 28 29# platform settings 30TZDRAM_BASE := 0x40000000 31$(eval $(call add_define,TZDRAM_BASE)) 32 33PLATFORM_CLUSTER_COUNT := 4 34$(eval $(call add_define,PLATFORM_CLUSTER_COUNT)) 35 36PLATFORM_MAX_CPUS_PER_CLUSTER := 2 37$(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER)) 38 39MAX_XLAT_TABLES := 25 40$(eval $(call add_define,MAX_XLAT_TABLES)) 41 42MAX_MMAP_REGIONS := 30 43$(eval $(call add_define,MAX_MMAP_REGIONS)) 44 45# platform files 46PLAT_INCLUDES += -I${SOC_DIR}/drivers/include 47 48BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \ 49 lib/cpus/aarch64/denver.S \ 50 ${COMMON_DIR}/drivers/memctrl/memctrl_v2.c \ 51 ${COMMON_DIR}/drivers/smmu/smmu.c \ 52 ${SOC_DIR}/drivers/mce/mce.c \ 53 ${SOC_DIR}/drivers/mce/nvg.c \ 54 ${SOC_DIR}/drivers/mce/aarch64/nvg_helpers.S \ 55 ${SOC_DIR}/drivers/se/se.c \ 56 ${SOC_DIR}/plat_memctrl.c \ 57 ${SOC_DIR}/plat_psci_handlers.c \ 58 ${SOC_DIR}/plat_setup.c \ 59 ${SOC_DIR}/plat_secondary.c \ 60 ${SOC_DIR}/plat_sip_calls.c \ 61 ${SOC_DIR}/plat_smmu.c \ 62 ${SOC_DIR}/plat_trampoline.S 63 64ifeq (${ENABLE_CONSOLE_SPE},1) 65BL31_SOURCES += ${COMMON_DIR}/drivers/spe/shared_console.S 66endif 67