1# 2# Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# platform configs 8ENABLE_CONSOLE_SPE := 0 9$(eval $(call add_define,ENABLE_CONSOLE_SPE)) 10 11ENABLE_STRICT_CHECKING_MODE := 1 12$(eval $(call add_define,ENABLE_STRICT_CHECKING_MODE)) 13 14RESET_TO_BL31 := 1 15 16PROGRAMMABLE_RESET_ADDRESS := 1 17 18COLD_BOOT_SINGLE_CPU := 1 19 20# platform settings 21TZDRAM_BASE := 0x40000000 22$(eval $(call add_define,TZDRAM_BASE)) 23 24PLATFORM_CLUSTER_COUNT := 4 25$(eval $(call add_define,PLATFORM_CLUSTER_COUNT)) 26 27PLATFORM_MAX_CPUS_PER_CLUSTER := 2 28$(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER)) 29 30MAX_XLAT_TABLES := 25 31$(eval $(call add_define,MAX_XLAT_TABLES)) 32 33MAX_MMAP_REGIONS := 30 34$(eval $(call add_define,MAX_MMAP_REGIONS)) 35 36# platform files 37PLAT_INCLUDES += -I${SOC_DIR}/drivers/include 38 39BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \ 40 lib/cpus/aarch64/denver.S \ 41 ${COMMON_DIR}/drivers/memctrl/memctrl_v2.c \ 42 ${COMMON_DIR}/drivers/smmu/smmu.c \ 43 ${SOC_DIR}/drivers/mce/mce.c \ 44 ${SOC_DIR}/drivers/mce/nvg.c \ 45 ${SOC_DIR}/drivers/mce/aarch64/nvg_helpers.S \ 46 ${SOC_DIR}/drivers/se/se.c \ 47 ${SOC_DIR}/plat_memctrl.c \ 48 ${SOC_DIR}/plat_psci_handlers.c \ 49 ${SOC_DIR}/plat_setup.c \ 50 ${SOC_DIR}/plat_secondary.c \ 51 ${SOC_DIR}/plat_sip_calls.c \ 52 ${SOC_DIR}/plat_smmu.c \ 53 ${SOC_DIR}/plat_trampoline.S 54 55ifeq (${ENABLE_CONSOLE_SPE},1) 56BL31_SOURCES += ${COMMON_DIR}/drivers/spe/shared_console.S 57endif 58