141612559SVarun Wadekar/* 2844e6cc5SPritesh Raithatha * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. 341612559SVarun Wadekar * 441612559SVarun Wadekar * SPDX-License-Identifier: BSD-3-Clause 541612559SVarun Wadekar */ 641612559SVarun Wadekar 741612559SVarun Wadekar#include <arch.h> 841612559SVarun Wadekar#include <asm_macros.S> 941612559SVarun Wadekar#include <plat/common/common_def.h> 1041612559SVarun Wadekar#include <memctrl_v2.h> 1141612559SVarun Wadekar#include <tegra_def.h> 1241612559SVarun Wadekar 13040529e9SVarun Wadekar#define TEGRA194_STATE_SYSTEM_SUSPEND 0x5C7 14040529e9SVarun Wadekar#define TEGRA194_STATE_SYSTEM_RESUME 0x600D 15*a391d494SPritesh Raithatha#define TEGRA194_MC_CTX_SIZE 0xFB 1641612559SVarun Wadekar 1741612559SVarun Wadekar .align 4 181c62509eSVarun Wadekar .globl tegra194_cpu_reset_handler 1941612559SVarun Wadekar 2041612559SVarun Wadekar/* CPU reset handler routine */ 211c62509eSVarun Wadekarfunc tegra194_cpu_reset_handler 22040529e9SVarun Wadekar /* check if we are exiting system suspend state */ 23040529e9SVarun Wadekar adr x0, __tegra194_system_suspend_state 24040529e9SVarun Wadekar ldr x1, [x0] 25040529e9SVarun Wadekar mov x2, #TEGRA194_STATE_SYSTEM_SUSPEND 26040529e9SVarun Wadekar lsl x2, x2, #16 27040529e9SVarun Wadekar add x2, x2, #TEGRA194_STATE_SYSTEM_SUSPEND 28040529e9SVarun Wadekar cmp x1, x2 29040529e9SVarun Wadekar bne boot_cpu 3041612559SVarun Wadekar 31040529e9SVarun Wadekar /* set system resume state */ 32040529e9SVarun Wadekar mov x1, #TEGRA194_STATE_SYSTEM_RESUME 33040529e9SVarun Wadekar lsl x1, x1, #16 34040529e9SVarun Wadekar mov x2, #TEGRA194_STATE_SYSTEM_RESUME 35040529e9SVarun Wadekar add x1, x1, x2 36040529e9SVarun Wadekar str x1, [x0] 37040529e9SVarun Wadekar dsb sy 38040529e9SVarun Wadekar 39040529e9SVarun Wadekar /* prepare to relocate to TZSRAM */ 4041612559SVarun Wadekar mov x0, #BL31_BASE 411c62509eSVarun Wadekar adr x1, __tegra194_cpu_reset_handler_end 421c62509eSVarun Wadekar adr x2, __tegra194_cpu_reset_handler_data 4341612559SVarun Wadekar ldr x2, [x2, #8] 4441612559SVarun Wadekar 4541612559SVarun Wadekar /* memcpy16 */ 4641612559SVarun Wadekarm_loop16: 4741612559SVarun Wadekar cmp x2, #16 4841612559SVarun Wadekar b.lt m_loop1 4941612559SVarun Wadekar ldp x3, x4, [x1], #16 5041612559SVarun Wadekar stp x3, x4, [x0], #16 5141612559SVarun Wadekar sub x2, x2, #16 5241612559SVarun Wadekar b m_loop16 5341612559SVarun Wadekar /* copy byte per byte */ 5441612559SVarun Wadekarm_loop1: 5541612559SVarun Wadekar cbz x2, boot_cpu 5641612559SVarun Wadekar ldrb w3, [x1], #1 5741612559SVarun Wadekar strb w3, [x0], #1 5841612559SVarun Wadekar subs x2, x2, #1 5941612559SVarun Wadekar b.ne m_loop1 6041612559SVarun Wadekar 6141612559SVarun Wadekarboot_cpu: 621c62509eSVarun Wadekar adr x0, __tegra194_cpu_reset_handler_data 6341612559SVarun Wadekar ldr x0, [x0] 6441612559SVarun Wadekar br x0 651c62509eSVarun Wadekarendfunc tegra194_cpu_reset_handler 6641612559SVarun Wadekar 6741612559SVarun Wadekar /* 681c62509eSVarun Wadekar * Tegra194 reset data (offset 0x0 - 0x2490) 6941612559SVarun Wadekar * 70ddbf946fSStefan Kristiansson * 0x0000: secure world's entrypoint 71ddbf946fSStefan Kristiansson * 0x0008: BL31 size (RO + RW) 72*a391d494SPritesh Raithatha * 0x0010: MC context start 73*a391d494SPritesh Raithatha * 0x2490: MC context end 7441612559SVarun Wadekar */ 7541612559SVarun Wadekar 7641612559SVarun Wadekar .align 4 771c62509eSVarun Wadekar .type __tegra194_cpu_reset_handler_data, %object 781c62509eSVarun Wadekar .globl __tegra194_cpu_reset_handler_data 791c62509eSVarun Wadekar__tegra194_cpu_reset_handler_data: 8041612559SVarun Wadekar .quad tegra_secure_entrypoint 8141612559SVarun Wadekar .quad __BL31_END__ - BL31_BASE 82040529e9SVarun Wadekar .globl __tegra194_system_suspend_state 83040529e9SVarun Wadekar__tegra194_system_suspend_state: 84040529e9SVarun Wadekar .quad 0 85040529e9SVarun Wadekar 86653fc380SVarun Wadekar .align 4 87*a391d494SPritesh Raithatha__tegra194_mc_context: 88*a391d494SPritesh Raithatha .rept TEGRA194_MC_CTX_SIZE 8941612559SVarun Wadekar .quad 0 9041612559SVarun Wadekar .endr 911c62509eSVarun Wadekar .size __tegra194_cpu_reset_handler_data, \ 921c62509eSVarun Wadekar . - __tegra194_cpu_reset_handler_data 9341612559SVarun Wadekar 9441612559SVarun Wadekar .align 4 951c62509eSVarun Wadekar .globl __tegra194_cpu_reset_handler_end 961c62509eSVarun Wadekar__tegra194_cpu_reset_handler_end: 97653fc380SVarun Wadekar 98653fc380SVarun Wadekar .globl tegra194_get_cpu_reset_handler_size 99653fc380SVarun Wadekar .globl tegra194_get_cpu_reset_handler_base 100*a391d494SPritesh Raithatha .globl tegra194_get_mc_ctx_offset 101040529e9SVarun Wadekar .globl tegra194_set_system_suspend_entry 102653fc380SVarun Wadekar 103653fc380SVarun Wadekar/* return size of the CPU reset handler */ 104653fc380SVarun Wadekarfunc tegra194_get_cpu_reset_handler_size 105653fc380SVarun Wadekar adr x0, __tegra194_cpu_reset_handler_end 106653fc380SVarun Wadekar adr x1, tegra194_cpu_reset_handler 107653fc380SVarun Wadekar sub x0, x0, x1 108653fc380SVarun Wadekar ret 109653fc380SVarun Wadekarendfunc tegra194_get_cpu_reset_handler_size 110653fc380SVarun Wadekar 111653fc380SVarun Wadekar/* return the start address of the CPU reset handler */ 112653fc380SVarun Wadekarfunc tegra194_get_cpu_reset_handler_base 113653fc380SVarun Wadekar adr x0, tegra194_cpu_reset_handler 114653fc380SVarun Wadekar ret 115653fc380SVarun Wadekarendfunc tegra194_get_cpu_reset_handler_base 116653fc380SVarun Wadekar 117*a391d494SPritesh Raithatha/* return the size of the MC context */ 118*a391d494SPritesh Raithathafunc tegra194_get_mc_ctx_offset 119*a391d494SPritesh Raithatha adr x0, __tegra194_mc_context 120653fc380SVarun Wadekar adr x1, tegra194_cpu_reset_handler 121653fc380SVarun Wadekar sub x0, x0, x1 122653fc380SVarun Wadekar ret 123*a391d494SPritesh Raithathaendfunc tegra194_get_mc_ctx_offset 124040529e9SVarun Wadekar 125040529e9SVarun Wadekar/* set system suspend state before SC7 entry */ 126040529e9SVarun Wadekarfunc tegra194_set_system_suspend_entry 127040529e9SVarun Wadekar mov x0, #TEGRA_MC_BASE 128040529e9SVarun Wadekar mov x3, #MC_SECURITY_CFG3_0 129040529e9SVarun Wadekar ldr w1, [x0, x3] 130040529e9SVarun Wadekar lsl x1, x1, #32 131040529e9SVarun Wadekar mov x3, #MC_SECURITY_CFG0_0 132040529e9SVarun Wadekar ldr w2, [x0, x3] 133040529e9SVarun Wadekar orr x3, x1, x2 /* TZDRAM base */ 134040529e9SVarun Wadekar adr x0, __tegra194_system_suspend_state 135040529e9SVarun Wadekar adr x1, tegra194_cpu_reset_handler 136040529e9SVarun Wadekar sub x2, x0, x1 /* offset in TZDRAM */ 137040529e9SVarun Wadekar mov x0, #TEGRA194_STATE_SYSTEM_SUSPEND 138040529e9SVarun Wadekar lsl x0, x0, #16 139040529e9SVarun Wadekar add x0, x0, #TEGRA194_STATE_SYSTEM_SUSPEND 140040529e9SVarun Wadekar str x0, [x3, x2] /* set value in TZDRAM */ 141040529e9SVarun Wadekar dsb sy 142040529e9SVarun Wadekar ret 143040529e9SVarun Wadekarendfunc tegra194_set_system_suspend_entry 144