1*41612559SVarun Wadekar/* 2*41612559SVarun Wadekar * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. 3*41612559SVarun Wadekar * 4*41612559SVarun Wadekar * SPDX-License-Identifier: BSD-3-Clause 5*41612559SVarun Wadekar */ 6*41612559SVarun Wadekar 7*41612559SVarun Wadekar#include <arch.h> 8*41612559SVarun Wadekar#include <asm_macros.S> 9*41612559SVarun Wadekar#include <plat/common/common_def.h> 10*41612559SVarun Wadekar#include <memctrl_v2.h> 11*41612559SVarun Wadekar#include <tegra_def.h> 12*41612559SVarun Wadekar 13*41612559SVarun Wadekar#define TEGRA186_SMMU_CTX_SIZE 0x420 14*41612559SVarun Wadekar 15*41612559SVarun Wadekar .align 4 16*41612559SVarun Wadekar .globl tegra186_cpu_reset_handler 17*41612559SVarun Wadekar 18*41612559SVarun Wadekar/* CPU reset handler routine */ 19*41612559SVarun Wadekarfunc tegra186_cpu_reset_handler 20*41612559SVarun Wadekar /* 21*41612559SVarun Wadekar * The TZRAM loses state during System Suspend. We use this 22*41612559SVarun Wadekar * information to decide if the reset handler is running after a 23*41612559SVarun Wadekar * System Suspend. Resume from system suspend requires restoring 24*41612559SVarun Wadekar * the entire state from TZDRAM to TZRAM. 25*41612559SVarun Wadekar */ 26*41612559SVarun Wadekar mov x0, #BL31_BASE 27*41612559SVarun Wadekar ldr x0, [x0] 28*41612559SVarun Wadekar cbnz x0, boot_cpu 29*41612559SVarun Wadekar 30*41612559SVarun Wadekar /* resume from system suspend */ 31*41612559SVarun Wadekar mov x0, #BL31_BASE 32*41612559SVarun Wadekar adr x1, __tegra186_cpu_reset_handler_end 33*41612559SVarun Wadekar adr x2, __tegra186_cpu_reset_handler_data 34*41612559SVarun Wadekar ldr x2, [x2, #8] 35*41612559SVarun Wadekar 36*41612559SVarun Wadekar /* memcpy16 */ 37*41612559SVarun Wadekarm_loop16: 38*41612559SVarun Wadekar cmp x2, #16 39*41612559SVarun Wadekar b.lt m_loop1 40*41612559SVarun Wadekar ldp x3, x4, [x1], #16 41*41612559SVarun Wadekar stp x3, x4, [x0], #16 42*41612559SVarun Wadekar sub x2, x2, #16 43*41612559SVarun Wadekar b m_loop16 44*41612559SVarun Wadekar /* copy byte per byte */ 45*41612559SVarun Wadekarm_loop1: 46*41612559SVarun Wadekar cbz x2, boot_cpu 47*41612559SVarun Wadekar ldrb w3, [x1], #1 48*41612559SVarun Wadekar strb w3, [x0], #1 49*41612559SVarun Wadekar subs x2, x2, #1 50*41612559SVarun Wadekar b.ne m_loop1 51*41612559SVarun Wadekar 52*41612559SVarun Wadekarboot_cpu: 53*41612559SVarun Wadekar adr x0, __tegra186_cpu_reset_handler_data 54*41612559SVarun Wadekar ldr x0, [x0] 55*41612559SVarun Wadekar br x0 56*41612559SVarun Wadekarendfunc tegra186_cpu_reset_handler 57*41612559SVarun Wadekar 58*41612559SVarun Wadekar /* 59*41612559SVarun Wadekar * Tegra186 reset data (offset 0x0 - 0x430) 60*41612559SVarun Wadekar * 61*41612559SVarun Wadekar * 0x000: secure world's entrypoint 62*41612559SVarun Wadekar * 0x008: BL31 size (RO + RW) 63*41612559SVarun Wadekar * 0x00C: SMMU context start 64*41612559SVarun Wadekar * 0x42C: SMMU context end 65*41612559SVarun Wadekar */ 66*41612559SVarun Wadekar 67*41612559SVarun Wadekar .align 4 68*41612559SVarun Wadekar .type __tegra186_cpu_reset_handler_data, %object 69*41612559SVarun Wadekar .globl __tegra186_cpu_reset_handler_data 70*41612559SVarun Wadekar__tegra186_cpu_reset_handler_data: 71*41612559SVarun Wadekar .quad tegra_secure_entrypoint 72*41612559SVarun Wadekar .quad __BL31_END__ - BL31_BASE 73*41612559SVarun Wadekar .globl __tegra186_smmu_ctx_start 74*41612559SVarun Wadekar__tegra186_smmu_ctx_start: 75*41612559SVarun Wadekar .rept TEGRA186_SMMU_CTX_SIZE 76*41612559SVarun Wadekar .quad 0 77*41612559SVarun Wadekar .endr 78*41612559SVarun Wadekar .size __tegra186_cpu_reset_handler_data, \ 79*41612559SVarun Wadekar . - __tegra186_cpu_reset_handler_data 80*41612559SVarun Wadekar 81*41612559SVarun Wadekar .align 4 82*41612559SVarun Wadekar .globl __tegra186_cpu_reset_handler_end 83*41612559SVarun Wadekar__tegra186_cpu_reset_handler_end: 84