141612559SVarun Wadekar/* 241612559SVarun Wadekar * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. 341612559SVarun Wadekar * 441612559SVarun Wadekar * SPDX-License-Identifier: BSD-3-Clause 541612559SVarun Wadekar */ 641612559SVarun Wadekar 741612559SVarun Wadekar#include <arch.h> 841612559SVarun Wadekar#include <asm_macros.S> 941612559SVarun Wadekar#include <plat/common/common_def.h> 1041612559SVarun Wadekar#include <memctrl_v2.h> 1141612559SVarun Wadekar#include <tegra_def.h> 1241612559SVarun Wadekar 13*1c62509eSVarun Wadekar#define TEGRA194_SMMU_CTX_SIZE 0x490 1441612559SVarun Wadekar 1541612559SVarun Wadekar .align 4 16*1c62509eSVarun Wadekar .globl tegra194_cpu_reset_handler 1741612559SVarun Wadekar 1841612559SVarun Wadekar/* CPU reset handler routine */ 19*1c62509eSVarun Wadekarfunc tegra194_cpu_reset_handler 2041612559SVarun Wadekar /* 2141612559SVarun Wadekar * The TZRAM loses state during System Suspend. We use this 2241612559SVarun Wadekar * information to decide if the reset handler is running after a 2341612559SVarun Wadekar * System Suspend. Resume from system suspend requires restoring 2441612559SVarun Wadekar * the entire state from TZDRAM to TZRAM. 2541612559SVarun Wadekar */ 2641612559SVarun Wadekar mov x0, #BL31_BASE 2741612559SVarun Wadekar ldr x0, [x0] 2841612559SVarun Wadekar cbnz x0, boot_cpu 2941612559SVarun Wadekar 3041612559SVarun Wadekar /* resume from system suspend */ 3141612559SVarun Wadekar mov x0, #BL31_BASE 32*1c62509eSVarun Wadekar adr x1, __tegra194_cpu_reset_handler_end 33*1c62509eSVarun Wadekar adr x2, __tegra194_cpu_reset_handler_data 3441612559SVarun Wadekar ldr x2, [x2, #8] 3541612559SVarun Wadekar 3641612559SVarun Wadekar /* memcpy16 */ 3741612559SVarun Wadekarm_loop16: 3841612559SVarun Wadekar cmp x2, #16 3941612559SVarun Wadekar b.lt m_loop1 4041612559SVarun Wadekar ldp x3, x4, [x1], #16 4141612559SVarun Wadekar stp x3, x4, [x0], #16 4241612559SVarun Wadekar sub x2, x2, #16 4341612559SVarun Wadekar b m_loop16 4441612559SVarun Wadekar /* copy byte per byte */ 4541612559SVarun Wadekarm_loop1: 4641612559SVarun Wadekar cbz x2, boot_cpu 4741612559SVarun Wadekar ldrb w3, [x1], #1 4841612559SVarun Wadekar strb w3, [x0], #1 4941612559SVarun Wadekar subs x2, x2, #1 5041612559SVarun Wadekar b.ne m_loop1 5141612559SVarun Wadekar 5241612559SVarun Wadekarboot_cpu: 53*1c62509eSVarun Wadekar adr x0, __tegra194_cpu_reset_handler_data 5441612559SVarun Wadekar ldr x0, [x0] 5541612559SVarun Wadekar br x0 56*1c62509eSVarun Wadekarendfunc tegra194_cpu_reset_handler 5741612559SVarun Wadekar 5841612559SVarun Wadekar /* 59*1c62509eSVarun Wadekar * Tegra194 reset data (offset 0x0 - 0x2490) 6041612559SVarun Wadekar * 61ddbf946fSStefan Kristiansson * 0x0000: secure world's entrypoint 62ddbf946fSStefan Kristiansson * 0x0008: BL31 size (RO + RW) 63ddbf946fSStefan Kristiansson * 0x0010: SMMU context start 64ddbf946fSStefan Kristiansson * 0x2490: SMMU context end 6541612559SVarun Wadekar */ 6641612559SVarun Wadekar 6741612559SVarun Wadekar .align 4 68*1c62509eSVarun Wadekar .type __tegra194_cpu_reset_handler_data, %object 69*1c62509eSVarun Wadekar .globl __tegra194_cpu_reset_handler_data 70*1c62509eSVarun Wadekar__tegra194_cpu_reset_handler_data: 7141612559SVarun Wadekar .quad tegra_secure_entrypoint 7241612559SVarun Wadekar .quad __BL31_END__ - BL31_BASE 73*1c62509eSVarun Wadekar .globl __tegra194_smmu_ctx_start 74*1c62509eSVarun Wadekar__tegra194_smmu_ctx_start: 75*1c62509eSVarun Wadekar .rept TEGRA194_SMMU_CTX_SIZE 7641612559SVarun Wadekar .quad 0 7741612559SVarun Wadekar .endr 78*1c62509eSVarun Wadekar .size __tegra194_cpu_reset_handler_data, \ 79*1c62509eSVarun Wadekar . - __tegra194_cpu_reset_handler_data 8041612559SVarun Wadekar 8141612559SVarun Wadekar .align 4 82*1c62509eSVarun Wadekar .globl __tegra194_cpu_reset_handler_end 83*1c62509eSVarun Wadekar__tegra194_cpu_reset_handler_end: 84