1 /* 2 * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <common/bl_common.h> 8 #include <common/debug.h> 9 #include <smmu.h> 10 #include <tegra_def.h> 11 #include <tegra_mc_def.h> 12 13 #define BOARD_SYSTEM_FPGA_BASE U(1) 14 #define BASE_CONFIG_SMMU_DEVICES U(2) 15 #define MAX_NUM_SMMU_DEVICES U(3) 16 17 static uint32_t tegra_misc_read_32(uint32_t off) 18 { 19 return mmio_read_32((uintptr_t)TEGRA_MISC_BASE + off); 20 } 21 22 /******************************************************************************* 23 * Array to hold SMMU context for Tegra194 24 ******************************************************************************/ 25 static __attribute__((aligned(16))) smmu_regs_t tegra194_smmu_context[] = { 26 _START_OF_TABLE_, 27 mc_make_sid_security_cfg(HDAR), 28 mc_make_sid_security_cfg(HOST1XDMAR), 29 mc_make_sid_security_cfg(NVENCSRD), 30 mc_make_sid_security_cfg(SATAR), 31 mc_make_sid_security_cfg(NVENCSWR), 32 mc_make_sid_security_cfg(HDAW), 33 mc_make_sid_security_cfg(SATAW), 34 mc_make_sid_security_cfg(ISPRA), 35 mc_make_sid_security_cfg(ISPFALR), 36 mc_make_sid_security_cfg(ISPWA), 37 mc_make_sid_security_cfg(ISPWB), 38 mc_make_sid_security_cfg(XUSB_HOSTR), 39 mc_make_sid_security_cfg(XUSB_HOSTW), 40 mc_make_sid_security_cfg(XUSB_DEVR), 41 mc_make_sid_security_cfg(XUSB_DEVW), 42 mc_make_sid_security_cfg(TSECSRD), 43 mc_make_sid_security_cfg(TSECSWR), 44 mc_make_sid_security_cfg(SDMMCRA), 45 mc_make_sid_security_cfg(SDMMCR), 46 mc_make_sid_security_cfg(SDMMCRAB), 47 mc_make_sid_security_cfg(SDMMCWA), 48 mc_make_sid_security_cfg(SDMMCW), 49 mc_make_sid_security_cfg(SDMMCWAB), 50 mc_make_sid_security_cfg(VICSRD), 51 mc_make_sid_security_cfg(VICSWR), 52 mc_make_sid_security_cfg(VIW), 53 mc_make_sid_security_cfg(NVDECSRD), 54 mc_make_sid_security_cfg(NVDECSWR), 55 mc_make_sid_security_cfg(APER), 56 mc_make_sid_security_cfg(APEW), 57 mc_make_sid_security_cfg(NVJPGSRD), 58 mc_make_sid_security_cfg(NVJPGSWR), 59 mc_make_sid_security_cfg(SESRD), 60 mc_make_sid_security_cfg(SESWR), 61 mc_make_sid_security_cfg(AXIAPR), 62 mc_make_sid_security_cfg(AXIAPW), 63 mc_make_sid_security_cfg(ETRR), 64 mc_make_sid_security_cfg(ETRW), 65 mc_make_sid_security_cfg(TSECSRDB), 66 mc_make_sid_security_cfg(TSECSWRB), 67 mc_make_sid_security_cfg(AXISR), 68 mc_make_sid_security_cfg(AXISW), 69 mc_make_sid_security_cfg(EQOSR), 70 mc_make_sid_security_cfg(EQOSW), 71 mc_make_sid_security_cfg(UFSHCR), 72 mc_make_sid_security_cfg(UFSHCW), 73 mc_make_sid_security_cfg(NVDISPLAYR), 74 mc_make_sid_security_cfg(BPMPR), 75 mc_make_sid_security_cfg(BPMPW), 76 mc_make_sid_security_cfg(BPMPDMAR), 77 mc_make_sid_security_cfg(BPMPDMAW), 78 mc_make_sid_security_cfg(AONR), 79 mc_make_sid_security_cfg(AONW), 80 mc_make_sid_security_cfg(AONDMAR), 81 mc_make_sid_security_cfg(AONDMAW), 82 mc_make_sid_security_cfg(SCER), 83 mc_make_sid_security_cfg(SCEW), 84 mc_make_sid_security_cfg(SCEDMAR), 85 mc_make_sid_security_cfg(SCEDMAW), 86 mc_make_sid_security_cfg(APEDMAR), 87 mc_make_sid_security_cfg(APEDMAW), 88 mc_make_sid_security_cfg(NVDISPLAYR1), 89 mc_make_sid_security_cfg(VICSRD1), 90 mc_make_sid_security_cfg(NVDECSRD1), 91 mc_make_sid_security_cfg(VIFALR), 92 mc_make_sid_security_cfg(VIFALW), 93 mc_make_sid_security_cfg(DLA0RDA), 94 mc_make_sid_security_cfg(DLA0FALRDB), 95 mc_make_sid_security_cfg(DLA0WRA), 96 mc_make_sid_security_cfg(DLA0FALWRB), 97 mc_make_sid_security_cfg(DLA1RDA), 98 mc_make_sid_security_cfg(DLA1FALRDB), 99 mc_make_sid_security_cfg(DLA1WRA), 100 mc_make_sid_security_cfg(DLA1FALWRB), 101 mc_make_sid_security_cfg(PVA0RDA), 102 mc_make_sid_security_cfg(PVA0RDB), 103 mc_make_sid_security_cfg(PVA0RDC), 104 mc_make_sid_security_cfg(PVA0WRA), 105 mc_make_sid_security_cfg(PVA0WRB), 106 mc_make_sid_security_cfg(PVA0WRC), 107 mc_make_sid_security_cfg(PVA1RDA), 108 mc_make_sid_security_cfg(PVA1RDB), 109 mc_make_sid_security_cfg(PVA1RDC), 110 mc_make_sid_security_cfg(PVA1WRA), 111 mc_make_sid_security_cfg(PVA1WRB), 112 mc_make_sid_security_cfg(PVA1WRC), 113 mc_make_sid_security_cfg(RCER), 114 mc_make_sid_security_cfg(RCEW), 115 mc_make_sid_security_cfg(RCEDMAR), 116 mc_make_sid_security_cfg(RCEDMAW), 117 mc_make_sid_security_cfg(NVENC1SRD), 118 mc_make_sid_security_cfg(NVENC1SWR), 119 mc_make_sid_security_cfg(PCIE0R), 120 mc_make_sid_security_cfg(PCIE0W), 121 mc_make_sid_security_cfg(PCIE1R), 122 mc_make_sid_security_cfg(PCIE1W), 123 mc_make_sid_security_cfg(PCIE2AR), 124 mc_make_sid_security_cfg(PCIE2AW), 125 mc_make_sid_security_cfg(PCIE3R), 126 mc_make_sid_security_cfg(PCIE3W), 127 mc_make_sid_security_cfg(PCIE4R), 128 mc_make_sid_security_cfg(PCIE4W), 129 mc_make_sid_security_cfg(PCIE5R), 130 mc_make_sid_security_cfg(PCIE5W), 131 mc_make_sid_security_cfg(ISPFALW), 132 mc_make_sid_security_cfg(DLA0RDA1), 133 mc_make_sid_security_cfg(DLA1RDA1), 134 mc_make_sid_security_cfg(PVA0RDA1), 135 mc_make_sid_security_cfg(PVA0RDB1), 136 mc_make_sid_security_cfg(PVA1RDA1), 137 mc_make_sid_security_cfg(PVA1RDB1), 138 mc_make_sid_security_cfg(PCIE5R1), 139 mc_make_sid_security_cfg(NVENCSRD1), 140 mc_make_sid_security_cfg(NVENC1SRD1), 141 mc_make_sid_security_cfg(ISPRA1), 142 mc_make_sid_security_cfg(MIU0R), 143 mc_make_sid_security_cfg(MIU0W), 144 mc_make_sid_security_cfg(MIU1R), 145 mc_make_sid_security_cfg(MIU1W), 146 mc_make_sid_security_cfg(MIU2R), 147 mc_make_sid_security_cfg(MIU2W), 148 mc_make_sid_security_cfg(MIU3R), 149 mc_make_sid_security_cfg(MIU3W), 150 mc_make_sid_override_cfg(HDAR), 151 mc_make_sid_override_cfg(HOST1XDMAR), 152 mc_make_sid_override_cfg(NVENCSRD), 153 mc_make_sid_override_cfg(SATAR), 154 mc_make_sid_override_cfg(NVENCSWR), 155 mc_make_sid_override_cfg(HDAW), 156 mc_make_sid_override_cfg(SATAW), 157 mc_make_sid_override_cfg(ISPRA), 158 mc_make_sid_override_cfg(ISPFALR), 159 mc_make_sid_override_cfg(ISPWA), 160 mc_make_sid_override_cfg(ISPWB), 161 mc_make_sid_override_cfg(XUSB_HOSTR), 162 mc_make_sid_override_cfg(XUSB_HOSTW), 163 mc_make_sid_override_cfg(XUSB_DEVR), 164 mc_make_sid_override_cfg(XUSB_DEVW), 165 mc_make_sid_override_cfg(TSECSRD), 166 mc_make_sid_override_cfg(TSECSWR), 167 mc_make_sid_override_cfg(SDMMCRA), 168 mc_make_sid_override_cfg(SDMMCR), 169 mc_make_sid_override_cfg(SDMMCRAB), 170 mc_make_sid_override_cfg(SDMMCWA), 171 mc_make_sid_override_cfg(SDMMCW), 172 mc_make_sid_override_cfg(SDMMCWAB), 173 mc_make_sid_override_cfg(VICSRD), 174 mc_make_sid_override_cfg(VICSWR), 175 mc_make_sid_override_cfg(VIW), 176 mc_make_sid_override_cfg(NVDECSRD), 177 mc_make_sid_override_cfg(NVDECSWR), 178 mc_make_sid_override_cfg(APER), 179 mc_make_sid_override_cfg(APEW), 180 mc_make_sid_override_cfg(NVJPGSRD), 181 mc_make_sid_override_cfg(NVJPGSWR), 182 mc_make_sid_override_cfg(SESRD), 183 mc_make_sid_override_cfg(SESWR), 184 mc_make_sid_override_cfg(AXIAPR), 185 mc_make_sid_override_cfg(AXIAPW), 186 mc_make_sid_override_cfg(ETRR), 187 mc_make_sid_override_cfg(ETRW), 188 mc_make_sid_override_cfg(TSECSRDB), 189 mc_make_sid_override_cfg(TSECSWRB), 190 mc_make_sid_override_cfg(AXISR), 191 mc_make_sid_override_cfg(AXISW), 192 mc_make_sid_override_cfg(EQOSR), 193 mc_make_sid_override_cfg(EQOSW), 194 mc_make_sid_override_cfg(UFSHCR), 195 mc_make_sid_override_cfg(UFSHCW), 196 mc_make_sid_override_cfg(NVDISPLAYR), 197 mc_make_sid_override_cfg(BPMPR), 198 mc_make_sid_override_cfg(BPMPW), 199 mc_make_sid_override_cfg(BPMPDMAR), 200 mc_make_sid_override_cfg(BPMPDMAW), 201 mc_make_sid_override_cfg(AONR), 202 mc_make_sid_override_cfg(AONW), 203 mc_make_sid_override_cfg(AONDMAR), 204 mc_make_sid_override_cfg(AONDMAW), 205 mc_make_sid_override_cfg(SCER), 206 mc_make_sid_override_cfg(SCEW), 207 mc_make_sid_override_cfg(SCEDMAR), 208 mc_make_sid_override_cfg(SCEDMAW), 209 mc_make_sid_override_cfg(APEDMAR), 210 mc_make_sid_override_cfg(APEDMAW), 211 mc_make_sid_override_cfg(NVDISPLAYR1), 212 mc_make_sid_override_cfg(VICSRD1), 213 mc_make_sid_override_cfg(NVDECSRD1), 214 mc_make_sid_override_cfg(VIFALR), 215 mc_make_sid_override_cfg(VIFALW), 216 mc_make_sid_override_cfg(DLA0RDA), 217 mc_make_sid_override_cfg(DLA0FALRDB), 218 mc_make_sid_override_cfg(DLA0WRA), 219 mc_make_sid_override_cfg(DLA0FALWRB), 220 mc_make_sid_override_cfg(DLA1RDA), 221 mc_make_sid_override_cfg(DLA1FALRDB), 222 mc_make_sid_override_cfg(DLA1WRA), 223 mc_make_sid_override_cfg(DLA1FALWRB), 224 mc_make_sid_override_cfg(PVA0RDA), 225 mc_make_sid_override_cfg(PVA0RDB), 226 mc_make_sid_override_cfg(PVA0RDC), 227 mc_make_sid_override_cfg(PVA0WRA), 228 mc_make_sid_override_cfg(PVA0WRB), 229 mc_make_sid_override_cfg(PVA0WRC), 230 mc_make_sid_override_cfg(PVA1RDA), 231 mc_make_sid_override_cfg(PVA1RDB), 232 mc_make_sid_override_cfg(PVA1RDC), 233 mc_make_sid_override_cfg(PVA1WRA), 234 mc_make_sid_override_cfg(PVA1WRB), 235 mc_make_sid_override_cfg(PVA1WRC), 236 mc_make_sid_override_cfg(RCER), 237 mc_make_sid_override_cfg(RCEW), 238 mc_make_sid_override_cfg(RCEDMAR), 239 mc_make_sid_override_cfg(RCEDMAW), 240 mc_make_sid_override_cfg(NVENC1SRD), 241 mc_make_sid_override_cfg(NVENC1SWR), 242 mc_make_sid_override_cfg(PCIE0R), 243 mc_make_sid_override_cfg(PCIE0W), 244 mc_make_sid_override_cfg(PCIE1R), 245 mc_make_sid_override_cfg(PCIE1W), 246 mc_make_sid_override_cfg(PCIE2AR), 247 mc_make_sid_override_cfg(PCIE2AW), 248 mc_make_sid_override_cfg(PCIE3R), 249 mc_make_sid_override_cfg(PCIE3W), 250 mc_make_sid_override_cfg(PCIE4R), 251 mc_make_sid_override_cfg(PCIE4W), 252 mc_make_sid_override_cfg(PCIE5R), 253 mc_make_sid_override_cfg(PCIE5W), 254 mc_make_sid_override_cfg(ISPFALW), 255 mc_make_sid_override_cfg(DLA0RDA1), 256 mc_make_sid_override_cfg(DLA1RDA1), 257 mc_make_sid_override_cfg(PVA0RDA1), 258 mc_make_sid_override_cfg(PVA0RDB1), 259 mc_make_sid_override_cfg(PVA1RDA1), 260 mc_make_sid_override_cfg(PVA1RDB1), 261 mc_make_sid_override_cfg(PCIE5R1), 262 mc_make_sid_override_cfg(NVENCSRD1), 263 mc_make_sid_override_cfg(NVENC1SRD1), 264 mc_make_sid_override_cfg(ISPRA1), 265 mc_make_sid_override_cfg(MIU0R), 266 mc_make_sid_override_cfg(MIU0W), 267 mc_make_sid_override_cfg(MIU1R), 268 mc_make_sid_override_cfg(MIU1W), 269 mc_make_sid_override_cfg(MIU2R), 270 mc_make_sid_override_cfg(MIU2W), 271 mc_make_sid_override_cfg(MIU3R), 272 mc_make_sid_override_cfg(MIU3W), 273 smmu_make_gnsr0_nsec_cfg(CR0), 274 smmu_make_gnsr0_sec_cfg(IDR0), 275 smmu_make_gnsr0_sec_cfg(IDR1), 276 smmu_make_gnsr0_sec_cfg(IDR2), 277 smmu_make_gnsr0_nsec_cfg(GFSR), 278 smmu_make_gnsr0_nsec_cfg(GFSYNR0), 279 smmu_make_gnsr0_nsec_cfg(GFSYNR1), 280 smmu_make_gnsr0_nsec_cfg(TLBGSTATUS), 281 smmu_make_gnsr0_nsec_cfg(PIDR2), 282 smmu_make_smrg_group(0), 283 smmu_make_smrg_group(1), 284 smmu_make_smrg_group(2), 285 smmu_make_smrg_group(3), 286 smmu_make_smrg_group(4), 287 smmu_make_smrg_group(5), 288 smmu_make_smrg_group(6), 289 smmu_make_smrg_group(7), 290 smmu_make_smrg_group(8), 291 smmu_make_smrg_group(9), 292 smmu_make_smrg_group(10), 293 smmu_make_smrg_group(11), 294 smmu_make_smrg_group(12), 295 smmu_make_smrg_group(13), 296 smmu_make_smrg_group(14), 297 smmu_make_smrg_group(15), 298 smmu_make_smrg_group(16), 299 smmu_make_smrg_group(17), 300 smmu_make_smrg_group(18), 301 smmu_make_smrg_group(19), 302 smmu_make_smrg_group(20), 303 smmu_make_smrg_group(21), 304 smmu_make_smrg_group(22), 305 smmu_make_smrg_group(23), 306 smmu_make_smrg_group(24), 307 smmu_make_smrg_group(25), 308 smmu_make_smrg_group(26), 309 smmu_make_smrg_group(27), 310 smmu_make_smrg_group(28), 311 smmu_make_smrg_group(29), 312 smmu_make_smrg_group(30), 313 smmu_make_smrg_group(31), 314 smmu_make_smrg_group(32), 315 smmu_make_smrg_group(33), 316 smmu_make_smrg_group(34), 317 smmu_make_smrg_group(35), 318 smmu_make_smrg_group(36), 319 smmu_make_smrg_group(37), 320 smmu_make_smrg_group(38), 321 smmu_make_smrg_group(39), 322 smmu_make_smrg_group(40), 323 smmu_make_smrg_group(41), 324 smmu_make_smrg_group(42), 325 smmu_make_smrg_group(43), 326 smmu_make_smrg_group(44), 327 smmu_make_smrg_group(45), 328 smmu_make_smrg_group(46), 329 smmu_make_smrg_group(47), 330 smmu_make_smrg_group(48), 331 smmu_make_smrg_group(49), 332 smmu_make_smrg_group(50), 333 smmu_make_smrg_group(51), 334 smmu_make_smrg_group(52), 335 smmu_make_smrg_group(53), 336 smmu_make_smrg_group(54), 337 smmu_make_smrg_group(55), 338 smmu_make_smrg_group(56), 339 smmu_make_smrg_group(57), 340 smmu_make_smrg_group(58), 341 smmu_make_smrg_group(59), 342 smmu_make_smrg_group(60), 343 smmu_make_smrg_group(61), 344 smmu_make_smrg_group(62), 345 smmu_make_smrg_group(63), 346 smmu_make_cb_group(0), 347 smmu_make_cb_group(1), 348 smmu_make_cb_group(2), 349 smmu_make_cb_group(3), 350 smmu_make_cb_group(4), 351 smmu_make_cb_group(5), 352 smmu_make_cb_group(6), 353 smmu_make_cb_group(7), 354 smmu_make_cb_group(8), 355 smmu_make_cb_group(9), 356 smmu_make_cb_group(10), 357 smmu_make_cb_group(11), 358 smmu_make_cb_group(12), 359 smmu_make_cb_group(13), 360 smmu_make_cb_group(14), 361 smmu_make_cb_group(15), 362 smmu_make_cb_group(16), 363 smmu_make_cb_group(17), 364 smmu_make_cb_group(18), 365 smmu_make_cb_group(19), 366 smmu_make_cb_group(20), 367 smmu_make_cb_group(21), 368 smmu_make_cb_group(22), 369 smmu_make_cb_group(23), 370 smmu_make_cb_group(24), 371 smmu_make_cb_group(25), 372 smmu_make_cb_group(26), 373 smmu_make_cb_group(27), 374 smmu_make_cb_group(28), 375 smmu_make_cb_group(29), 376 smmu_make_cb_group(30), 377 smmu_make_cb_group(31), 378 smmu_make_cb_group(32), 379 smmu_make_cb_group(33), 380 smmu_make_cb_group(34), 381 smmu_make_cb_group(35), 382 smmu_make_cb_group(36), 383 smmu_make_cb_group(37), 384 smmu_make_cb_group(38), 385 smmu_make_cb_group(39), 386 smmu_make_cb_group(40), 387 smmu_make_cb_group(41), 388 smmu_make_cb_group(42), 389 smmu_make_cb_group(43), 390 smmu_make_cb_group(44), 391 smmu_make_cb_group(45), 392 smmu_make_cb_group(46), 393 smmu_make_cb_group(47), 394 smmu_make_cb_group(48), 395 smmu_make_cb_group(49), 396 smmu_make_cb_group(50), 397 smmu_make_cb_group(51), 398 smmu_make_cb_group(52), 399 smmu_make_cb_group(53), 400 smmu_make_cb_group(54), 401 smmu_make_cb_group(55), 402 smmu_make_cb_group(56), 403 smmu_make_cb_group(57), 404 smmu_make_cb_group(58), 405 smmu_make_cb_group(59), 406 smmu_make_cb_group(60), 407 smmu_make_cb_group(61), 408 smmu_make_cb_group(62), 409 smmu_make_cb_group(63), 410 smmu_bypass_cfg, /* TBU settings */ 411 _END_OF_TABLE_, 412 }; 413 414 /******************************************************************************* 415 * Handler to return the pointer to the SMMU's context struct 416 ******************************************************************************/ 417 smmu_regs_t *plat_get_smmu_ctx(void) 418 { 419 /* index of _END_OF_TABLE_ */ 420 tegra194_smmu_context[0].val = (uint32_t)ARRAY_SIZE(tegra194_smmu_context) - 1U; 421 422 return tegra194_smmu_context; 423 } 424 425 /******************************************************************************* 426 * Handler to return the support SMMU devices number 427 ******************************************************************************/ 428 uint32_t plat_get_num_smmu_devices(void) 429 { 430 uint32_t ret_num = MAX_NUM_SMMU_DEVICES; 431 uint32_t board_revid = ((tegra_misc_read_32(MISCREG_EMU_REVID) >> \ 432 BOARD_SHIFT_BITS) & BOARD_MASK_BITS); 433 434 if (board_revid == BOARD_SYSTEM_FPGA_BASE) { 435 ret_num = BASE_CONFIG_SMMU_DEVICES; 436 } 437 438 return ret_num; 439 } 440