1 /* 2 * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <common/bl_common.h> 8 #include <common/debug.h> 9 #include <smmu.h> 10 #include <tegra_def.h> 11 #include <tegra_mc_def.h> 12 13 #define BOARD_SYSTEM_FPGA_BASE U(1) 14 #define BASE_CONFIG_SMMU_DEVICES U(2) 15 #define MAX_NUM_SMMU_DEVICES U(3) 16 17 static uint32_t tegra_misc_read_32(uint32_t off) 18 { 19 return mmio_read_32((uintptr_t)TEGRA_MISC_BASE + off); 20 } 21 22 /******************************************************************************* 23 * Array to hold SMMU context for Tegra194 24 ******************************************************************************/ 25 static __attribute__((aligned(16))) smmu_regs_t tegra194_smmu_context[] = { 26 _START_OF_TABLE_, 27 mc_make_sid_security_cfg(HDAR), 28 mc_make_sid_security_cfg(HOST1XDMAR), 29 mc_make_sid_security_cfg(NVENCSRD), 30 mc_make_sid_security_cfg(SATAR), 31 mc_make_sid_security_cfg(NVENCSWR), 32 mc_make_sid_security_cfg(HDAW), 33 mc_make_sid_security_cfg(SATAW), 34 mc_make_sid_security_cfg(ISPRA), 35 mc_make_sid_security_cfg(ISPFALR), 36 mc_make_sid_security_cfg(ISPWA), 37 mc_make_sid_security_cfg(ISPWB), 38 mc_make_sid_security_cfg(XUSB_HOSTR), 39 mc_make_sid_security_cfg(XUSB_HOSTW), 40 mc_make_sid_security_cfg(XUSB_DEVR), 41 mc_make_sid_security_cfg(XUSB_DEVW), 42 mc_make_sid_security_cfg(TSECSRD), 43 mc_make_sid_security_cfg(TSECSWR), 44 mc_make_sid_security_cfg(SDMMCRA), 45 mc_make_sid_security_cfg(SDMMCR), 46 mc_make_sid_security_cfg(SDMMCRAB), 47 mc_make_sid_security_cfg(SDMMCWA), 48 mc_make_sid_security_cfg(SDMMCW), 49 mc_make_sid_security_cfg(SDMMCWAB), 50 mc_make_sid_security_cfg(VICSRD), 51 mc_make_sid_security_cfg(VICSWR), 52 mc_make_sid_security_cfg(VIW), 53 mc_make_sid_security_cfg(NVDECSRD), 54 mc_make_sid_security_cfg(NVDECSWR), 55 mc_make_sid_security_cfg(APER), 56 mc_make_sid_security_cfg(APEW), 57 mc_make_sid_security_cfg(NVJPGSRD), 58 mc_make_sid_security_cfg(NVJPGSWR), 59 mc_make_sid_security_cfg(SESRD), 60 mc_make_sid_security_cfg(SESWR), 61 mc_make_sid_security_cfg(AXIAPR), 62 mc_make_sid_security_cfg(AXIAPW), 63 mc_make_sid_security_cfg(ETRR), 64 mc_make_sid_security_cfg(ETRW), 65 mc_make_sid_security_cfg(TSECSRDB), 66 mc_make_sid_security_cfg(TSECSWRB), 67 mc_make_sid_security_cfg(AXISR), 68 mc_make_sid_security_cfg(AXISW), 69 mc_make_sid_security_cfg(EQOSR), 70 mc_make_sid_security_cfg(EQOSW), 71 mc_make_sid_security_cfg(UFSHCR), 72 mc_make_sid_security_cfg(UFSHCW), 73 mc_make_sid_security_cfg(NVDISPLAYR), 74 mc_make_sid_security_cfg(BPMPR), 75 mc_make_sid_security_cfg(BPMPW), 76 mc_make_sid_security_cfg(BPMPDMAR), 77 mc_make_sid_security_cfg(BPMPDMAW), 78 mc_make_sid_security_cfg(AONR), 79 mc_make_sid_security_cfg(AONW), 80 mc_make_sid_security_cfg(AONDMAR), 81 mc_make_sid_security_cfg(AONDMAW), 82 mc_make_sid_security_cfg(SCER), 83 mc_make_sid_security_cfg(SCEW), 84 mc_make_sid_security_cfg(SCEDMAR), 85 mc_make_sid_security_cfg(SCEDMAW), 86 mc_make_sid_security_cfg(APEDMAR), 87 mc_make_sid_security_cfg(APEDMAW), 88 mc_make_sid_security_cfg(NVDISPLAYR1), 89 mc_make_sid_security_cfg(VICSRD1), 90 mc_make_sid_security_cfg(NVDECSRD1), 91 mc_make_sid_security_cfg(VIFALR), 92 mc_make_sid_security_cfg(VIFALW), 93 mc_make_sid_security_cfg(DLA0RDA), 94 mc_make_sid_security_cfg(DLA0FALRDB), 95 mc_make_sid_security_cfg(DLA0WRA), 96 mc_make_sid_security_cfg(DLA0FALWRB), 97 mc_make_sid_security_cfg(DLA1RDA), 98 mc_make_sid_security_cfg(DLA1FALRDB), 99 mc_make_sid_security_cfg(DLA1WRA), 100 mc_make_sid_security_cfg(DLA1FALWRB), 101 mc_make_sid_security_cfg(PVA0RDA), 102 mc_make_sid_security_cfg(PVA0RDB), 103 mc_make_sid_security_cfg(PVA0RDC), 104 mc_make_sid_security_cfg(PVA0WRA), 105 mc_make_sid_security_cfg(PVA0WRB), 106 mc_make_sid_security_cfg(PVA0WRC), 107 mc_make_sid_security_cfg(PVA1RDA), 108 mc_make_sid_security_cfg(PVA1RDB), 109 mc_make_sid_security_cfg(PVA1RDC), 110 mc_make_sid_security_cfg(PVA1WRA), 111 mc_make_sid_security_cfg(PVA1WRB), 112 mc_make_sid_security_cfg(PVA1WRC), 113 mc_make_sid_security_cfg(RCER), 114 mc_make_sid_security_cfg(RCEW), 115 mc_make_sid_security_cfg(RCEDMAR), 116 mc_make_sid_security_cfg(RCEDMAW), 117 mc_make_sid_security_cfg(NVENC1SRD), 118 mc_make_sid_security_cfg(NVENC1SWR), 119 mc_make_sid_security_cfg(PCIE0R), 120 mc_make_sid_security_cfg(PCIE0W), 121 mc_make_sid_security_cfg(PCIE1R), 122 mc_make_sid_security_cfg(PCIE1W), 123 mc_make_sid_security_cfg(PCIE2AR), 124 mc_make_sid_security_cfg(PCIE2AW), 125 mc_make_sid_security_cfg(PCIE3R), 126 mc_make_sid_security_cfg(PCIE3W), 127 mc_make_sid_security_cfg(PCIE4R), 128 mc_make_sid_security_cfg(PCIE4W), 129 mc_make_sid_security_cfg(PCIE5R), 130 mc_make_sid_security_cfg(PCIE5W), 131 mc_make_sid_security_cfg(ISPFALW), 132 mc_make_sid_security_cfg(DLA0RDA1), 133 mc_make_sid_security_cfg(DLA1RDA1), 134 mc_make_sid_security_cfg(PVA0RDA1), 135 mc_make_sid_security_cfg(PVA0RDB1), 136 mc_make_sid_security_cfg(PVA1RDA1), 137 mc_make_sid_security_cfg(PVA1RDB1), 138 mc_make_sid_security_cfg(PCIE5R1), 139 mc_make_sid_security_cfg(NVENCSRD1), 140 mc_make_sid_security_cfg(NVENC1SRD1), 141 mc_make_sid_security_cfg(ISPRA1), 142 mc_make_sid_security_cfg(PCIE0R1), 143 mc_make_sid_security_cfg(MIU0R), 144 mc_make_sid_security_cfg(MIU0W), 145 mc_make_sid_security_cfg(MIU1R), 146 mc_make_sid_security_cfg(MIU1W), 147 mc_make_sid_security_cfg(MIU2R), 148 mc_make_sid_security_cfg(MIU2W), 149 mc_make_sid_security_cfg(MIU3R), 150 mc_make_sid_security_cfg(MIU3W), 151 mc_make_sid_override_cfg(HDAR), 152 mc_make_sid_override_cfg(HOST1XDMAR), 153 mc_make_sid_override_cfg(NVENCSRD), 154 mc_make_sid_override_cfg(SATAR), 155 mc_make_sid_override_cfg(NVENCSWR), 156 mc_make_sid_override_cfg(HDAW), 157 mc_make_sid_override_cfg(SATAW), 158 mc_make_sid_override_cfg(ISPRA), 159 mc_make_sid_override_cfg(ISPFALR), 160 mc_make_sid_override_cfg(ISPWA), 161 mc_make_sid_override_cfg(ISPWB), 162 mc_make_sid_override_cfg(XUSB_HOSTR), 163 mc_make_sid_override_cfg(XUSB_HOSTW), 164 mc_make_sid_override_cfg(XUSB_DEVR), 165 mc_make_sid_override_cfg(XUSB_DEVW), 166 mc_make_sid_override_cfg(TSECSRD), 167 mc_make_sid_override_cfg(TSECSWR), 168 mc_make_sid_override_cfg(SDMMCRA), 169 mc_make_sid_override_cfg(SDMMCR), 170 mc_make_sid_override_cfg(SDMMCRAB), 171 mc_make_sid_override_cfg(SDMMCWA), 172 mc_make_sid_override_cfg(SDMMCW), 173 mc_make_sid_override_cfg(SDMMCWAB), 174 mc_make_sid_override_cfg(VICSRD), 175 mc_make_sid_override_cfg(VICSWR), 176 mc_make_sid_override_cfg(VIW), 177 mc_make_sid_override_cfg(NVDECSRD), 178 mc_make_sid_override_cfg(NVDECSWR), 179 mc_make_sid_override_cfg(APER), 180 mc_make_sid_override_cfg(APEW), 181 mc_make_sid_override_cfg(NVJPGSRD), 182 mc_make_sid_override_cfg(NVJPGSWR), 183 mc_make_sid_override_cfg(SESRD), 184 mc_make_sid_override_cfg(SESWR), 185 mc_make_sid_override_cfg(AXIAPR), 186 mc_make_sid_override_cfg(AXIAPW), 187 mc_make_sid_override_cfg(ETRR), 188 mc_make_sid_override_cfg(ETRW), 189 mc_make_sid_override_cfg(TSECSRDB), 190 mc_make_sid_override_cfg(TSECSWRB), 191 mc_make_sid_override_cfg(AXISR), 192 mc_make_sid_override_cfg(AXISW), 193 mc_make_sid_override_cfg(EQOSR), 194 mc_make_sid_override_cfg(EQOSW), 195 mc_make_sid_override_cfg(UFSHCR), 196 mc_make_sid_override_cfg(UFSHCW), 197 mc_make_sid_override_cfg(NVDISPLAYR), 198 mc_make_sid_override_cfg(BPMPR), 199 mc_make_sid_override_cfg(BPMPW), 200 mc_make_sid_override_cfg(BPMPDMAR), 201 mc_make_sid_override_cfg(BPMPDMAW), 202 mc_make_sid_override_cfg(AONR), 203 mc_make_sid_override_cfg(AONW), 204 mc_make_sid_override_cfg(AONDMAR), 205 mc_make_sid_override_cfg(AONDMAW), 206 mc_make_sid_override_cfg(SCER), 207 mc_make_sid_override_cfg(SCEW), 208 mc_make_sid_override_cfg(SCEDMAR), 209 mc_make_sid_override_cfg(SCEDMAW), 210 mc_make_sid_override_cfg(APEDMAR), 211 mc_make_sid_override_cfg(APEDMAW), 212 mc_make_sid_override_cfg(NVDISPLAYR1), 213 mc_make_sid_override_cfg(VICSRD1), 214 mc_make_sid_override_cfg(NVDECSRD1), 215 mc_make_sid_override_cfg(VIFALR), 216 mc_make_sid_override_cfg(VIFALW), 217 mc_make_sid_override_cfg(DLA0RDA), 218 mc_make_sid_override_cfg(DLA0FALRDB), 219 mc_make_sid_override_cfg(DLA0WRA), 220 mc_make_sid_override_cfg(DLA0FALWRB), 221 mc_make_sid_override_cfg(DLA1RDA), 222 mc_make_sid_override_cfg(DLA1FALRDB), 223 mc_make_sid_override_cfg(DLA1WRA), 224 mc_make_sid_override_cfg(DLA1FALWRB), 225 mc_make_sid_override_cfg(PVA0RDA), 226 mc_make_sid_override_cfg(PVA0RDB), 227 mc_make_sid_override_cfg(PVA0RDC), 228 mc_make_sid_override_cfg(PVA0WRA), 229 mc_make_sid_override_cfg(PVA0WRB), 230 mc_make_sid_override_cfg(PVA0WRC), 231 mc_make_sid_override_cfg(PVA1RDA), 232 mc_make_sid_override_cfg(PVA1RDB), 233 mc_make_sid_override_cfg(PVA1RDC), 234 mc_make_sid_override_cfg(PVA1WRA), 235 mc_make_sid_override_cfg(PVA1WRB), 236 mc_make_sid_override_cfg(PVA1WRC), 237 mc_make_sid_override_cfg(RCER), 238 mc_make_sid_override_cfg(RCEW), 239 mc_make_sid_override_cfg(RCEDMAR), 240 mc_make_sid_override_cfg(RCEDMAW), 241 mc_make_sid_override_cfg(NVENC1SRD), 242 mc_make_sid_override_cfg(NVENC1SWR), 243 mc_make_sid_override_cfg(PCIE0R), 244 mc_make_sid_override_cfg(PCIE0W), 245 mc_make_sid_override_cfg(PCIE1R), 246 mc_make_sid_override_cfg(PCIE1W), 247 mc_make_sid_override_cfg(PCIE2AR), 248 mc_make_sid_override_cfg(PCIE2AW), 249 mc_make_sid_override_cfg(PCIE3R), 250 mc_make_sid_override_cfg(PCIE3W), 251 mc_make_sid_override_cfg(PCIE4R), 252 mc_make_sid_override_cfg(PCIE4W), 253 mc_make_sid_override_cfg(PCIE5R), 254 mc_make_sid_override_cfg(PCIE5W), 255 mc_make_sid_override_cfg(ISPFALW), 256 mc_make_sid_override_cfg(DLA0RDA1), 257 mc_make_sid_override_cfg(DLA1RDA1), 258 mc_make_sid_override_cfg(PVA0RDA1), 259 mc_make_sid_override_cfg(PVA0RDB1), 260 mc_make_sid_override_cfg(PVA1RDA1), 261 mc_make_sid_override_cfg(PVA1RDB1), 262 mc_make_sid_override_cfg(PCIE5R1), 263 mc_make_sid_override_cfg(NVENCSRD1), 264 mc_make_sid_override_cfg(NVENC1SRD1), 265 mc_make_sid_override_cfg(ISPRA1), 266 mc_make_sid_override_cfg(PCIE0R1), 267 mc_make_sid_override_cfg(MIU0R), 268 mc_make_sid_override_cfg(MIU0W), 269 mc_make_sid_override_cfg(MIU1R), 270 mc_make_sid_override_cfg(MIU1W), 271 mc_make_sid_override_cfg(MIU2R), 272 mc_make_sid_override_cfg(MIU2W), 273 mc_make_sid_override_cfg(MIU3R), 274 mc_make_sid_override_cfg(MIU3W), 275 smmu_make_cfg(TEGRA_SMMU0_BASE), 276 smmu_make_cfg(TEGRA_SMMU2_BASE), 277 smmu_bypass_cfg, /* TBU settings */ 278 _END_OF_TABLE_, 279 }; 280 281 /******************************************************************************* 282 * Handler to return the pointer to the SMMU's context struct 283 ******************************************************************************/ 284 smmu_regs_t *plat_get_smmu_ctx(void) 285 { 286 /* index of _END_OF_TABLE_ */ 287 tegra194_smmu_context[0].val = (uint32_t)ARRAY_SIZE(tegra194_smmu_context) - 1U; 288 289 return tegra194_smmu_context; 290 } 291 292 /******************************************************************************* 293 * Handler to return the support SMMU devices number 294 ******************************************************************************/ 295 uint32_t plat_get_num_smmu_devices(void) 296 { 297 uint32_t ret_num = MAX_NUM_SMMU_DEVICES; 298 uint32_t board_revid = ((tegra_misc_read_32(MISCREG_EMU_REVID) >> \ 299 BOARD_SHIFT_BITS) & BOARD_MASK_BITS); 300 301 if (board_revid == BOARD_SYSTEM_FPGA_BASE) { 302 ret_num = BASE_CONFIG_SMMU_DEVICES; 303 } 304 305 return ret_num; 306 } 307