1719fdb6eSVarun Wadekar /* 2844e6cc5SPritesh Raithatha * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. 3719fdb6eSVarun Wadekar * 4719fdb6eSVarun Wadekar * SPDX-License-Identifier: BSD-3-Clause 5719fdb6eSVarun Wadekar */ 6719fdb6eSVarun Wadekar 7719fdb6eSVarun Wadekar #include <common/bl_common.h> 8719fdb6eSVarun Wadekar #include <common/debug.h> 9719fdb6eSVarun Wadekar #include <smmu.h> 10719fdb6eSVarun Wadekar #include <tegra_def.h> 11719fdb6eSVarun Wadekar 1213dcbc6fSSteven Kao #define BOARD_SYSTEM_FPGA_BASE U(1) 1313dcbc6fSSteven Kao #define BASE_CONFIG_SMMU_DEVICES U(2) 1413dcbc6fSSteven Kao #define MAX_NUM_SMMU_DEVICES U(3) 1513dcbc6fSSteven Kao 1613dcbc6fSSteven Kao static uint32_t tegra_misc_read_32(uint32_t off) 1713dcbc6fSSteven Kao { 18b6533b56SAnthony Zhou return mmio_read_32((uintptr_t)TEGRA_MISC_BASE + off); 1913dcbc6fSSteven Kao } 2013dcbc6fSSteven Kao 21719fdb6eSVarun Wadekar /******************************************************************************* 2213dcbc6fSSteven Kao * Handler to return the support SMMU devices number 2313dcbc6fSSteven Kao ******************************************************************************/ 2413dcbc6fSSteven Kao uint32_t plat_get_num_smmu_devices(void) 2513dcbc6fSSteven Kao { 2613dcbc6fSSteven Kao uint32_t ret_num = MAX_NUM_SMMU_DEVICES; 27*9a90d720SElyes Haouas uint32_t board_revid = ((tegra_misc_read_32(MISCREG_EMU_REVID) >> 286907891dSPritesh Raithatha BOARD_SHIFT_BITS) & BOARD_MASK_BITS); 2913dcbc6fSSteven Kao 3013dcbc6fSSteven Kao if (board_revid == BOARD_SYSTEM_FPGA_BASE) { 3113dcbc6fSSteven Kao ret_num = BASE_CONFIG_SMMU_DEVICES; 3213dcbc6fSSteven Kao } 3313dcbc6fSSteven Kao 3413dcbc6fSSteven Kao return ret_num; 3513dcbc6fSSteven Kao } 36