1 /* 2 * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <bl31/bl31.h> 10 #include <common/bl_common.h> 11 #include <common/interrupt_props.h> 12 #include <drivers/console.h> 13 #include <context.h> 14 #include <lib/el3_runtime/context_mgmt.h> 15 #include <cortex_a57.h> 16 #include <common/debug.h> 17 #include <denver.h> 18 #include <drivers/arm/gic_common.h> 19 #include <drivers/arm/gicv2.h> 20 #include <bl31/interrupt_mgmt.h> 21 #include <mce.h> 22 #include <mce_private.h> 23 #include <plat/common/platform.h> 24 #include <spe.h> 25 #include <tegra_def.h> 26 #include <tegra_mc_def.h> 27 #include <tegra_platform.h> 28 #include <tegra_private.h> 29 #include <lib/xlat_tables/xlat_tables_v2.h> 30 31 /* ID for spe-console */ 32 #define TEGRA_CONSOLE_SPE_ID 0xFE 33 34 /******************************************************************************* 35 * The Tegra power domain tree has a single system level power domain i.e. a 36 * single root node. The first entry in the power domain descriptor specifies 37 * the number of power domains at the highest power level. 38 ******************************************************************************* 39 */ 40 static const uint8_t tegra_power_domain_tree_desc[] = { 41 /* No of root nodes */ 42 1, 43 /* No of clusters */ 44 PLATFORM_CLUSTER_COUNT, 45 /* No of CPU cores - cluster0 */ 46 PLATFORM_MAX_CPUS_PER_CLUSTER, 47 /* No of CPU cores - cluster1 */ 48 PLATFORM_MAX_CPUS_PER_CLUSTER, 49 /* No of CPU cores - cluster2 */ 50 PLATFORM_MAX_CPUS_PER_CLUSTER, 51 /* No of CPU cores - cluster3 */ 52 PLATFORM_MAX_CPUS_PER_CLUSTER 53 }; 54 55 /******************************************************************************* 56 * This function returns the Tegra default topology tree information. 57 ******************************************************************************/ 58 const uint8_t *plat_get_power_domain_tree_desc(void) 59 { 60 return tegra_power_domain_tree_desc; 61 } 62 63 /* 64 * Table of regions to map using the MMU. 65 */ 66 static const mmap_region_t tegra_mmap[] = { 67 MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000U, /* 64KB */ 68 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 69 MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000U, /* 128KB */ 70 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 71 MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000U, /* 64KB */ 72 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 73 MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000U, /* 64KB */ 74 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 75 #if !ENABLE_CONSOLE_SPE 76 MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000U, /* 128KB - UART A, B*/ 77 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 78 MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000U, /* 128KB - UART C, G */ 79 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 80 MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000U, /* 192KB - UART D, E, F */ 81 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 82 #endif 83 MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000U, /* 64KB */ 84 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 85 MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000U, /* 128KB */ 86 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 87 MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000U, /* 64KB */ 88 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 89 MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000U, /* 64KB */ 90 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 91 MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000U, /* 64KB */ 92 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 93 #if ENABLE_CONSOLE_SPE 94 MAP_REGION_FLAT(TEGRA_AON_HSP_SM_6_7_BASE, 0x10000U, /* 64KB */ 95 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 96 #endif 97 MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000U, /* 64KB */ 98 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 99 MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000U, /* 256KB */ 100 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 101 MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000U, /* 64KB */ 102 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 103 MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000U, /* 384KB */ 104 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 105 MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x1000000U, /* 64KB */ 106 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 107 MAP_REGION_FLAT(TEGRA_SMMU1_BASE, 0x1000000U, /* 64KB */ 108 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 109 MAP_REGION_FLAT(TEGRA_SMMU2_BASE, 0x1000000U, /* 64KB */ 110 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 111 MAP_REGION_FLAT(TEGRA_XUSB_PADCTL_BASE, 0x10000U, /* 64KB */ 112 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 113 {0} 114 }; 115 116 /******************************************************************************* 117 * Set up the pagetables as per the platform memory map & initialize the MMU 118 ******************************************************************************/ 119 const mmap_region_t *plat_get_mmio_map(void) 120 { 121 /* MMIO space */ 122 return tegra_mmap; 123 } 124 125 /******************************************************************************* 126 * Handler to get the System Counter Frequency 127 ******************************************************************************/ 128 uint32_t plat_get_syscnt_freq2(void) 129 { 130 return 31250000; 131 } 132 133 #if !ENABLE_CONSOLE_SPE 134 /******************************************************************************* 135 * Maximum supported UART controllers 136 ******************************************************************************/ 137 #define TEGRA194_MAX_UART_PORTS 7 138 139 /******************************************************************************* 140 * This variable holds the UART port base addresses 141 ******************************************************************************/ 142 static uint32_t tegra194_uart_addresses[TEGRA194_MAX_UART_PORTS + 1] = { 143 0, /* undefined - treated as an error case */ 144 TEGRA_UARTA_BASE, 145 TEGRA_UARTB_BASE, 146 TEGRA_UARTC_BASE, 147 TEGRA_UARTD_BASE, 148 TEGRA_UARTE_BASE, 149 TEGRA_UARTF_BASE, 150 TEGRA_UARTG_BASE 151 }; 152 #endif 153 154 /******************************************************************************* 155 * Enable console corresponding to the console ID 156 ******************************************************************************/ 157 void plat_enable_console(int32_t id) 158 { 159 uint32_t console_clock = 0U; 160 161 #if ENABLE_CONSOLE_SPE 162 static console_spe_t spe_console; 163 164 if (id == TEGRA_CONSOLE_SPE_ID) { 165 (void)console_spe_register(TEGRA_CONSOLE_SPE_BASE, 166 console_clock, 167 TEGRA_CONSOLE_BAUDRATE, 168 &spe_console); 169 console_set_scope(&spe_console.console, CONSOLE_FLAG_BOOT | 170 CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH); 171 } 172 #else 173 static console_16550_t uart_console; 174 175 if ((id > 0) && (id < TEGRA194_MAX_UART_PORTS)) { 176 /* 177 * Reference clock used by the FPGAs is a lot slower. 178 */ 179 if (tegra_platform_is_fpga()) { 180 console_clock = TEGRA_BOOT_UART_CLK_13_MHZ; 181 } else { 182 console_clock = TEGRA_BOOT_UART_CLK_408_MHZ; 183 } 184 185 (void)console_16550_register(tegra194_uart_addresses[id], 186 console_clock, 187 TEGRA_CONSOLE_BAUDRATE, 188 &uart_console); 189 console_set_scope(&uart_console.console, CONSOLE_FLAG_BOOT | 190 CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH); 191 } 192 #endif 193 } 194 195 /******************************************************************************* 196 * Handler for early platform setup 197 ******************************************************************************/ 198 void plat_early_platform_setup(void) 199 { 200 201 /* sanity check MCE firmware compatibility */ 202 mce_verify_firmware_version(); 203 204 /* Program XUSB STREAMIDs 205 * Xavier XUSB has support for XUSB virtualization. It will have one 206 * physical function (PF) and four Virtual function (VF) 207 * 208 * There were below two SIDs for XUSB until T186. 209 * 1) #define TEGRA_SID_XUSB_HOST 0x1bU 210 * 2) #define TEGRA_SID_XUSB_DEV 0x1cU 211 * 212 * We have below four new SIDs added for VF(s) 213 * 3) #define TEGRA_SID_XUSB_VF0 0x5dU 214 * 4) #define TEGRA_SID_XUSB_VF1 0x5eU 215 * 5) #define TEGRA_SID_XUSB_VF2 0x5fU 216 * 6) #define TEGRA_SID_XUSB_VF3 0x60U 217 * 218 * When virtualization is enabled then we have to disable SID override 219 * and program above SIDs in below newly added SID registers in XUSB 220 * PADCTL MMIO space. These registers are TZ protected and so need to 221 * be done in ATF. 222 * a) #define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 (0x136cU) 223 * b) #define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0 (0x139cU) 224 * c) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 (0x1370U) 225 * d) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 (0x1374U) 226 * e) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 (0x1378U) 227 * f) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 (0x137cU) 228 * 229 * This change disables SID override and programs XUSB SIDs in 230 * above registers to support both virtualization and non-virtualization 231 * 232 * Known Limitations: 233 * If xusb interface disables SMMU in XUSB DT in non-virtualization 234 * setup then there will be SMMU fault. We need to use WAR at 235 * https:\\git-master.nvidia.com/r/1529227/ to the issue. 236 * 237 * More details can be found in the bug 1971161 238 */ 239 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 240 XUSB_PADCTL_HOST_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_HOST); 241 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 242 XUSB_PADCTL_HOST_AXI_STREAMID_VF_0, TEGRA_SID_XUSB_VF0); 243 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 244 XUSB_PADCTL_HOST_AXI_STREAMID_VF_1, TEGRA_SID_XUSB_VF1); 245 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 246 XUSB_PADCTL_HOST_AXI_STREAMID_VF_2, TEGRA_SID_XUSB_VF2); 247 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 248 XUSB_PADCTL_HOST_AXI_STREAMID_VF_3, TEGRA_SID_XUSB_VF3); 249 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 250 XUSB_PADCTL_DEV_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_DEV); 251 } 252 253 /* Secure IRQs for Tegra194 */ 254 static const interrupt_prop_t tegra194_interrupt_props[] = { 255 INTR_PROP_DESC(TEGRA194_TOP_WDT_IRQ, GIC_HIGHEST_SEC_PRIORITY, 256 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE), 257 INTR_PROP_DESC(TEGRA194_AON_WDT_IRQ, GIC_HIGHEST_SEC_PRIORITY, 258 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE) 259 }; 260 261 /******************************************************************************* 262 * Initialize the GIC and SGIs 263 ******************************************************************************/ 264 void plat_gic_setup(void) 265 { 266 tegra_gic_setup(tegra194_interrupt_props, ARRAY_SIZE(tegra194_interrupt_props)); 267 tegra_gic_init(); 268 269 /* 270 * Initialize the FIQ handler 271 */ 272 tegra_fiq_handler_setup(); 273 } 274 275 /******************************************************************************* 276 * Return pointer to the BL31 params from previous bootloader 277 ******************************************************************************/ 278 struct tegra_bl31_params *plat_get_bl31_params(void) 279 { 280 uint32_t val; 281 282 val = mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PARAMS_ADDR); 283 284 return (struct tegra_bl31_params *)(uintptr_t)val; 285 } 286 287 /******************************************************************************* 288 * Return pointer to the BL31 platform params from previous bootloader 289 ******************************************************************************/ 290 plat_params_from_bl2_t *plat_get_bl31_plat_params(void) 291 { 292 uint32_t val; 293 294 val = mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PLAT_PARAMS_ADDR); 295 296 return (plat_params_from_bl2_t *)(uintptr_t)val; 297 } 298 299 void plat_late_platform_setup(void) 300 { 301 /* 302 * Enable strict checking after programming the GSC for 303 * enabling TZSRAM and TZDRAM 304 */ 305 mce_enable_strict_checking(); 306 } 307