1 /* 2 * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <bl31/bl31.h> 10 #include <common/bl_common.h> 11 #include <common/interrupt_props.h> 12 #include <drivers/console.h> 13 #include <context.h> 14 #include <lib/el3_runtime/context_mgmt.h> 15 #include <cortex_a57.h> 16 #include <common/debug.h> 17 #include <denver.h> 18 #include <drivers/arm/gic_common.h> 19 #include <drivers/arm/gicv2.h> 20 #include <bl31/interrupt_mgmt.h> 21 #include <mce.h> 22 #include <mce_private.h> 23 #include <plat/common/platform.h> 24 #include <spe.h> 25 #include <tegra_def.h> 26 #include <tegra_mc_def.h> 27 #include <tegra_platform.h> 28 #include <tegra_private.h> 29 #include <lib/xlat_tables/xlat_tables_v2.h> 30 31 /* ID for spe-console */ 32 #define TEGRA_CONSOLE_SPE_ID 0xFE 33 34 /******************************************************************************* 35 * The Tegra power domain tree has a single system level power domain i.e. a 36 * single root node. The first entry in the power domain descriptor specifies 37 * the number of power domains at the highest power level. 38 ******************************************************************************* 39 */ 40 static const uint8_t tegra_power_domain_tree_desc[] = { 41 /* No of root nodes */ 42 1, 43 /* No of clusters */ 44 PLATFORM_CLUSTER_COUNT, 45 /* No of CPU cores - cluster0 */ 46 PLATFORM_MAX_CPUS_PER_CLUSTER, 47 /* No of CPU cores - cluster1 */ 48 PLATFORM_MAX_CPUS_PER_CLUSTER, 49 /* No of CPU cores - cluster2 */ 50 PLATFORM_MAX_CPUS_PER_CLUSTER, 51 /* No of CPU cores - cluster3 */ 52 PLATFORM_MAX_CPUS_PER_CLUSTER 53 }; 54 55 /******************************************************************************* 56 * This function returns the Tegra default topology tree information. 57 ******************************************************************************/ 58 const uint8_t *plat_get_power_domain_tree_desc(void) 59 { 60 return tegra_power_domain_tree_desc; 61 } 62 63 /* 64 * Table of regions to map using the MMU. 65 */ 66 static const mmap_region_t tegra_mmap[] = { 67 MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x4000U, /* 16KB */ 68 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 69 MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000U, /* 128KB */ 70 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 71 MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x8000U, /* 32KB */ 72 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 73 MAP_REGION_FLAT(TEGRA_MC_BASE, 0x8000U, /* 32KB */ 74 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 75 #if !ENABLE_CONSOLE_SPE 76 MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000U, /* 128KB - UART A, B*/ 77 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 78 MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000U, /* 128KB - UART C, G */ 79 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 80 MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000U, /* 192KB - UART D, E, F */ 81 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 82 #endif 83 MAP_REGION_FLAT(TEGRA_XUSB_PADCTL_BASE, 0x2000U, /* 8KB */ 84 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 85 MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x1000, /* 4KB */ 86 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 87 MAP_REGION_FLAT(TEGRA_GICC_BASE, 0x1000, /* 4KB */ 88 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 89 MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x1000U, /* 4KB */ 90 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 91 MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x1000U, /* 4KB */ 92 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 93 MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x1000U, /* 4KB */ 94 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 95 MAP_REGION_FLAT(TEGRA_HSP_DBELL_BASE, 0x1000U, /* 4KB */ 96 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 97 #if ENABLE_CONSOLE_SPE 98 MAP_REGION_FLAT(TEGRA_CONSOLE_SPE_BASE, 0x1000U, /* 4KB */ 99 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 100 #endif 101 MAP_REGION_FLAT(TEGRA_TMRUS_BASE, TEGRA_TMRUS_SIZE, /* 4KB */ 102 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 103 MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x1000U, /* 4KB */ 104 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 105 MAP_REGION_FLAT(TEGRA_SMMU2_BASE, 0x800000U, /* 8MB */ 106 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 107 MAP_REGION_FLAT(TEGRA_SMMU1_BASE, 0x800000U, /* 8MB */ 108 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 109 MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x800000U, /* 8MB */ 110 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 111 MAP_REGION_FLAT(TEGRA_BPMP_IPC_TX_PHYS_BASE, 0x10000U, /* 64KB */ 112 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 113 MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000U, /* 64KB */ 114 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 115 {0} 116 }; 117 118 /******************************************************************************* 119 * Set up the pagetables as per the platform memory map & initialize the MMU 120 ******************************************************************************/ 121 const mmap_region_t *plat_get_mmio_map(void) 122 { 123 /* MMIO space */ 124 return tegra_mmap; 125 } 126 127 /******************************************************************************* 128 * Handler to get the System Counter Frequency 129 ******************************************************************************/ 130 uint32_t plat_get_syscnt_freq2(void) 131 { 132 return 31250000; 133 } 134 135 #if !ENABLE_CONSOLE_SPE 136 /******************************************************************************* 137 * Maximum supported UART controllers 138 ******************************************************************************/ 139 #define TEGRA194_MAX_UART_PORTS 7 140 141 /******************************************************************************* 142 * This variable holds the UART port base addresses 143 ******************************************************************************/ 144 static uint32_t tegra194_uart_addresses[TEGRA194_MAX_UART_PORTS + 1] = { 145 0, /* undefined - treated as an error case */ 146 TEGRA_UARTA_BASE, 147 TEGRA_UARTB_BASE, 148 TEGRA_UARTC_BASE, 149 TEGRA_UARTD_BASE, 150 TEGRA_UARTE_BASE, 151 TEGRA_UARTF_BASE, 152 TEGRA_UARTG_BASE 153 }; 154 #endif 155 156 /******************************************************************************* 157 * Enable console corresponding to the console ID 158 ******************************************************************************/ 159 void plat_enable_console(int32_t id) 160 { 161 uint32_t console_clock = 0U; 162 163 #if ENABLE_CONSOLE_SPE 164 static console_spe_t spe_console; 165 166 if (id == TEGRA_CONSOLE_SPE_ID) { 167 (void)console_spe_register(TEGRA_CONSOLE_SPE_BASE, 168 console_clock, 169 TEGRA_CONSOLE_BAUDRATE, 170 &spe_console); 171 console_set_scope(&spe_console.console, CONSOLE_FLAG_BOOT | 172 CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH); 173 } 174 #else 175 static console_16550_t uart_console; 176 177 if ((id > 0) && (id < TEGRA194_MAX_UART_PORTS)) { 178 /* 179 * Reference clock used by the FPGAs is a lot slower. 180 */ 181 if (tegra_platform_is_fpga()) { 182 console_clock = TEGRA_BOOT_UART_CLK_13_MHZ; 183 } else { 184 console_clock = TEGRA_BOOT_UART_CLK_408_MHZ; 185 } 186 187 (void)console_16550_register(tegra194_uart_addresses[id], 188 console_clock, 189 TEGRA_CONSOLE_BAUDRATE, 190 &uart_console); 191 console_set_scope(&uart_console.console, CONSOLE_FLAG_BOOT | 192 CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH); 193 } 194 #endif 195 } 196 197 /******************************************************************************* 198 * Handler for early platform setup 199 ******************************************************************************/ 200 void plat_early_platform_setup(void) 201 { 202 /* sanity check MCE firmware compatibility */ 203 mce_verify_firmware_version(); 204 205 /* 206 * Program XUSB STREAMIDs 207 * ====================== 208 * T19x XUSB has support for XUSB virtualization. It will have one 209 * physical function (PF) and four Virtual function (VF) 210 * 211 * There were below two SIDs for XUSB until T186. 212 * 1) #define TEGRA_SID_XUSB_HOST 0x1bU 213 * 2) #define TEGRA_SID_XUSB_DEV 0x1cU 214 * 215 * We have below four new SIDs added for VF(s) 216 * 3) #define TEGRA_SID_XUSB_VF0 0x5dU 217 * 4) #define TEGRA_SID_XUSB_VF1 0x5eU 218 * 5) #define TEGRA_SID_XUSB_VF2 0x5fU 219 * 6) #define TEGRA_SID_XUSB_VF3 0x60U 220 * 221 * When virtualization is enabled then we have to disable SID override 222 * and program above SIDs in below newly added SID registers in XUSB 223 * PADCTL MMIO space. These registers are TZ protected and so need to 224 * be done in ATF. 225 * a) #define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 (0x136cU) 226 * b) #define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0 (0x139cU) 227 * c) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 (0x1370U) 228 * d) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 (0x1374U) 229 * e) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 (0x1378U) 230 * f) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 (0x137cU) 231 * 232 * This change disables SID override and programs XUSB SIDs in 233 * above registers to support both virtualization and 234 * non-virtualization platforms 235 */ 236 if (tegra_platform_is_silicon() || tegra_platform_is_fpga()) { 237 238 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 239 XUSB_PADCTL_HOST_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_HOST); 240 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 241 XUSB_PADCTL_HOST_AXI_STREAMID_VF_0, TEGRA_SID_XUSB_VF0); 242 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 243 XUSB_PADCTL_HOST_AXI_STREAMID_VF_1, TEGRA_SID_XUSB_VF1); 244 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 245 XUSB_PADCTL_HOST_AXI_STREAMID_VF_2, TEGRA_SID_XUSB_VF2); 246 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 247 XUSB_PADCTL_HOST_AXI_STREAMID_VF_3, TEGRA_SID_XUSB_VF3); 248 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 249 XUSB_PADCTL_DEV_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_DEV); 250 } 251 } 252 253 /* Secure IRQs for Tegra194 */ 254 static const interrupt_prop_t tegra194_interrupt_props[] = { 255 INTR_PROP_DESC(TEGRA194_TOP_WDT_IRQ, GIC_HIGHEST_SEC_PRIORITY, 256 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE), 257 INTR_PROP_DESC(TEGRA194_AON_WDT_IRQ, GIC_HIGHEST_SEC_PRIORITY, 258 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE) 259 }; 260 261 /******************************************************************************* 262 * Initialize the GIC and SGIs 263 ******************************************************************************/ 264 void plat_gic_setup(void) 265 { 266 tegra_gic_setup(tegra194_interrupt_props, ARRAY_SIZE(tegra194_interrupt_props)); 267 tegra_gic_init(); 268 269 /* 270 * Initialize the FIQ handler 271 */ 272 tegra_fiq_handler_setup(); 273 } 274 275 /******************************************************************************* 276 * Return pointer to the BL31 params from previous bootloader 277 ******************************************************************************/ 278 struct tegra_bl31_params *plat_get_bl31_params(void) 279 { 280 uint64_t val; 281 282 val = (mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PARAMS_HI_ADDR) & 283 SCRATCH_BL31_PARAMS_HI_ADDR_MASK) >> SCRATCH_BL31_PARAMS_HI_ADDR_SHIFT; 284 val <<= 32; 285 val |= mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PARAMS_LO_ADDR); 286 287 return (struct tegra_bl31_params *)(uintptr_t)val; 288 } 289 290 /******************************************************************************* 291 * Return pointer to the BL31 platform params from previous bootloader 292 ******************************************************************************/ 293 plat_params_from_bl2_t *plat_get_bl31_plat_params(void) 294 { 295 uint64_t val; 296 297 val = (mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PLAT_PARAMS_HI_ADDR) & 298 SCRATCH_BL31_PLAT_PARAMS_HI_ADDR_MASK) >> SCRATCH_BL31_PLAT_PARAMS_HI_ADDR_SHIFT; 299 val <<= 32; 300 val |= mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PLAT_PARAMS_LO_ADDR); 301 302 return (plat_params_from_bl2_t *)(uintptr_t)val; 303 } 304 305 void plat_late_platform_setup(void) 306 { 307 #if ENABLE_STRICT_CHECKING_MODE 308 /* 309 * Enable strict checking after programming the GSC for 310 * enabling TZSRAM and TZDRAM 311 */ 312 mce_enable_strict_checking(); 313 #endif 314 } 315