1 /* 2 * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <bl31/bl31.h> 10 #include <common/bl_common.h> 11 #include <common/interrupt_props.h> 12 #include <drivers/console.h> 13 #include <context.h> 14 #include <lib/el3_runtime/context_mgmt.h> 15 #include <cortex_a57.h> 16 #include <common/debug.h> 17 #include <denver.h> 18 #include <drivers/arm/gic_common.h> 19 #include <drivers/arm/gicv2.h> 20 #include <bl31/interrupt_mgmt.h> 21 #include <mce.h> 22 #include <plat/common/platform.h> 23 #include <tegra_def.h> 24 #include <tegra_mc_def.h> 25 #include <tegra_platform.h> 26 #include <tegra_private.h> 27 #include <lib/xlat_tables/xlat_tables_v2.h> 28 29 /******************************************************************************* 30 * The Tegra power domain tree has a single system level power domain i.e. a 31 * single root node. The first entry in the power domain descriptor specifies 32 * the number of power domains at the highest power level. 33 ******************************************************************************* 34 */ 35 const unsigned char tegra_power_domain_tree_desc[] = { 36 /* No of root nodes */ 37 1, 38 /* No of clusters */ 39 PLATFORM_CLUSTER_COUNT, 40 /* No of CPU cores - cluster0 */ 41 PLATFORM_MAX_CPUS_PER_CLUSTER, 42 /* No of CPU cores - cluster1 */ 43 PLATFORM_MAX_CPUS_PER_CLUSTER, 44 /* No of CPU cores - cluster2 */ 45 PLATFORM_MAX_CPUS_PER_CLUSTER, 46 /* No of CPU cores - cluster3 */ 47 PLATFORM_MAX_CPUS_PER_CLUSTER 48 }; 49 50 /******************************************************************************* 51 * This function returns the Tegra default topology tree information. 52 ******************************************************************************/ 53 const unsigned char *plat_get_power_domain_tree_desc(void) 54 { 55 return tegra_power_domain_tree_desc; 56 } 57 58 /* 59 * Table of regions to map using the MMU. 60 */ 61 static const mmap_region_t tegra_mmap[] = { 62 MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000, /* 64KB */ 63 MT_DEVICE | MT_RW | MT_SECURE), 64 MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000, /* 128KB */ 65 MT_DEVICE | MT_RW | MT_SECURE), 66 MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000, /* 64KB */ 67 MT_DEVICE | MT_RW | MT_SECURE), 68 MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000, /* 64KB */ 69 MT_DEVICE | MT_RW | MT_SECURE), 70 MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000, /* 128KB - UART A, B*/ 71 MT_DEVICE | MT_RW | MT_SECURE), 72 MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000, /* 128KB - UART C, G */ 73 MT_DEVICE | MT_RW | MT_SECURE), 74 MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000, /* 192KB - UART D, E, F */ 75 MT_DEVICE | MT_RW | MT_SECURE), 76 MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000, /* 64KB */ 77 MT_DEVICE | MT_RW | MT_SECURE), 78 MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000, /* 128KB */ 79 MT_DEVICE | MT_RW | MT_SECURE), 80 MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000, /* 64KB */ 81 MT_DEVICE | MT_RW | MT_SECURE), 82 MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000, /* 64KB */ 83 MT_DEVICE | MT_RW | MT_SECURE), 84 MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000, /* 64KB */ 85 MT_DEVICE | MT_RW | MT_SECURE), 86 MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000, /* 64KB */ 87 MT_DEVICE | MT_RW | MT_SECURE), 88 MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000, /* 256KB */ 89 MT_DEVICE | MT_RW | MT_SECURE), 90 MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000, /* 64KB */ 91 MT_DEVICE | MT_RW | MT_SECURE), 92 MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000, /* 384KB */ 93 MT_DEVICE | MT_RW | MT_SECURE), 94 MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x1000000, /* 64KB */ 95 MT_DEVICE | MT_RW | MT_SECURE), 96 MAP_REGION_FLAT(TEGRA_SMMU1_BASE, 0x1000000, /* 64KB */ 97 MT_DEVICE | MT_RW | MT_SECURE), 98 MAP_REGION_FLAT(TEGRA_SMMU2_BASE, 0x1000000, /* 64KB */ 99 MT_DEVICE | MT_RW | MT_SECURE), 100 MAP_REGION_FLAT(TEGRA_XUSB_PADCTL_BASE, 0x10000, /* 64KB */ 101 MT_DEVICE | MT_RW | MT_SECURE), 102 {0} 103 }; 104 105 /******************************************************************************* 106 * Set up the pagetables as per the platform memory map & initialize the MMU 107 ******************************************************************************/ 108 const mmap_region_t *plat_get_mmio_map(void) 109 { 110 /* MMIO space */ 111 return tegra_mmap; 112 } 113 114 /******************************************************************************* 115 * Handler to get the System Counter Frequency 116 ******************************************************************************/ 117 unsigned int plat_get_syscnt_freq2(void) 118 { 119 return 31250000; 120 } 121 122 /******************************************************************************* 123 * Maximum supported UART controllers 124 ******************************************************************************/ 125 #define TEGRA186_MAX_UART_PORTS 7 126 127 /******************************************************************************* 128 * This variable holds the UART port base addresses 129 ******************************************************************************/ 130 static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = { 131 0, /* undefined - treated as an error case */ 132 TEGRA_UARTA_BASE, 133 TEGRA_UARTB_BASE, 134 TEGRA_UARTC_BASE, 135 TEGRA_UARTD_BASE, 136 TEGRA_UARTE_BASE, 137 TEGRA_UARTF_BASE, 138 TEGRA_UARTG_BASE, 139 }; 140 141 /******************************************************************************* 142 * Retrieve the UART controller base to be used as the console 143 ******************************************************************************/ 144 uint32_t plat_get_console_from_id(int id) 145 { 146 if (id > TEGRA186_MAX_UART_PORTS) 147 return 0; 148 149 return tegra186_uart_addresses[id]; 150 } 151 152 /******************************************************************************* 153 * Handler for early platform setup 154 ******************************************************************************/ 155 void plat_early_platform_setup(void) 156 { 157 158 /* sanity check MCE firmware compatibility */ 159 mce_verify_firmware_version(); 160 161 /* Program XUSB STREAMIDs 162 * Xavier XUSB has support for XUSB virtualization. It will have one 163 * physical function (PF) and four Virtual function (VF) 164 * 165 * There were below two SIDs for XUSB until T186. 166 * 1) #define TEGRA_SID_XUSB_HOST 0x1bU 167 * 2) #define TEGRA_SID_XUSB_DEV 0x1cU 168 * 169 * We have below four new SIDs added for VF(s) 170 * 3) #define TEGRA_SID_XUSB_VF0 0x5dU 171 * 4) #define TEGRA_SID_XUSB_VF1 0x5eU 172 * 5) #define TEGRA_SID_XUSB_VF2 0x5fU 173 * 6) #define TEGRA_SID_XUSB_VF3 0x60U 174 * 175 * When virtualization is enabled then we have to disable SID override 176 * and program above SIDs in below newly added SID registers in XUSB 177 * PADCTL MMIO space. These registers are TZ protected and so need to 178 * be done in ATF. 179 * a) #define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 (0x136cU) 180 * b) #define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0 (0x139cU) 181 * c) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 (0x1370U) 182 * d) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 (0x1374U) 183 * e) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 (0x1378U) 184 * f) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 (0x137cU) 185 * 186 * This change disables SID override and programs XUSB SIDs in 187 * above registers to support both virtualization and non-virtualization 188 * 189 * Known Limitations: 190 * If xusb interface disables SMMU in XUSB DT in non-virtualization 191 * setup then there will be SMMU fault. We need to use WAR at 192 * https://git-master.nvidia.com/r/1529227/ to the issue. 193 * 194 * More details can be found in the bug 1971161 195 */ 196 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 197 XUSB_PADCTL_HOST_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_HOST); 198 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 199 XUSB_PADCTL_HOST_AXI_STREAMID_VF_0, TEGRA_SID_XUSB_VF0); 200 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 201 XUSB_PADCTL_HOST_AXI_STREAMID_VF_1, TEGRA_SID_XUSB_VF1); 202 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 203 XUSB_PADCTL_HOST_AXI_STREAMID_VF_2, TEGRA_SID_XUSB_VF2); 204 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 205 XUSB_PADCTL_HOST_AXI_STREAMID_VF_3, TEGRA_SID_XUSB_VF3); 206 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 207 XUSB_PADCTL_DEV_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_DEV); 208 } 209 210 /* Secure IRQs for Tegra186 */ 211 static const irq_sec_cfg_t tegra186_sec_irqs[] = { 212 [0] = { 213 TEGRA186_BPMP_WDT_IRQ, 214 TEGRA186_SEC_IRQ_TARGET_MASK, 215 INTR_TYPE_EL3, 216 }, 217 [1] = { 218 TEGRA186_BPMP_WDT_IRQ, 219 TEGRA186_SEC_IRQ_TARGET_MASK, 220 INTR_TYPE_EL3, 221 }, 222 [2] = { 223 TEGRA186_SPE_WDT_IRQ, 224 TEGRA186_SEC_IRQ_TARGET_MASK, 225 INTR_TYPE_EL3, 226 }, 227 [3] = { 228 TEGRA186_SCE_WDT_IRQ, 229 TEGRA186_SEC_IRQ_TARGET_MASK, 230 INTR_TYPE_EL3, 231 }, 232 [4] = { 233 TEGRA186_TOP_WDT_IRQ, 234 TEGRA186_SEC_IRQ_TARGET_MASK, 235 INTR_TYPE_EL3, 236 }, 237 [5] = { 238 TEGRA186_AON_WDT_IRQ, 239 TEGRA186_SEC_IRQ_TARGET_MASK, 240 INTR_TYPE_EL3, 241 }, 242 }; 243 244 /******************************************************************************* 245 * Initialize the GIC and SGIs 246 ******************************************************************************/ 247 void plat_gic_setup(void) 248 { 249 tegra_gic_setup(tegra186_sec_irqs, 250 sizeof(tegra186_sec_irqs) / sizeof(tegra186_sec_irqs[0])); 251 252 /* 253 * Initialize the FIQ handler only if the platform supports any 254 * FIQ interrupt sources. 255 */ 256 if (sizeof(tegra186_sec_irqs) > 0) 257 tegra_fiq_handler_setup(); 258 } 259 260 /******************************************************************************* 261 * Return pointer to the BL31 params from previous bootloader 262 ******************************************************************************/ 263 struct tegra_bl31_params *plat_get_bl31_params(void) 264 { 265 uint32_t val; 266 267 val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_LO); 268 269 return (struct tegra_bl31_params *)(uintptr_t)val; 270 } 271 272 /******************************************************************************* 273 * Return pointer to the BL31 platform params from previous bootloader 274 ******************************************************************************/ 275 plat_params_from_bl2_t *plat_get_bl31_plat_params(void) 276 { 277 uint32_t val; 278 279 val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_HI); 280 281 return (plat_params_from_bl2_t *)(uintptr_t)val; 282 } 283