1 /* 2 * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <bl31/bl31.h> 10 #include <common/bl_common.h> 11 #include <common/interrupt_props.h> 12 #include <drivers/console.h> 13 #include <context.h> 14 #include <lib/el3_runtime/context_mgmt.h> 15 #include <cortex_a57.h> 16 #include <common/debug.h> 17 #include <denver.h> 18 #include <drivers/arm/gic_common.h> 19 #include <drivers/arm/gicv2.h> 20 #include <bl31/interrupt_mgmt.h> 21 #include <mce.h> 22 #include <mce_private.h> 23 #include <plat/common/platform.h> 24 #include <spe.h> 25 #include <tegra_def.h> 26 #include <tegra_mc_def.h> 27 #include <tegra_platform.h> 28 #include <tegra_private.h> 29 #include <lib/xlat_tables/xlat_tables_v2.h> 30 31 /* ID for spe-console */ 32 #define TEGRA_CONSOLE_SPE_ID 0xFE 33 34 /******************************************************************************* 35 * The Tegra power domain tree has a single system level power domain i.e. a 36 * single root node. The first entry in the power domain descriptor specifies 37 * the number of power domains at the highest power level. 38 ******************************************************************************* 39 */ 40 static const uint8_t tegra_power_domain_tree_desc[] = { 41 /* No of root nodes */ 42 1, 43 /* No of clusters */ 44 PLATFORM_CLUSTER_COUNT, 45 /* No of CPU cores - cluster0 */ 46 PLATFORM_MAX_CPUS_PER_CLUSTER, 47 /* No of CPU cores - cluster1 */ 48 PLATFORM_MAX_CPUS_PER_CLUSTER, 49 /* No of CPU cores - cluster2 */ 50 PLATFORM_MAX_CPUS_PER_CLUSTER, 51 /* No of CPU cores - cluster3 */ 52 PLATFORM_MAX_CPUS_PER_CLUSTER 53 }; 54 55 /******************************************************************************* 56 * This function returns the Tegra default topology tree information. 57 ******************************************************************************/ 58 const uint8_t *plat_get_power_domain_tree_desc(void) 59 { 60 return tegra_power_domain_tree_desc; 61 } 62 63 /* 64 * Table of regions to map using the MMU. 65 */ 66 static const mmap_region_t tegra_mmap[] = { 67 MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x4000U, /* 16KB */ 68 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 69 MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000U, /* 128KB */ 70 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 71 MAP_REGION_FLAT(TEGRA_GPCDMA_BASE, 0x10000U, /* 64KB */ 72 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 73 MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x8000U, /* 32KB */ 74 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 75 MAP_REGION_FLAT(TEGRA_MC_BASE, 0x8000U, /* 32KB */ 76 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 77 #if !ENABLE_CONSOLE_SPE 78 MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000U, /* 128KB - UART A, B*/ 79 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 80 MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000U, /* 128KB - UART C, G */ 81 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 82 MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000U, /* 192KB - UART D, E, F */ 83 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 84 #endif 85 MAP_REGION_FLAT(TEGRA_XUSB_PADCTL_BASE, 0x2000U, /* 8KB */ 86 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 87 MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x1000, /* 4KB */ 88 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 89 MAP_REGION_FLAT(TEGRA_GICC_BASE, 0x1000, /* 4KB */ 90 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 91 MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x1000U, /* 4KB */ 92 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 93 MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x1000U, /* 4KB */ 94 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 95 MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x1000U, /* 4KB */ 96 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 97 MAP_REGION_FLAT(TEGRA_HSP_DBELL_BASE, 0x1000U, /* 4KB */ 98 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 99 #if ENABLE_CONSOLE_SPE 100 MAP_REGION_FLAT(TEGRA_CONSOLE_SPE_BASE, 0x1000U, /* 4KB */ 101 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 102 #endif 103 MAP_REGION_FLAT(TEGRA_TMRUS_BASE, TEGRA_TMRUS_SIZE, /* 4KB */ 104 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 105 MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x1000U, /* 4KB */ 106 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 107 MAP_REGION_FLAT(TEGRA_SMMU2_BASE, 0x800000U, /* 8MB */ 108 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 109 MAP_REGION_FLAT(TEGRA_SMMU1_BASE, 0x800000U, /* 8MB */ 110 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 111 MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x800000U, /* 8MB */ 112 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 113 MAP_REGION_FLAT(TEGRA_BPMP_IPC_TX_PHYS_BASE, 0x10000U, /* 64KB */ 114 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 115 MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000U, /* 64KB */ 116 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 117 {0} 118 }; 119 120 /******************************************************************************* 121 * Set up the pagetables as per the platform memory map & initialize the MMU 122 ******************************************************************************/ 123 const mmap_region_t *plat_get_mmio_map(void) 124 { 125 /* MMIO space */ 126 return tegra_mmap; 127 } 128 129 /******************************************************************************* 130 * Handler to get the System Counter Frequency 131 ******************************************************************************/ 132 uint32_t plat_get_syscnt_freq2(void) 133 { 134 return 31250000; 135 } 136 137 #if !ENABLE_CONSOLE_SPE 138 /******************************************************************************* 139 * Maximum supported UART controllers 140 ******************************************************************************/ 141 #define TEGRA194_MAX_UART_PORTS 7 142 143 /******************************************************************************* 144 * This variable holds the UART port base addresses 145 ******************************************************************************/ 146 static uint32_t tegra194_uart_addresses[TEGRA194_MAX_UART_PORTS + 1] = { 147 0, /* undefined - treated as an error case */ 148 TEGRA_UARTA_BASE, 149 TEGRA_UARTB_BASE, 150 TEGRA_UARTC_BASE, 151 TEGRA_UARTD_BASE, 152 TEGRA_UARTE_BASE, 153 TEGRA_UARTF_BASE, 154 TEGRA_UARTG_BASE 155 }; 156 #endif 157 158 /******************************************************************************* 159 * Enable console corresponding to the console ID 160 ******************************************************************************/ 161 void plat_enable_console(int32_t id) 162 { 163 uint32_t console_clock = 0U; 164 165 #if ENABLE_CONSOLE_SPE 166 static console_spe_t spe_console; 167 168 if (id == TEGRA_CONSOLE_SPE_ID) { 169 (void)console_spe_register(TEGRA_CONSOLE_SPE_BASE, 170 console_clock, 171 TEGRA_CONSOLE_BAUDRATE, 172 &spe_console); 173 console_set_scope(&spe_console.console, CONSOLE_FLAG_BOOT | 174 CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH); 175 } 176 #else 177 static console_16550_t uart_console; 178 179 if ((id > 0) && (id < TEGRA194_MAX_UART_PORTS)) { 180 /* 181 * Reference clock used by the FPGAs is a lot slower. 182 */ 183 if (tegra_platform_is_fpga()) { 184 console_clock = TEGRA_BOOT_UART_CLK_13_MHZ; 185 } else { 186 console_clock = TEGRA_BOOT_UART_CLK_408_MHZ; 187 } 188 189 (void)console_16550_register(tegra194_uart_addresses[id], 190 console_clock, 191 TEGRA_CONSOLE_BAUDRATE, 192 &uart_console); 193 console_set_scope(&uart_console.console, CONSOLE_FLAG_BOOT | 194 CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH); 195 } 196 #endif 197 } 198 199 /******************************************************************************* 200 * Handler for early platform setup 201 ******************************************************************************/ 202 void plat_early_platform_setup(void) 203 { 204 /* sanity check MCE firmware compatibility */ 205 mce_verify_firmware_version(); 206 207 /* 208 * Program XUSB STREAMIDs 209 * ====================== 210 * T19x XUSB has support for XUSB virtualization. It will have one 211 * physical function (PF) and four Virtual function (VF) 212 * 213 * There were below two SIDs for XUSB until T186. 214 * 1) #define TEGRA_SID_XUSB_HOST 0x1bU 215 * 2) #define TEGRA_SID_XUSB_DEV 0x1cU 216 * 217 * We have below four new SIDs added for VF(s) 218 * 3) #define TEGRA_SID_XUSB_VF0 0x5dU 219 * 4) #define TEGRA_SID_XUSB_VF1 0x5eU 220 * 5) #define TEGRA_SID_XUSB_VF2 0x5fU 221 * 6) #define TEGRA_SID_XUSB_VF3 0x60U 222 * 223 * When virtualization is enabled then we have to disable SID override 224 * and program above SIDs in below newly added SID registers in XUSB 225 * PADCTL MMIO space. These registers are TZ protected and so need to 226 * be done in ATF. 227 * a) #define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 (0x136cU) 228 * b) #define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0 (0x139cU) 229 * c) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 (0x1370U) 230 * d) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 (0x1374U) 231 * e) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 (0x1378U) 232 * f) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 (0x137cU) 233 * 234 * This change disables SID override and programs XUSB SIDs in 235 * above registers to support both virtualization and 236 * non-virtualization platforms 237 */ 238 if (tegra_platform_is_silicon() || tegra_platform_is_fpga()) { 239 240 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 241 XUSB_PADCTL_HOST_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_HOST); 242 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 243 XUSB_PADCTL_HOST_AXI_STREAMID_VF_0, TEGRA_SID_XUSB_VF0); 244 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 245 XUSB_PADCTL_HOST_AXI_STREAMID_VF_1, TEGRA_SID_XUSB_VF1); 246 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 247 XUSB_PADCTL_HOST_AXI_STREAMID_VF_2, TEGRA_SID_XUSB_VF2); 248 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 249 XUSB_PADCTL_HOST_AXI_STREAMID_VF_3, TEGRA_SID_XUSB_VF3); 250 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 251 XUSB_PADCTL_DEV_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_DEV); 252 } 253 } 254 255 /* Secure IRQs for Tegra194 */ 256 static const interrupt_prop_t tegra194_interrupt_props[] = { 257 INTR_PROP_DESC(TEGRA194_TOP_WDT_IRQ, GIC_HIGHEST_SEC_PRIORITY, 258 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE), 259 INTR_PROP_DESC(TEGRA194_AON_WDT_IRQ, GIC_HIGHEST_SEC_PRIORITY, 260 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE) 261 }; 262 263 /******************************************************************************* 264 * Initialize the GIC and SGIs 265 ******************************************************************************/ 266 void plat_gic_setup(void) 267 { 268 tegra_gic_setup(tegra194_interrupt_props, ARRAY_SIZE(tegra194_interrupt_props)); 269 tegra_gic_init(); 270 271 /* 272 * Initialize the FIQ handler 273 */ 274 tegra_fiq_handler_setup(); 275 } 276 277 /******************************************************************************* 278 * Return pointer to the BL31 params from previous bootloader 279 ******************************************************************************/ 280 struct tegra_bl31_params *plat_get_bl31_params(void) 281 { 282 uint64_t val; 283 284 val = (mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PARAMS_HI_ADDR) & 285 SCRATCH_BL31_PARAMS_HI_ADDR_MASK) >> SCRATCH_BL31_PARAMS_HI_ADDR_SHIFT; 286 val <<= 32; 287 val |= mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PARAMS_LO_ADDR); 288 289 return (struct tegra_bl31_params *)(uintptr_t)val; 290 } 291 292 /******************************************************************************* 293 * Return pointer to the BL31 platform params from previous bootloader 294 ******************************************************************************/ 295 plat_params_from_bl2_t *plat_get_bl31_plat_params(void) 296 { 297 uint64_t val; 298 299 val = (mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PLAT_PARAMS_HI_ADDR) & 300 SCRATCH_BL31_PLAT_PARAMS_HI_ADDR_MASK) >> SCRATCH_BL31_PLAT_PARAMS_HI_ADDR_SHIFT; 301 val <<= 32; 302 val |= mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PLAT_PARAMS_LO_ADDR); 303 304 return (plat_params_from_bl2_t *)(uintptr_t)val; 305 } 306 307 void plat_late_platform_setup(void) 308 { 309 #if ENABLE_STRICT_CHECKING_MODE 310 /* 311 * Enable strict checking after programming the GSC for 312 * enabling TZSRAM and TZDRAM 313 */ 314 mce_enable_strict_checking(); 315 #endif 316 } 317