1 /* 2 * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <bl31/bl31.h> 10 #include <common/bl_common.h> 11 #include <common/interrupt_props.h> 12 #include <drivers/console.h> 13 #include <context.h> 14 #include <lib/el3_runtime/context_mgmt.h> 15 #include <cortex_a57.h> 16 #include <common/debug.h> 17 #include <denver.h> 18 #include <drivers/arm/gic_common.h> 19 #include <drivers/arm/gicv2.h> 20 #include <bl31/interrupt_mgmt.h> 21 #include <mce.h> 22 #include <plat/common/platform.h> 23 #include <tegra_def.h> 24 #include <tegra_platform.h> 25 #include <tegra_private.h> 26 #include <lib/xlat_tables/xlat_tables_v2.h> 27 28 /******************************************************************************* 29 * The Tegra power domain tree has a single system level power domain i.e. a 30 * single root node. The first entry in the power domain descriptor specifies 31 * the number of power domains at the highest power level. 32 ******************************************************************************* 33 */ 34 const unsigned char tegra_power_domain_tree_desc[] = { 35 /* No of root nodes */ 36 1, 37 /* No of clusters */ 38 PLATFORM_CLUSTER_COUNT, 39 /* No of CPU cores - cluster0 */ 40 PLATFORM_MAX_CPUS_PER_CLUSTER, 41 /* No of CPU cores - cluster1 */ 42 PLATFORM_MAX_CPUS_PER_CLUSTER 43 }; 44 45 /******************************************************************************* 46 * This function returns the Tegra default topology tree information. 47 ******************************************************************************/ 48 const unsigned char *plat_get_power_domain_tree_desc(void) 49 { 50 return tegra_power_domain_tree_desc; 51 } 52 53 /* 54 * Table of regions to map using the MMU. 55 */ 56 static const mmap_region_t tegra_mmap[] = { 57 MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000, /* 64KB */ 58 MT_DEVICE | MT_RW | MT_SECURE), 59 MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000, /* 128KB */ 60 MT_DEVICE | MT_RW | MT_SECURE), 61 MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000, /* 64KB */ 62 MT_DEVICE | MT_RW | MT_SECURE), 63 MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000, /* 64KB */ 64 MT_DEVICE | MT_RW | MT_SECURE), 65 MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000, /* 128KB - UART A, B*/ 66 MT_DEVICE | MT_RW | MT_SECURE), 67 MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000, /* 128KB - UART C, G */ 68 MT_DEVICE | MT_RW | MT_SECURE), 69 MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000, /* 192KB - UART D, E, F */ 70 MT_DEVICE | MT_RW | MT_SECURE), 71 MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000, /* 64KB */ 72 MT_DEVICE | MT_RW | MT_SECURE), 73 MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000, /* 128KB */ 74 MT_DEVICE | MT_RW | MT_SECURE), 75 MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000, /* 64KB */ 76 MT_DEVICE | MT_RW | MT_SECURE), 77 MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000, /* 64KB */ 78 MT_DEVICE | MT_RW | MT_SECURE), 79 MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000, /* 64KB */ 80 MT_DEVICE | MT_RW | MT_SECURE), 81 MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000, /* 64KB */ 82 MT_DEVICE | MT_RW | MT_SECURE), 83 MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000, /* 256KB */ 84 MT_DEVICE | MT_RW | MT_SECURE), 85 MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000, /* 64KB */ 86 MT_DEVICE | MT_RW | MT_SECURE), 87 MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000, /* 384KB */ 88 MT_DEVICE | MT_RW | MT_SECURE), 89 MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x1000000, /* 64KB */ 90 MT_DEVICE | MT_RW | MT_SECURE), 91 MAP_REGION_FLAT(TEGRA_SMMU1_BASE, 0x1000000, /* 64KB */ 92 MT_DEVICE | MT_RW | MT_SECURE), 93 MAP_REGION_FLAT(TEGRA_SMMU2_BASE, 0x1000000, /* 64KB */ 94 MT_DEVICE | MT_RW | MT_SECURE), 95 {0} 96 }; 97 98 /******************************************************************************* 99 * Set up the pagetables as per the platform memory map & initialize the MMU 100 ******************************************************************************/ 101 const mmap_region_t *plat_get_mmio_map(void) 102 { 103 /* MMIO space */ 104 return tegra_mmap; 105 } 106 107 /******************************************************************************* 108 * Handler to get the System Counter Frequency 109 ******************************************************************************/ 110 unsigned int plat_get_syscnt_freq2(void) 111 { 112 return 31250000; 113 } 114 115 /******************************************************************************* 116 * Maximum supported UART controllers 117 ******************************************************************************/ 118 #define TEGRA186_MAX_UART_PORTS 7 119 120 /******************************************************************************* 121 * This variable holds the UART port base addresses 122 ******************************************************************************/ 123 static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = { 124 0, /* undefined - treated as an error case */ 125 TEGRA_UARTA_BASE, 126 TEGRA_UARTB_BASE, 127 TEGRA_UARTC_BASE, 128 TEGRA_UARTD_BASE, 129 TEGRA_UARTE_BASE, 130 TEGRA_UARTF_BASE, 131 TEGRA_UARTG_BASE, 132 }; 133 134 /******************************************************************************* 135 * Retrieve the UART controller base to be used as the console 136 ******************************************************************************/ 137 uint32_t plat_get_console_from_id(int id) 138 { 139 if (id > TEGRA186_MAX_UART_PORTS) 140 return 0; 141 142 return tegra186_uart_addresses[id]; 143 } 144 145 /******************************************************************************* 146 * Handler for early platform setup 147 ******************************************************************************/ 148 void plat_early_platform_setup(void) 149 { 150 151 /* sanity check MCE firmware compatibility */ 152 mce_verify_firmware_version(); 153 154 } 155 156 /* Secure IRQs for Tegra186 */ 157 static const irq_sec_cfg_t tegra186_sec_irqs[] = { 158 [0] = { 159 TEGRA186_BPMP_WDT_IRQ, 160 TEGRA186_SEC_IRQ_TARGET_MASK, 161 INTR_TYPE_EL3, 162 }, 163 [1] = { 164 TEGRA186_BPMP_WDT_IRQ, 165 TEGRA186_SEC_IRQ_TARGET_MASK, 166 INTR_TYPE_EL3, 167 }, 168 [2] = { 169 TEGRA186_SPE_WDT_IRQ, 170 TEGRA186_SEC_IRQ_TARGET_MASK, 171 INTR_TYPE_EL3, 172 }, 173 [3] = { 174 TEGRA186_SCE_WDT_IRQ, 175 TEGRA186_SEC_IRQ_TARGET_MASK, 176 INTR_TYPE_EL3, 177 }, 178 [4] = { 179 TEGRA186_TOP_WDT_IRQ, 180 TEGRA186_SEC_IRQ_TARGET_MASK, 181 INTR_TYPE_EL3, 182 }, 183 [5] = { 184 TEGRA186_AON_WDT_IRQ, 185 TEGRA186_SEC_IRQ_TARGET_MASK, 186 INTR_TYPE_EL3, 187 }, 188 }; 189 190 /******************************************************************************* 191 * Initialize the GIC and SGIs 192 ******************************************************************************/ 193 void plat_gic_setup(void) 194 { 195 tegra_gic_setup(tegra186_sec_irqs, 196 sizeof(tegra186_sec_irqs) / sizeof(tegra186_sec_irqs[0])); 197 198 /* 199 * Initialize the FIQ handler only if the platform supports any 200 * FIQ interrupt sources. 201 */ 202 if (sizeof(tegra186_sec_irqs) > 0) 203 tegra_fiq_handler_setup(); 204 } 205 206 /******************************************************************************* 207 * Return pointer to the BL31 params from previous bootloader 208 ******************************************************************************/ 209 struct tegra_bl31_params *plat_get_bl31_params(void) 210 { 211 uint32_t val; 212 213 val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_LO); 214 215 return (struct tegra_bl31_params *)(uintptr_t)val; 216 } 217 218 /******************************************************************************* 219 * Return pointer to the BL31 platform params from previous bootloader 220 ******************************************************************************/ 221 plat_params_from_bl2_t *plat_get_bl31_plat_params(void) 222 { 223 uint32_t val; 224 225 val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_HI); 226 227 return (plat_params_from_bl2_t *)(uintptr_t)val; 228 } 229