1*41612559SVarun Wadekar /* 2*41612559SVarun Wadekar * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. 3*41612559SVarun Wadekar * 4*41612559SVarun Wadekar * SPDX-License-Identifier: BSD-3-Clause 5*41612559SVarun Wadekar */ 6*41612559SVarun Wadekar 7*41612559SVarun Wadekar #include <arch_helpers.h> 8*41612559SVarun Wadekar #include <assert.h> 9*41612559SVarun Wadekar #include <bl31/bl31.h> 10*41612559SVarun Wadekar #include <common/bl_common.h> 11*41612559SVarun Wadekar #include <common/interrupt_props.h> 12*41612559SVarun Wadekar #include <drivers/console.h> 13*41612559SVarun Wadekar #include <context.h> 14*41612559SVarun Wadekar #include <lib/el3_runtime/context_mgmt.h> 15*41612559SVarun Wadekar #include <cortex_a57.h> 16*41612559SVarun Wadekar #include <common/debug.h> 17*41612559SVarun Wadekar #include <denver.h> 18*41612559SVarun Wadekar #include <drivers/arm/gic_common.h> 19*41612559SVarun Wadekar #include <drivers/arm/gicv2.h> 20*41612559SVarun Wadekar #include <bl31/interrupt_mgmt.h> 21*41612559SVarun Wadekar #include <mce.h> 22*41612559SVarun Wadekar #include <plat/common/platform.h> 23*41612559SVarun Wadekar #include <tegra_def.h> 24*41612559SVarun Wadekar #include <tegra_platform.h> 25*41612559SVarun Wadekar #include <tegra_private.h> 26*41612559SVarun Wadekar #include <lib/xlat_tables/xlat_tables_v2.h> 27*41612559SVarun Wadekar 28*41612559SVarun Wadekar DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, L2CTLR_EL1) 29*41612559SVarun Wadekar extern uint64_t tegra_enable_l2_ecc_parity_prot; 30*41612559SVarun Wadekar 31*41612559SVarun Wadekar /******************************************************************************* 32*41612559SVarun Wadekar * The Tegra power domain tree has a single system level power domain i.e. a 33*41612559SVarun Wadekar * single root node. The first entry in the power domain descriptor specifies 34*41612559SVarun Wadekar * the number of power domains at the highest power level. 35*41612559SVarun Wadekar ******************************************************************************* 36*41612559SVarun Wadekar */ 37*41612559SVarun Wadekar const unsigned char tegra_power_domain_tree_desc[] = { 38*41612559SVarun Wadekar /* No of root nodes */ 39*41612559SVarun Wadekar 1, 40*41612559SVarun Wadekar /* No of clusters */ 41*41612559SVarun Wadekar PLATFORM_CLUSTER_COUNT, 42*41612559SVarun Wadekar /* No of CPU cores - cluster0 */ 43*41612559SVarun Wadekar PLATFORM_MAX_CPUS_PER_CLUSTER, 44*41612559SVarun Wadekar /* No of CPU cores - cluster1 */ 45*41612559SVarun Wadekar PLATFORM_MAX_CPUS_PER_CLUSTER 46*41612559SVarun Wadekar }; 47*41612559SVarun Wadekar 48*41612559SVarun Wadekar /* 49*41612559SVarun Wadekar * Table of regions to map using the MMU. 50*41612559SVarun Wadekar */ 51*41612559SVarun Wadekar static const mmap_region_t tegra_mmap[] = { 52*41612559SVarun Wadekar MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000, /* 64KB */ 53*41612559SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 54*41612559SVarun Wadekar MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000, /* 128KB */ 55*41612559SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 56*41612559SVarun Wadekar MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000, /* 64KB */ 57*41612559SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 58*41612559SVarun Wadekar MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000, /* 64KB */ 59*41612559SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 60*41612559SVarun Wadekar MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000, /* 128KB - UART A, B*/ 61*41612559SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 62*41612559SVarun Wadekar MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000, /* 128KB - UART C, G */ 63*41612559SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 64*41612559SVarun Wadekar MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000, /* 192KB - UART D, E, F */ 65*41612559SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 66*41612559SVarun Wadekar MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000, /* 64KB */ 67*41612559SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 68*41612559SVarun Wadekar MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000, /* 128KB */ 69*41612559SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 70*41612559SVarun Wadekar MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000, /* 64KB */ 71*41612559SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 72*41612559SVarun Wadekar MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000, /* 64KB */ 73*41612559SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 74*41612559SVarun Wadekar MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000, /* 64KB */ 75*41612559SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 76*41612559SVarun Wadekar MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000, /* 64KB */ 77*41612559SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 78*41612559SVarun Wadekar MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000, /* 256KB */ 79*41612559SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 80*41612559SVarun Wadekar MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000, /* 64KB */ 81*41612559SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 82*41612559SVarun Wadekar MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000, /* 384KB */ 83*41612559SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 84*41612559SVarun Wadekar MAP_REGION_FLAT(TEGRA_SMMU_BASE, 0x1000000, /* 64KB */ 85*41612559SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 86*41612559SVarun Wadekar {0} 87*41612559SVarun Wadekar }; 88*41612559SVarun Wadekar 89*41612559SVarun Wadekar /******************************************************************************* 90*41612559SVarun Wadekar * Set up the pagetables as per the platform memory map & initialize the MMU 91*41612559SVarun Wadekar ******************************************************************************/ 92*41612559SVarun Wadekar const mmap_region_t *plat_get_mmio_map(void) 93*41612559SVarun Wadekar { 94*41612559SVarun Wadekar /* MMIO space */ 95*41612559SVarun Wadekar return tegra_mmap; 96*41612559SVarun Wadekar } 97*41612559SVarun Wadekar 98*41612559SVarun Wadekar /******************************************************************************* 99*41612559SVarun Wadekar * Handler to get the System Counter Frequency 100*41612559SVarun Wadekar ******************************************************************************/ 101*41612559SVarun Wadekar unsigned int plat_get_syscnt_freq2(void) 102*41612559SVarun Wadekar { 103*41612559SVarun Wadekar return 31250000; 104*41612559SVarun Wadekar } 105*41612559SVarun Wadekar 106*41612559SVarun Wadekar /******************************************************************************* 107*41612559SVarun Wadekar * Maximum supported UART controllers 108*41612559SVarun Wadekar ******************************************************************************/ 109*41612559SVarun Wadekar #define TEGRA186_MAX_UART_PORTS 7 110*41612559SVarun Wadekar 111*41612559SVarun Wadekar /******************************************************************************* 112*41612559SVarun Wadekar * This variable holds the UART port base addresses 113*41612559SVarun Wadekar ******************************************************************************/ 114*41612559SVarun Wadekar static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = { 115*41612559SVarun Wadekar 0, /* undefined - treated as an error case */ 116*41612559SVarun Wadekar TEGRA_UARTA_BASE, 117*41612559SVarun Wadekar TEGRA_UARTB_BASE, 118*41612559SVarun Wadekar TEGRA_UARTC_BASE, 119*41612559SVarun Wadekar TEGRA_UARTD_BASE, 120*41612559SVarun Wadekar TEGRA_UARTE_BASE, 121*41612559SVarun Wadekar TEGRA_UARTF_BASE, 122*41612559SVarun Wadekar TEGRA_UARTG_BASE, 123*41612559SVarun Wadekar }; 124*41612559SVarun Wadekar 125*41612559SVarun Wadekar /******************************************************************************* 126*41612559SVarun Wadekar * Retrieve the UART controller base to be used as the console 127*41612559SVarun Wadekar ******************************************************************************/ 128*41612559SVarun Wadekar uint32_t plat_get_console_from_id(int id) 129*41612559SVarun Wadekar { 130*41612559SVarun Wadekar if (id > TEGRA186_MAX_UART_PORTS) 131*41612559SVarun Wadekar return 0; 132*41612559SVarun Wadekar 133*41612559SVarun Wadekar return tegra186_uart_addresses[id]; 134*41612559SVarun Wadekar } 135*41612559SVarun Wadekar 136*41612559SVarun Wadekar /* represent chip-version as concatenation of major (15:12), minor (11:8) and subrev (7:0) */ 137*41612559SVarun Wadekar #define TEGRA186_VER_A02P 0x1201 138*41612559SVarun Wadekar 139*41612559SVarun Wadekar /******************************************************************************* 140*41612559SVarun Wadekar * Handler for early platform setup 141*41612559SVarun Wadekar ******************************************************************************/ 142*41612559SVarun Wadekar void plat_early_platform_setup(void) 143*41612559SVarun Wadekar { 144*41612559SVarun Wadekar int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; 145*41612559SVarun Wadekar uint32_t chip_subrev, val; 146*41612559SVarun Wadekar 147*41612559SVarun Wadekar /* sanity check MCE firmware compatibility */ 148*41612559SVarun Wadekar mce_verify_firmware_version(); 149*41612559SVarun Wadekar 150*41612559SVarun Wadekar /* 151*41612559SVarun Wadekar * Enable ECC and Parity Protection for Cortex-A57 CPUs 152*41612559SVarun Wadekar * for Tegra A02p SKUs 153*41612559SVarun Wadekar */ 154*41612559SVarun Wadekar if (impl != DENVER_IMPL) { 155*41612559SVarun Wadekar 156*41612559SVarun Wadekar /* get the major, minor and sub-version values */ 157*41612559SVarun Wadekar chip_subrev = mmio_read_32(TEGRA_FUSE_BASE + OPT_SUBREVISION) & 158*41612559SVarun Wadekar SUBREVISION_MASK; 159*41612559SVarun Wadekar 160*41612559SVarun Wadekar /* prepare chip version number */ 161*41612559SVarun Wadekar val = (tegra_get_chipid_major() << 12) | 162*41612559SVarun Wadekar (tegra_get_chipid_minor() << 8) | 163*41612559SVarun Wadekar chip_subrev; 164*41612559SVarun Wadekar 165*41612559SVarun Wadekar /* enable L2 ECC for Tegra186 A02P and beyond */ 166*41612559SVarun Wadekar if (val >= TEGRA186_VER_A02P) { 167*41612559SVarun Wadekar 168*41612559SVarun Wadekar val = read_l2ctlr_el1(); 169*41612559SVarun Wadekar val |= L2_ECC_PARITY_PROTECTION_BIT; 170*41612559SVarun Wadekar write_l2ctlr_el1(val); 171*41612559SVarun Wadekar 172*41612559SVarun Wadekar /* 173*41612559SVarun Wadekar * Set the flag to enable ECC/Parity Protection 174*41612559SVarun Wadekar * when we exit System Suspend or Cluster Powerdn 175*41612559SVarun Wadekar */ 176*41612559SVarun Wadekar tegra_enable_l2_ecc_parity_prot = 1; 177*41612559SVarun Wadekar } 178*41612559SVarun Wadekar } 179*41612559SVarun Wadekar } 180*41612559SVarun Wadekar 181*41612559SVarun Wadekar /* Secure IRQs for Tegra186 */ 182*41612559SVarun Wadekar static const irq_sec_cfg_t tegra186_sec_irqs[] = { 183*41612559SVarun Wadekar [0] = { 184*41612559SVarun Wadekar TEGRA186_BPMP_WDT_IRQ, 185*41612559SVarun Wadekar TEGRA186_SEC_IRQ_TARGET_MASK, 186*41612559SVarun Wadekar INTR_TYPE_EL3, 187*41612559SVarun Wadekar }, 188*41612559SVarun Wadekar [1] = { 189*41612559SVarun Wadekar TEGRA186_BPMP_WDT_IRQ, 190*41612559SVarun Wadekar TEGRA186_SEC_IRQ_TARGET_MASK, 191*41612559SVarun Wadekar INTR_TYPE_EL3, 192*41612559SVarun Wadekar }, 193*41612559SVarun Wadekar [2] = { 194*41612559SVarun Wadekar TEGRA186_SPE_WDT_IRQ, 195*41612559SVarun Wadekar TEGRA186_SEC_IRQ_TARGET_MASK, 196*41612559SVarun Wadekar INTR_TYPE_EL3, 197*41612559SVarun Wadekar }, 198*41612559SVarun Wadekar [3] = { 199*41612559SVarun Wadekar TEGRA186_SCE_WDT_IRQ, 200*41612559SVarun Wadekar TEGRA186_SEC_IRQ_TARGET_MASK, 201*41612559SVarun Wadekar INTR_TYPE_EL3, 202*41612559SVarun Wadekar }, 203*41612559SVarun Wadekar [4] = { 204*41612559SVarun Wadekar TEGRA186_TOP_WDT_IRQ, 205*41612559SVarun Wadekar TEGRA186_SEC_IRQ_TARGET_MASK, 206*41612559SVarun Wadekar INTR_TYPE_EL3, 207*41612559SVarun Wadekar }, 208*41612559SVarun Wadekar [5] = { 209*41612559SVarun Wadekar TEGRA186_AON_WDT_IRQ, 210*41612559SVarun Wadekar TEGRA186_SEC_IRQ_TARGET_MASK, 211*41612559SVarun Wadekar INTR_TYPE_EL3, 212*41612559SVarun Wadekar }, 213*41612559SVarun Wadekar }; 214*41612559SVarun Wadekar 215*41612559SVarun Wadekar /******************************************************************************* 216*41612559SVarun Wadekar * Initialize the GIC and SGIs 217*41612559SVarun Wadekar ******************************************************************************/ 218*41612559SVarun Wadekar void plat_gic_setup(void) 219*41612559SVarun Wadekar { 220*41612559SVarun Wadekar tegra_gic_setup(tegra186_sec_irqs, 221*41612559SVarun Wadekar sizeof(tegra186_sec_irqs) / sizeof(tegra186_sec_irqs[0])); 222*41612559SVarun Wadekar 223*41612559SVarun Wadekar /* 224*41612559SVarun Wadekar * Initialize the FIQ handler only if the platform supports any 225*41612559SVarun Wadekar * FIQ interrupt sources. 226*41612559SVarun Wadekar */ 227*41612559SVarun Wadekar if (sizeof(tegra186_sec_irqs) > 0) 228*41612559SVarun Wadekar tegra_fiq_handler_setup(); 229*41612559SVarun Wadekar } 230*41612559SVarun Wadekar 231*41612559SVarun Wadekar /******************************************************************************* 232*41612559SVarun Wadekar * Return pointer to the BL31 params from previous bootloader 233*41612559SVarun Wadekar ******************************************************************************/ 234*41612559SVarun Wadekar struct tegra_bl31_params *plat_get_bl31_params(void) 235*41612559SVarun Wadekar { 236*41612559SVarun Wadekar uint32_t val; 237*41612559SVarun Wadekar 238*41612559SVarun Wadekar val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_LO); 239*41612559SVarun Wadekar 240*41612559SVarun Wadekar return (struct tegra_bl31_params *)(uintptr_t)val; 241*41612559SVarun Wadekar } 242*41612559SVarun Wadekar 243*41612559SVarun Wadekar /******************************************************************************* 244*41612559SVarun Wadekar * Return pointer to the BL31 platform params from previous bootloader 245*41612559SVarun Wadekar ******************************************************************************/ 246*41612559SVarun Wadekar plat_params_from_bl2_t *plat_get_bl31_plat_params(void) 247*41612559SVarun Wadekar { 248*41612559SVarun Wadekar uint32_t val; 249*41612559SVarun Wadekar 250*41612559SVarun Wadekar val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_HI); 251*41612559SVarun Wadekar 252*41612559SVarun Wadekar return (plat_params_from_bl2_t *)(uintptr_t)val; 253*41612559SVarun Wadekar } 254