141612559SVarun Wadekar /* 241612559SVarun Wadekar * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. 341612559SVarun Wadekar * 441612559SVarun Wadekar * SPDX-License-Identifier: BSD-3-Clause 541612559SVarun Wadekar */ 641612559SVarun Wadekar 741612559SVarun Wadekar #include <arch_helpers.h> 841612559SVarun Wadekar #include <assert.h> 941612559SVarun Wadekar #include <bl31/bl31.h> 1041612559SVarun Wadekar #include <common/bl_common.h> 1141612559SVarun Wadekar #include <common/interrupt_props.h> 1241612559SVarun Wadekar #include <drivers/console.h> 1341612559SVarun Wadekar #include <context.h> 1441612559SVarun Wadekar #include <lib/el3_runtime/context_mgmt.h> 1541612559SVarun Wadekar #include <cortex_a57.h> 1641612559SVarun Wadekar #include <common/debug.h> 1741612559SVarun Wadekar #include <denver.h> 1841612559SVarun Wadekar #include <drivers/arm/gic_common.h> 1941612559SVarun Wadekar #include <drivers/arm/gicv2.h> 2041612559SVarun Wadekar #include <bl31/interrupt_mgmt.h> 2141612559SVarun Wadekar #include <mce.h> 2241612559SVarun Wadekar #include <plat/common/platform.h> 2341612559SVarun Wadekar #include <tegra_def.h> 2441612559SVarun Wadekar #include <tegra_platform.h> 2541612559SVarun Wadekar #include <tegra_private.h> 2641612559SVarun Wadekar #include <lib/xlat_tables/xlat_tables_v2.h> 2741612559SVarun Wadekar 2841612559SVarun Wadekar /******************************************************************************* 2941612559SVarun Wadekar * The Tegra power domain tree has a single system level power domain i.e. a 3041612559SVarun Wadekar * single root node. The first entry in the power domain descriptor specifies 3141612559SVarun Wadekar * the number of power domains at the highest power level. 3241612559SVarun Wadekar ******************************************************************************* 3341612559SVarun Wadekar */ 3441612559SVarun Wadekar const unsigned char tegra_power_domain_tree_desc[] = { 3541612559SVarun Wadekar /* No of root nodes */ 3641612559SVarun Wadekar 1, 3741612559SVarun Wadekar /* No of clusters */ 3841612559SVarun Wadekar PLATFORM_CLUSTER_COUNT, 3941612559SVarun Wadekar /* No of CPU cores - cluster0 */ 4041612559SVarun Wadekar PLATFORM_MAX_CPUS_PER_CLUSTER, 4141612559SVarun Wadekar /* No of CPU cores - cluster1 */ 42*1e6a7f91SVarun Wadekar PLATFORM_MAX_CPUS_PER_CLUSTER, 43*1e6a7f91SVarun Wadekar /* No of CPU cores - cluster2 */ 44*1e6a7f91SVarun Wadekar PLATFORM_MAX_CPUS_PER_CLUSTER, 45*1e6a7f91SVarun Wadekar /* No of CPU cores - cluster3 */ 4641612559SVarun Wadekar PLATFORM_MAX_CPUS_PER_CLUSTER 4741612559SVarun Wadekar }; 4841612559SVarun Wadekar 4942de0384SVarun Wadekar /******************************************************************************* 5042de0384SVarun Wadekar * This function returns the Tegra default topology tree information. 5142de0384SVarun Wadekar ******************************************************************************/ 5242de0384SVarun Wadekar const unsigned char *plat_get_power_domain_tree_desc(void) 5342de0384SVarun Wadekar { 5442de0384SVarun Wadekar return tegra_power_domain_tree_desc; 5542de0384SVarun Wadekar } 5642de0384SVarun Wadekar 5741612559SVarun Wadekar /* 5841612559SVarun Wadekar * Table of regions to map using the MMU. 5941612559SVarun Wadekar */ 6041612559SVarun Wadekar static const mmap_region_t tegra_mmap[] = { 6141612559SVarun Wadekar MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000, /* 64KB */ 6241612559SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 6341612559SVarun Wadekar MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000, /* 128KB */ 6441612559SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 6541612559SVarun Wadekar MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000, /* 64KB */ 6641612559SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 6741612559SVarun Wadekar MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000, /* 64KB */ 6841612559SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 6941612559SVarun Wadekar MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000, /* 128KB - UART A, B*/ 7041612559SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 7141612559SVarun Wadekar MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000, /* 128KB - UART C, G */ 7241612559SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 7341612559SVarun Wadekar MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000, /* 192KB - UART D, E, F */ 7441612559SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 7541612559SVarun Wadekar MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000, /* 64KB */ 7641612559SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 7741612559SVarun Wadekar MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000, /* 128KB */ 7841612559SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 7941612559SVarun Wadekar MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000, /* 64KB */ 8041612559SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 8141612559SVarun Wadekar MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000, /* 64KB */ 8241612559SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 8341612559SVarun Wadekar MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000, /* 64KB */ 8441612559SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 8541612559SVarun Wadekar MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000, /* 64KB */ 8641612559SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 8741612559SVarun Wadekar MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000, /* 256KB */ 8841612559SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 8941612559SVarun Wadekar MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000, /* 64KB */ 9041612559SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 9141612559SVarun Wadekar MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000, /* 384KB */ 9241612559SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 930ea8881eSPritesh Raithatha MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x1000000, /* 64KB */ 940ea8881eSPritesh Raithatha MT_DEVICE | MT_RW | MT_SECURE), 950ea8881eSPritesh Raithatha MAP_REGION_FLAT(TEGRA_SMMU1_BASE, 0x1000000, /* 64KB */ 960ea8881eSPritesh Raithatha MT_DEVICE | MT_RW | MT_SECURE), 970ea8881eSPritesh Raithatha MAP_REGION_FLAT(TEGRA_SMMU2_BASE, 0x1000000, /* 64KB */ 9841612559SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 99bc019041SAjay Gupta MAP_REGION_FLAT(TEGRA_XUSB_PADCTL_BASE, 0x10000, /* 64KB */ 100bc019041SAjay Gupta MT_DEVICE | MT_RW | MT_SECURE), 10141612559SVarun Wadekar {0} 10241612559SVarun Wadekar }; 10341612559SVarun Wadekar 10441612559SVarun Wadekar /******************************************************************************* 10541612559SVarun Wadekar * Set up the pagetables as per the platform memory map & initialize the MMU 10641612559SVarun Wadekar ******************************************************************************/ 10741612559SVarun Wadekar const mmap_region_t *plat_get_mmio_map(void) 10841612559SVarun Wadekar { 10941612559SVarun Wadekar /* MMIO space */ 11041612559SVarun Wadekar return tegra_mmap; 11141612559SVarun Wadekar } 11241612559SVarun Wadekar 11341612559SVarun Wadekar /******************************************************************************* 11441612559SVarun Wadekar * Handler to get the System Counter Frequency 11541612559SVarun Wadekar ******************************************************************************/ 11641612559SVarun Wadekar unsigned int plat_get_syscnt_freq2(void) 11741612559SVarun Wadekar { 11841612559SVarun Wadekar return 31250000; 11941612559SVarun Wadekar } 12041612559SVarun Wadekar 12141612559SVarun Wadekar /******************************************************************************* 12241612559SVarun Wadekar * Maximum supported UART controllers 12341612559SVarun Wadekar ******************************************************************************/ 12441612559SVarun Wadekar #define TEGRA186_MAX_UART_PORTS 7 12541612559SVarun Wadekar 12641612559SVarun Wadekar /******************************************************************************* 12741612559SVarun Wadekar * This variable holds the UART port base addresses 12841612559SVarun Wadekar ******************************************************************************/ 12941612559SVarun Wadekar static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = { 13041612559SVarun Wadekar 0, /* undefined - treated as an error case */ 13141612559SVarun Wadekar TEGRA_UARTA_BASE, 13241612559SVarun Wadekar TEGRA_UARTB_BASE, 13341612559SVarun Wadekar TEGRA_UARTC_BASE, 13441612559SVarun Wadekar TEGRA_UARTD_BASE, 13541612559SVarun Wadekar TEGRA_UARTE_BASE, 13641612559SVarun Wadekar TEGRA_UARTF_BASE, 13741612559SVarun Wadekar TEGRA_UARTG_BASE, 13841612559SVarun Wadekar }; 13941612559SVarun Wadekar 14041612559SVarun Wadekar /******************************************************************************* 14141612559SVarun Wadekar * Retrieve the UART controller base to be used as the console 14241612559SVarun Wadekar ******************************************************************************/ 14341612559SVarun Wadekar uint32_t plat_get_console_from_id(int id) 14441612559SVarun Wadekar { 14541612559SVarun Wadekar if (id > TEGRA186_MAX_UART_PORTS) 14641612559SVarun Wadekar return 0; 14741612559SVarun Wadekar 14841612559SVarun Wadekar return tegra186_uart_addresses[id]; 14941612559SVarun Wadekar } 15041612559SVarun Wadekar 15141612559SVarun Wadekar /******************************************************************************* 15241612559SVarun Wadekar * Handler for early platform setup 15341612559SVarun Wadekar ******************************************************************************/ 15441612559SVarun Wadekar void plat_early_platform_setup(void) 15541612559SVarun Wadekar { 15641612559SVarun Wadekar 15741612559SVarun Wadekar /* sanity check MCE firmware compatibility */ 15841612559SVarun Wadekar mce_verify_firmware_version(); 15941612559SVarun Wadekar 160bc019041SAjay Gupta /* Program XUSB STREAMIDs 161bc019041SAjay Gupta * Xavier XUSB has support for XUSB virtualization. It will have one 162bc019041SAjay Gupta * physical function (PF) and four Virtual function (VF) 163bc019041SAjay Gupta * 164bc019041SAjay Gupta * There were below two SIDs for XUSB until T186. 165bc019041SAjay Gupta * 1) #define TEGRA_SID_XUSB_HOST 0x1bU 166bc019041SAjay Gupta * 2) #define TEGRA_SID_XUSB_DEV 0x1cU 167bc019041SAjay Gupta * 168bc019041SAjay Gupta * We have below four new SIDs added for VF(s) 169bc019041SAjay Gupta * 3) #define TEGRA_SID_XUSB_VF0 0x5dU 170bc019041SAjay Gupta * 4) #define TEGRA_SID_XUSB_VF1 0x5eU 171bc019041SAjay Gupta * 5) #define TEGRA_SID_XUSB_VF2 0x5fU 172bc019041SAjay Gupta * 6) #define TEGRA_SID_XUSB_VF3 0x60U 173bc019041SAjay Gupta * 174bc019041SAjay Gupta * When virtualization is enabled then we have to disable SID override 175bc019041SAjay Gupta * and program above SIDs in below newly added SID registers in XUSB 176bc019041SAjay Gupta * PADCTL MMIO space. These registers are TZ protected and so need to 177bc019041SAjay Gupta * be done in ATF. 178bc019041SAjay Gupta * a) #define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 (0x136cU) 179bc019041SAjay Gupta * b) #define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0 (0x139cU) 180bc019041SAjay Gupta * c) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 (0x1370U) 181bc019041SAjay Gupta * d) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 (0x1374U) 182bc019041SAjay Gupta * e) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 (0x1378U) 183bc019041SAjay Gupta * f) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 (0x137cU) 184bc019041SAjay Gupta * 185bc019041SAjay Gupta * This change disables SID override and programs XUSB SIDs in 186bc019041SAjay Gupta * above registers to support both virtualization and non-virtualization 187bc019041SAjay Gupta * 188bc019041SAjay Gupta * Known Limitations: 189bc019041SAjay Gupta * If xusb interface disables SMMU in XUSB DT in non-virtualization 190bc019041SAjay Gupta * setup then there will be SMMU fault. We need to use WAR at 191bc019041SAjay Gupta * https://git-master.nvidia.com/r/1529227/ to the issue. 192bc019041SAjay Gupta * 193bc019041SAjay Gupta * More details can be found in the bug 1971161 194bc019041SAjay Gupta */ 195bc019041SAjay Gupta mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 196bc019041SAjay Gupta XUSB_PADCTL_HOST_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_HOST); 197bc019041SAjay Gupta mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 198bc019041SAjay Gupta XUSB_PADCTL_HOST_AXI_STREAMID_VF_0, TEGRA_SID_XUSB_VF0); 199bc019041SAjay Gupta mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 200bc019041SAjay Gupta XUSB_PADCTL_HOST_AXI_STREAMID_VF_1, TEGRA_SID_XUSB_VF1); 201bc019041SAjay Gupta mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 202bc019041SAjay Gupta XUSB_PADCTL_HOST_AXI_STREAMID_VF_2, TEGRA_SID_XUSB_VF2); 203bc019041SAjay Gupta mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 204bc019041SAjay Gupta XUSB_PADCTL_HOST_AXI_STREAMID_VF_3, TEGRA_SID_XUSB_VF3); 205bc019041SAjay Gupta mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 206bc019041SAjay Gupta XUSB_PADCTL_DEV_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_DEV); 20741612559SVarun Wadekar } 20841612559SVarun Wadekar 20941612559SVarun Wadekar /* Secure IRQs for Tegra186 */ 21041612559SVarun Wadekar static const irq_sec_cfg_t tegra186_sec_irqs[] = { 21141612559SVarun Wadekar [0] = { 21241612559SVarun Wadekar TEGRA186_BPMP_WDT_IRQ, 21341612559SVarun Wadekar TEGRA186_SEC_IRQ_TARGET_MASK, 21441612559SVarun Wadekar INTR_TYPE_EL3, 21541612559SVarun Wadekar }, 21641612559SVarun Wadekar [1] = { 21741612559SVarun Wadekar TEGRA186_BPMP_WDT_IRQ, 21841612559SVarun Wadekar TEGRA186_SEC_IRQ_TARGET_MASK, 21941612559SVarun Wadekar INTR_TYPE_EL3, 22041612559SVarun Wadekar }, 22141612559SVarun Wadekar [2] = { 22241612559SVarun Wadekar TEGRA186_SPE_WDT_IRQ, 22341612559SVarun Wadekar TEGRA186_SEC_IRQ_TARGET_MASK, 22441612559SVarun Wadekar INTR_TYPE_EL3, 22541612559SVarun Wadekar }, 22641612559SVarun Wadekar [3] = { 22741612559SVarun Wadekar TEGRA186_SCE_WDT_IRQ, 22841612559SVarun Wadekar TEGRA186_SEC_IRQ_TARGET_MASK, 22941612559SVarun Wadekar INTR_TYPE_EL3, 23041612559SVarun Wadekar }, 23141612559SVarun Wadekar [4] = { 23241612559SVarun Wadekar TEGRA186_TOP_WDT_IRQ, 23341612559SVarun Wadekar TEGRA186_SEC_IRQ_TARGET_MASK, 23441612559SVarun Wadekar INTR_TYPE_EL3, 23541612559SVarun Wadekar }, 23641612559SVarun Wadekar [5] = { 23741612559SVarun Wadekar TEGRA186_AON_WDT_IRQ, 23841612559SVarun Wadekar TEGRA186_SEC_IRQ_TARGET_MASK, 23941612559SVarun Wadekar INTR_TYPE_EL3, 24041612559SVarun Wadekar }, 24141612559SVarun Wadekar }; 24241612559SVarun Wadekar 24341612559SVarun Wadekar /******************************************************************************* 24441612559SVarun Wadekar * Initialize the GIC and SGIs 24541612559SVarun Wadekar ******************************************************************************/ 24641612559SVarun Wadekar void plat_gic_setup(void) 24741612559SVarun Wadekar { 24841612559SVarun Wadekar tegra_gic_setup(tegra186_sec_irqs, 24941612559SVarun Wadekar sizeof(tegra186_sec_irqs) / sizeof(tegra186_sec_irqs[0])); 25041612559SVarun Wadekar 25141612559SVarun Wadekar /* 25241612559SVarun Wadekar * Initialize the FIQ handler only if the platform supports any 25341612559SVarun Wadekar * FIQ interrupt sources. 25441612559SVarun Wadekar */ 25541612559SVarun Wadekar if (sizeof(tegra186_sec_irqs) > 0) 25641612559SVarun Wadekar tegra_fiq_handler_setup(); 25741612559SVarun Wadekar } 25841612559SVarun Wadekar 25941612559SVarun Wadekar /******************************************************************************* 26041612559SVarun Wadekar * Return pointer to the BL31 params from previous bootloader 26141612559SVarun Wadekar ******************************************************************************/ 26241612559SVarun Wadekar struct tegra_bl31_params *plat_get_bl31_params(void) 26341612559SVarun Wadekar { 26441612559SVarun Wadekar uint32_t val; 26541612559SVarun Wadekar 26641612559SVarun Wadekar val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_LO); 26741612559SVarun Wadekar 26841612559SVarun Wadekar return (struct tegra_bl31_params *)(uintptr_t)val; 26941612559SVarun Wadekar } 27041612559SVarun Wadekar 27141612559SVarun Wadekar /******************************************************************************* 27241612559SVarun Wadekar * Return pointer to the BL31 platform params from previous bootloader 27341612559SVarun Wadekar ******************************************************************************/ 27441612559SVarun Wadekar plat_params_from_bl2_t *plat_get_bl31_plat_params(void) 27541612559SVarun Wadekar { 27641612559SVarun Wadekar uint32_t val; 27741612559SVarun Wadekar 27841612559SVarun Wadekar val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_HI); 27941612559SVarun Wadekar 28041612559SVarun Wadekar return (plat_params_from_bl2_t *)(uintptr_t)val; 28141612559SVarun Wadekar } 282