1 /* 2 * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <common/debug.h> 9 #include <lib/mmio.h> 10 #include <mce.h> 11 #include <string.h> 12 #include <tegra194_private.h> 13 #include <tegra_def.h> 14 #include <tegra_private.h> 15 16 extern uint64_t tegra_bl31_phys_base; 17 18 #define MISCREG_AA64_RST_LOW 0x2004U 19 #define MISCREG_AA64_RST_HIGH 0x2008U 20 21 #define CPU_RESET_MODE_AA64 1U 22 23 /******************************************************************************* 24 * Setup secondary CPU vectors 25 ******************************************************************************/ 26 void plat_secondary_setup(void) 27 { 28 uint32_t addr_low, addr_high; 29 plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); 30 uint64_t cpu_reset_handler_base, cpu_reset_handler_size, tzdram_addr; 31 uint64_t src_len_bytes = BL_END - tegra_bl31_phys_base; 32 33 INFO("Setting up secondary CPU boot\n"); 34 35 tzdram_addr = params_from_bl2->tzdram_base + 36 tegra194_get_cpu_reset_handler_size(); 37 38 /* 39 * The BL31 code resides in the TZSRAM which loses state 40 * when we enter System Suspend. Copy the wakeup trampoline 41 * code to TZDRAM to help us exit from System Suspend. 42 */ 43 cpu_reset_handler_base = tegra194_get_cpu_reset_handler_base(); 44 cpu_reset_handler_size = tegra194_get_cpu_reset_handler_size(); 45 memcpy((void *)((uintptr_t)params_from_bl2->tzdram_base), 46 (void *)((uintptr_t)cpu_reset_handler_base), 47 cpu_reset_handler_size); 48 49 /* TZDRAM base will be used as the "resume" address */ 50 addr_low = (uint32_t)params_from_bl2->tzdram_base | CPU_RESET_MODE_AA64; 51 addr_high = (uint32_t)((params_from_bl2->tzdram_base >> 32U) & 0x7ffU); 52 53 /* write lower 32 bits first, then the upper 11 bits */ 54 mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_LOW, addr_low); 55 mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_HIGH, addr_high); 56 57 /* save reset vector to be used during SYSTEM_SUSPEND exit */ 58 mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_LO, 59 addr_low); 60 mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_HI, 61 addr_high); 62 mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV72_LO, 63 (uint32_t)tzdram_addr); 64 mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV72_HI, 65 (uint32_t)src_len_bytes); 66 } 67