141612559SVarun Wadekar /* 241612559SVarun Wadekar * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. 341612559SVarun Wadekar * 441612559SVarun Wadekar * SPDX-License-Identifier: BSD-3-Clause 541612559SVarun Wadekar */ 641612559SVarun Wadekar 741612559SVarun Wadekar #include <arch_helpers.h> 841612559SVarun Wadekar #include <common/debug.h> 941612559SVarun Wadekar #include <lib/mmio.h> 1041612559SVarun Wadekar #include <mce.h> 1141612559SVarun Wadekar #include <string.h> 1241612559SVarun Wadekar #include <tegra_def.h> 1341612559SVarun Wadekar #include <tegra_private.h> 1441612559SVarun Wadekar 15*b6533b56SAnthony Zhou #define MISCREG_CPU_RESET_VECTOR 0x2000U 16*b6533b56SAnthony Zhou #define MISCREG_AA64_RST_LOW 0x2004U 17*b6533b56SAnthony Zhou #define MISCREG_AA64_RST_HIGH 0x2008U 1841612559SVarun Wadekar 19*b6533b56SAnthony Zhou #define CPU_RESET_MODE_AA64 1U 2041612559SVarun Wadekar 2141612559SVarun Wadekar extern void tegra_secure_entrypoint(void); 2241612559SVarun Wadekar 2341612559SVarun Wadekar #if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM 2441612559SVarun Wadekar extern void tegra186_cpu_reset_handler(void); 2541612559SVarun Wadekar extern uint64_t __tegra186_smmu_ctx_start; 2641612559SVarun Wadekar #endif 2741612559SVarun Wadekar 2841612559SVarun Wadekar /******************************************************************************* 2941612559SVarun Wadekar * Setup secondary CPU vectors 3041612559SVarun Wadekar ******************************************************************************/ 3141612559SVarun Wadekar void plat_secondary_setup(void) 3241612559SVarun Wadekar { 3341612559SVarun Wadekar uint32_t addr_low, addr_high; 3441612559SVarun Wadekar #if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM 3541612559SVarun Wadekar plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); 3641612559SVarun Wadekar uint64_t cpu_reset_handler_base = params_from_bl2->tzdram_base; 3741612559SVarun Wadekar #else 3841612559SVarun Wadekar uint64_t cpu_reset_handler_base = (uintptr_t)tegra_secure_entrypoint; 3941612559SVarun Wadekar #endif 4041612559SVarun Wadekar 4141612559SVarun Wadekar INFO("Setting up secondary CPU boot\n"); 4241612559SVarun Wadekar 4341612559SVarun Wadekar #if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM 4441612559SVarun Wadekar memcpy((void *)((uintptr_t)cpu_reset_handler_base), 4541612559SVarun Wadekar (void *)(uintptr_t)tegra186_cpu_reset_handler, 4641612559SVarun Wadekar (uintptr_t)&__tegra186_smmu_ctx_start - 47*b6533b56SAnthony Zhou (uintptr_t)&tegra186_cpu_reset_handler); 4841612559SVarun Wadekar #endif 4941612559SVarun Wadekar 5041612559SVarun Wadekar addr_low = (uint32_t)cpu_reset_handler_base | CPU_RESET_MODE_AA64; 51*b6533b56SAnthony Zhou addr_high = (uint32_t)((cpu_reset_handler_base >> 32U) & 0x7ffU); 5241612559SVarun Wadekar 5341612559SVarun Wadekar /* write lower 32 bits first, then the upper 11 bits */ 5441612559SVarun Wadekar mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_LOW, addr_low); 5541612559SVarun Wadekar mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_HIGH, addr_high); 5641612559SVarun Wadekar 5741612559SVarun Wadekar /* save reset vector to be used during SYSTEM_SUSPEND exit */ 5841612559SVarun Wadekar mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV1_LO, 5941612559SVarun Wadekar addr_low); 6041612559SVarun Wadekar mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV1_HI, 6141612559SVarun Wadekar addr_high); 6241612559SVarun Wadekar } 63