1*41612559SVarun Wadekar /* 2*41612559SVarun Wadekar * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. 3*41612559SVarun Wadekar * 4*41612559SVarun Wadekar * SPDX-License-Identifier: BSD-3-Clause 5*41612559SVarun Wadekar */ 6*41612559SVarun Wadekar 7*41612559SVarun Wadekar #include <arch_helpers.h> 8*41612559SVarun Wadekar #include <common/debug.h> 9*41612559SVarun Wadekar #include <lib/mmio.h> 10*41612559SVarun Wadekar #include <mce.h> 11*41612559SVarun Wadekar #include <string.h> 12*41612559SVarun Wadekar #include <tegra_def.h> 13*41612559SVarun Wadekar #include <tegra_private.h> 14*41612559SVarun Wadekar 15*41612559SVarun Wadekar #define MISCREG_CPU_RESET_VECTOR 0x2000 16*41612559SVarun Wadekar #define MISCREG_AA64_RST_LOW 0x2004 17*41612559SVarun Wadekar #define MISCREG_AA64_RST_HIGH 0x2008 18*41612559SVarun Wadekar 19*41612559SVarun Wadekar #define CPU_RESET_MODE_AA64 1 20*41612559SVarun Wadekar 21*41612559SVarun Wadekar extern void tegra_secure_entrypoint(void); 22*41612559SVarun Wadekar 23*41612559SVarun Wadekar #if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM 24*41612559SVarun Wadekar extern void tegra186_cpu_reset_handler(void); 25*41612559SVarun Wadekar extern uint64_t __tegra186_smmu_ctx_start; 26*41612559SVarun Wadekar #endif 27*41612559SVarun Wadekar 28*41612559SVarun Wadekar /******************************************************************************* 29*41612559SVarun Wadekar * Setup secondary CPU vectors 30*41612559SVarun Wadekar ******************************************************************************/ 31*41612559SVarun Wadekar void plat_secondary_setup(void) 32*41612559SVarun Wadekar { 33*41612559SVarun Wadekar uint32_t addr_low, addr_high; 34*41612559SVarun Wadekar #if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM 35*41612559SVarun Wadekar plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); 36*41612559SVarun Wadekar uint64_t cpu_reset_handler_base = params_from_bl2->tzdram_base; 37*41612559SVarun Wadekar #else 38*41612559SVarun Wadekar uint64_t cpu_reset_handler_base = (uintptr_t)tegra_secure_entrypoint; 39*41612559SVarun Wadekar #endif 40*41612559SVarun Wadekar 41*41612559SVarun Wadekar INFO("Setting up secondary CPU boot\n"); 42*41612559SVarun Wadekar 43*41612559SVarun Wadekar #if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM 44*41612559SVarun Wadekar memcpy((void *)((uintptr_t)cpu_reset_handler_base), 45*41612559SVarun Wadekar (void *)(uintptr_t)tegra186_cpu_reset_handler, 46*41612559SVarun Wadekar (uintptr_t)&__tegra186_smmu_ctx_start - 47*41612559SVarun Wadekar (uintptr_t)tegra186_cpu_reset_handler); 48*41612559SVarun Wadekar #endif 49*41612559SVarun Wadekar 50*41612559SVarun Wadekar addr_low = (uint32_t)cpu_reset_handler_base | CPU_RESET_MODE_AA64; 51*41612559SVarun Wadekar addr_high = (uint32_t)((cpu_reset_handler_base >> 32) & 0x7ff); 52*41612559SVarun Wadekar 53*41612559SVarun Wadekar /* write lower 32 bits first, then the upper 11 bits */ 54*41612559SVarun Wadekar mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_LOW, addr_low); 55*41612559SVarun Wadekar mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_HIGH, addr_high); 56*41612559SVarun Wadekar 57*41612559SVarun Wadekar /* save reset vector to be used during SYSTEM_SUSPEND exit */ 58*41612559SVarun Wadekar mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV1_LO, 59*41612559SVarun Wadekar addr_low); 60*41612559SVarun Wadekar mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV1_HI, 61*41612559SVarun Wadekar addr_high); 62*41612559SVarun Wadekar 63*41612559SVarun Wadekar /* update reset vector address to the CCPLEX */ 64*41612559SVarun Wadekar mce_update_reset_vector(); 65*41612559SVarun Wadekar } 66