141612559SVarun Wadekar /* 22ac7b223SJeetesh Burman * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. 341612559SVarun Wadekar * 441612559SVarun Wadekar * SPDX-License-Identifier: BSD-3-Clause 541612559SVarun Wadekar */ 641612559SVarun Wadekar 7*2561cb50SAnthony Zhou #include <assert.h> 8*2561cb50SAnthony Zhou #include <string.h> 9*2561cb50SAnthony Zhou 1041612559SVarun Wadekar #include <arch_helpers.h> 1141612559SVarun Wadekar #include <common/debug.h> 1241612559SVarun Wadekar #include <lib/mmio.h> 13*2561cb50SAnthony Zhou 1441612559SVarun Wadekar #include <mce.h> 15653fc380SVarun Wadekar #include <tegra194_private.h> 1641612559SVarun Wadekar #include <tegra_def.h> 1741612559SVarun Wadekar #include <tegra_private.h> 1841612559SVarun Wadekar 192ac7b223SJeetesh Burman extern uint64_t tegra_bl31_phys_base; 202ac7b223SJeetesh Burman 21b6533b56SAnthony Zhou #define MISCREG_AA64_RST_LOW 0x2004U 22b6533b56SAnthony Zhou #define MISCREG_AA64_RST_HIGH 0x2008U 2341612559SVarun Wadekar 24b6533b56SAnthony Zhou #define CPU_RESET_MODE_AA64 1U 2541612559SVarun Wadekar 2641612559SVarun Wadekar /******************************************************************************* 2741612559SVarun Wadekar * Setup secondary CPU vectors 2841612559SVarun Wadekar ******************************************************************************/ 2941612559SVarun Wadekar void plat_secondary_setup(void) 3041612559SVarun Wadekar { 3141612559SVarun Wadekar uint32_t addr_low, addr_high; 3241612559SVarun Wadekar plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); 332ac7b223SJeetesh Burman uint64_t cpu_reset_handler_base, cpu_reset_handler_size, tzdram_addr; 342ac7b223SJeetesh Burman uint64_t src_len_bytes = BL_END - tegra_bl31_phys_base; 3541612559SVarun Wadekar 3641612559SVarun Wadekar INFO("Setting up secondary CPU boot\n"); 3741612559SVarun Wadekar 382ac7b223SJeetesh Burman tzdram_addr = params_from_bl2->tzdram_base + 392ac7b223SJeetesh Burman tegra194_get_cpu_reset_handler_size(); 402ac7b223SJeetesh Burman 41653fc380SVarun Wadekar /* 42653fc380SVarun Wadekar * The BL31 code resides in the TZSRAM which loses state 43653fc380SVarun Wadekar * when we enter System Suspend. Copy the wakeup trampoline 44653fc380SVarun Wadekar * code to TZDRAM to help us exit from System Suspend. 45653fc380SVarun Wadekar */ 46653fc380SVarun Wadekar cpu_reset_handler_base = tegra194_get_cpu_reset_handler_base(); 47653fc380SVarun Wadekar cpu_reset_handler_size = tegra194_get_cpu_reset_handler_size(); 48653fc380SVarun Wadekar memcpy((void *)((uintptr_t)params_from_bl2->tzdram_base), 49653fc380SVarun Wadekar (void *)((uintptr_t)cpu_reset_handler_base), 50653fc380SVarun Wadekar cpu_reset_handler_size); 5141612559SVarun Wadekar 52653fc380SVarun Wadekar /* TZDRAM base will be used as the "resume" address */ 53653fc380SVarun Wadekar addr_low = (uint32_t)params_from_bl2->tzdram_base | CPU_RESET_MODE_AA64; 54653fc380SVarun Wadekar addr_high = (uint32_t)((params_from_bl2->tzdram_base >> 32U) & 0x7ffU); 5541612559SVarun Wadekar 5641612559SVarun Wadekar /* write lower 32 bits first, then the upper 11 bits */ 5741612559SVarun Wadekar mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_LOW, addr_low); 58*2561cb50SAnthony Zhou assert(mmio_read_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_LOW) == addr_low); 5941612559SVarun Wadekar mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_HIGH, addr_high); 60*2561cb50SAnthony Zhou assert(mmio_read_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_HIGH) == addr_high); 6141612559SVarun Wadekar 6241612559SVarun Wadekar /* save reset vector to be used during SYSTEM_SUSPEND exit */ 63192fd367SSteven Kao mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_LO, 6441612559SVarun Wadekar addr_low); 65*2561cb50SAnthony Zhou assert(mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_LO) == addr_low); 66192fd367SSteven Kao mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_HI, 6741612559SVarun Wadekar addr_high); 68*2561cb50SAnthony Zhou assert(mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_HI) == addr_high); 692ac7b223SJeetesh Burman mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV72_LO, 702ac7b223SJeetesh Burman (uint32_t)tzdram_addr); 71*2561cb50SAnthony Zhou assert(mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV72_LO) == (uint32_t)tzdram_addr); 722ac7b223SJeetesh Burman mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV72_HI, 732ac7b223SJeetesh Burman (uint32_t)src_len_bytes); 74*2561cb50SAnthony Zhou assert(mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV72_HI) == (uint32_t)src_len_bytes); 7541612559SVarun Wadekar } 76