1 /* 2 * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <common/bl_common.h> 9 #include <mce.h> 10 #include <memctrl_v2.h> 11 #include <tegra_mc_def.h> 12 #include <tegra_platform.h> 13 14 /******************************************************************************* 15 * Array to hold stream_id override config register offsets 16 ******************************************************************************/ 17 const static uint32_t tegra194_streamid_override_regs[] = { 18 MC_STREAMID_OVERRIDE_CFG_HDAR, 19 MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR, 20 MC_STREAMID_OVERRIDE_CFG_NVENCSRD, 21 MC_STREAMID_OVERRIDE_CFG_SATAR, 22 MC_STREAMID_OVERRIDE_CFG_NVENCSWR, 23 MC_STREAMID_OVERRIDE_CFG_HDAW, 24 MC_STREAMID_OVERRIDE_CFG_SATAW, 25 MC_STREAMID_OVERRIDE_CFG_ISPRA, 26 MC_STREAMID_OVERRIDE_CFG_ISPFALR, 27 MC_STREAMID_OVERRIDE_CFG_ISPWA, 28 MC_STREAMID_OVERRIDE_CFG_ISPWB, 29 MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR, 30 MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW, 31 MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR, 32 MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW, 33 MC_STREAMID_OVERRIDE_CFG_TSECSRD, 34 MC_STREAMID_OVERRIDE_CFG_TSECSWR, 35 MC_STREAMID_OVERRIDE_CFG_SDMMCRA, 36 MC_STREAMID_OVERRIDE_CFG_SDMMCR, 37 MC_STREAMID_OVERRIDE_CFG_SDMMCRAB, 38 MC_STREAMID_OVERRIDE_CFG_SDMMCWA, 39 MC_STREAMID_OVERRIDE_CFG_SDMMCW, 40 MC_STREAMID_OVERRIDE_CFG_SDMMCWAB, 41 MC_STREAMID_OVERRIDE_CFG_VICSRD, 42 MC_STREAMID_OVERRIDE_CFG_VICSWR, 43 MC_STREAMID_OVERRIDE_CFG_VIW, 44 MC_STREAMID_OVERRIDE_CFG_NVDECSRD, 45 MC_STREAMID_OVERRIDE_CFG_NVDECSWR, 46 MC_STREAMID_OVERRIDE_CFG_APER, 47 MC_STREAMID_OVERRIDE_CFG_APEW, 48 MC_STREAMID_OVERRIDE_CFG_NVJPGSRD, 49 MC_STREAMID_OVERRIDE_CFG_NVJPGSWR, 50 MC_STREAMID_OVERRIDE_CFG_SESRD, 51 MC_STREAMID_OVERRIDE_CFG_SESWR, 52 MC_STREAMID_OVERRIDE_CFG_AXIAPR, 53 MC_STREAMID_OVERRIDE_CFG_AXIAPW, 54 MC_STREAMID_OVERRIDE_CFG_ETRR, 55 MC_STREAMID_OVERRIDE_CFG_ETRW, 56 MC_STREAMID_OVERRIDE_CFG_TSECSRDB, 57 MC_STREAMID_OVERRIDE_CFG_TSECSWRB, 58 MC_STREAMID_OVERRIDE_CFG_AXISR, 59 MC_STREAMID_OVERRIDE_CFG_AXISW, 60 MC_STREAMID_OVERRIDE_CFG_EQOSR, 61 MC_STREAMID_OVERRIDE_CFG_EQOSW, 62 MC_STREAMID_OVERRIDE_CFG_UFSHCR, 63 MC_STREAMID_OVERRIDE_CFG_UFSHCW, 64 MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR, 65 MC_STREAMID_OVERRIDE_CFG_BPMPR, 66 MC_STREAMID_OVERRIDE_CFG_BPMPW, 67 MC_STREAMID_OVERRIDE_CFG_BPMPDMAR, 68 MC_STREAMID_OVERRIDE_CFG_BPMPDMAW, 69 MC_STREAMID_OVERRIDE_CFG_AONR, 70 MC_STREAMID_OVERRIDE_CFG_AONW, 71 MC_STREAMID_OVERRIDE_CFG_AONDMAR, 72 MC_STREAMID_OVERRIDE_CFG_AONDMAW, 73 MC_STREAMID_OVERRIDE_CFG_SCER, 74 MC_STREAMID_OVERRIDE_CFG_SCEW, 75 MC_STREAMID_OVERRIDE_CFG_SCEDMAR, 76 MC_STREAMID_OVERRIDE_CFG_SCEDMAW, 77 MC_STREAMID_OVERRIDE_CFG_APEDMAR, 78 MC_STREAMID_OVERRIDE_CFG_APEDMAW, 79 MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1, 80 MC_STREAMID_OVERRIDE_CFG_VICSRD1, 81 MC_STREAMID_OVERRIDE_CFG_NVDECSRD1, 82 MC_STREAMID_OVERRIDE_CFG_VIFALR, 83 MC_STREAMID_OVERRIDE_CFG_VIFALW, 84 MC_STREAMID_OVERRIDE_CFG_DLA0RDA, 85 MC_STREAMID_OVERRIDE_CFG_DLA0FALRDB, 86 MC_STREAMID_OVERRIDE_CFG_DLA0WRA, 87 MC_STREAMID_OVERRIDE_CFG_DLA0FALWRB, 88 MC_STREAMID_OVERRIDE_CFG_DLA1RDA, 89 MC_STREAMID_OVERRIDE_CFG_DLA1FALRDB, 90 MC_STREAMID_OVERRIDE_CFG_DLA1WRA, 91 MC_STREAMID_OVERRIDE_CFG_DLA1FALWRB, 92 MC_STREAMID_OVERRIDE_CFG_PVA0RDA, 93 MC_STREAMID_OVERRIDE_CFG_PVA0RDB, 94 MC_STREAMID_OVERRIDE_CFG_PVA0RDC, 95 MC_STREAMID_OVERRIDE_CFG_PVA0WRA, 96 MC_STREAMID_OVERRIDE_CFG_PVA0WRB, 97 MC_STREAMID_OVERRIDE_CFG_PVA0WRC, 98 MC_STREAMID_OVERRIDE_CFG_PVA1RDA, 99 MC_STREAMID_OVERRIDE_CFG_PVA1RDB, 100 MC_STREAMID_OVERRIDE_CFG_PVA1RDC, 101 MC_STREAMID_OVERRIDE_CFG_PVA1WRA, 102 MC_STREAMID_OVERRIDE_CFG_PVA1WRB, 103 MC_STREAMID_OVERRIDE_CFG_PVA1WRC, 104 MC_STREAMID_OVERRIDE_CFG_RCER, 105 MC_STREAMID_OVERRIDE_CFG_RCEW, 106 MC_STREAMID_OVERRIDE_CFG_RCEDMAR, 107 MC_STREAMID_OVERRIDE_CFG_RCEDMAW, 108 MC_STREAMID_OVERRIDE_CFG_NVENC1SRD, 109 MC_STREAMID_OVERRIDE_CFG_NVENC1SWR, 110 MC_STREAMID_OVERRIDE_CFG_PCIE0R, 111 MC_STREAMID_OVERRIDE_CFG_PCIE0W, 112 MC_STREAMID_OVERRIDE_CFG_PCIE1R, 113 MC_STREAMID_OVERRIDE_CFG_PCIE1W, 114 MC_STREAMID_OVERRIDE_CFG_PCIE2AR, 115 MC_STREAMID_OVERRIDE_CFG_PCIE2AW, 116 MC_STREAMID_OVERRIDE_CFG_PCIE3R, 117 MC_STREAMID_OVERRIDE_CFG_PCIE3W, 118 MC_STREAMID_OVERRIDE_CFG_PCIE4R, 119 MC_STREAMID_OVERRIDE_CFG_PCIE4W, 120 MC_STREAMID_OVERRIDE_CFG_PCIE5R, 121 MC_STREAMID_OVERRIDE_CFG_PCIE5W, 122 MC_STREAMID_OVERRIDE_CFG_ISPFALW, 123 MC_STREAMID_OVERRIDE_CFG_DLA0RDA1, 124 MC_STREAMID_OVERRIDE_CFG_DLA1RDA1, 125 MC_STREAMID_OVERRIDE_CFG_PVA0RDA1, 126 MC_STREAMID_OVERRIDE_CFG_PVA0RDB1, 127 MC_STREAMID_OVERRIDE_CFG_PVA1RDA1, 128 MC_STREAMID_OVERRIDE_CFG_PVA1RDB1, 129 MC_STREAMID_OVERRIDE_CFG_PCIE5R1, 130 MC_STREAMID_OVERRIDE_CFG_NVENCSRD1, 131 MC_STREAMID_OVERRIDE_CFG_NVENC1SRD1, 132 MC_STREAMID_OVERRIDE_CFG_ISPRA1, 133 MC_STREAMID_OVERRIDE_CFG_MIU0R, 134 MC_STREAMID_OVERRIDE_CFG_MIU0W, 135 MC_STREAMID_OVERRIDE_CFG_MIU1R, 136 MC_STREAMID_OVERRIDE_CFG_MIU1W, 137 MC_STREAMID_OVERRIDE_CFG_MIU2R, 138 MC_STREAMID_OVERRIDE_CFG_MIU2W, 139 MC_STREAMID_OVERRIDE_CFG_MIU3R, 140 MC_STREAMID_OVERRIDE_CFG_MIU3W 141 }; 142 143 /******************************************************************************* 144 * Array to hold the security configs for stream IDs 145 ******************************************************************************/ 146 const static mc_streamid_security_cfg_t tegra194_streamid_sec_cfgs[] = { 147 mc_make_sec_cfg(HDAR, NON_SECURE, OVERRIDE, ENABLE), 148 mc_make_sec_cfg(HOST1XDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), 149 mc_make_sec_cfg(NVENCSRD, NON_SECURE, NO_OVERRIDE, ENABLE), 150 mc_make_sec_cfg(SATAR, NON_SECURE, OVERRIDE, ENABLE), 151 mc_make_sec_cfg(NVENCSWR, NON_SECURE, NO_OVERRIDE, ENABLE), 152 mc_make_sec_cfg(HDAW, NON_SECURE, OVERRIDE, ENABLE), 153 mc_make_sec_cfg(SATAW, NON_SECURE, OVERRIDE, ENABLE), 154 mc_make_sec_cfg(ISPRA, NON_SECURE, NO_OVERRIDE, ENABLE), 155 mc_make_sec_cfg(ISPFALR, NON_SECURE, NO_OVERRIDE, ENABLE), 156 mc_make_sec_cfg(ISPWA, NON_SECURE, NO_OVERRIDE, ENABLE), 157 mc_make_sec_cfg(ISPWB, NON_SECURE, NO_OVERRIDE, ENABLE), 158 mc_make_sec_cfg(XUSB_HOSTR, NON_SECURE, NO_OVERRIDE, ENABLE), 159 mc_make_sec_cfg(XUSB_HOSTW, NON_SECURE, NO_OVERRIDE, ENABLE), 160 mc_make_sec_cfg(XUSB_DEVR, NON_SECURE, NO_OVERRIDE, ENABLE), 161 mc_make_sec_cfg(XUSB_DEVW, NON_SECURE, NO_OVERRIDE, ENABLE), 162 mc_make_sec_cfg(TSECSRD, NON_SECURE, NO_OVERRIDE, ENABLE), 163 mc_make_sec_cfg(TSECSWR, NON_SECURE, NO_OVERRIDE, ENABLE), 164 mc_make_sec_cfg(SDMMCRA, NON_SECURE, OVERRIDE, ENABLE), 165 mc_make_sec_cfg(SDMMCR, NON_SECURE, OVERRIDE, ENABLE), 166 mc_make_sec_cfg(SDMMCRAB, NON_SECURE, OVERRIDE, ENABLE), 167 mc_make_sec_cfg(SDMMCWA, NON_SECURE, OVERRIDE, ENABLE), 168 mc_make_sec_cfg(SDMMCW, NON_SECURE, OVERRIDE, ENABLE), 169 mc_make_sec_cfg(SDMMCWAB, NON_SECURE, OVERRIDE, ENABLE), 170 mc_make_sec_cfg(VICSRD, NON_SECURE, NO_OVERRIDE, ENABLE), 171 mc_make_sec_cfg(VICSWR, NON_SECURE, NO_OVERRIDE, ENABLE), 172 mc_make_sec_cfg(VIW, NON_SECURE, NO_OVERRIDE, ENABLE), 173 mc_make_sec_cfg(NVDECSRD, NON_SECURE, NO_OVERRIDE, ENABLE), 174 mc_make_sec_cfg(NVDECSWR, NON_SECURE, NO_OVERRIDE, ENABLE), 175 mc_make_sec_cfg(APER, NON_SECURE, NO_OVERRIDE, ENABLE), 176 mc_make_sec_cfg(APEW, NON_SECURE, NO_OVERRIDE, ENABLE), 177 mc_make_sec_cfg(NVJPGSRD, NON_SECURE, NO_OVERRIDE, ENABLE), 178 mc_make_sec_cfg(NVJPGSWR, NON_SECURE, NO_OVERRIDE, ENABLE), 179 mc_make_sec_cfg(SESRD, NON_SECURE, NO_OVERRIDE, ENABLE), 180 mc_make_sec_cfg(SESWR, NON_SECURE, NO_OVERRIDE, ENABLE), 181 mc_make_sec_cfg(AXIAPR, NON_SECURE, OVERRIDE, ENABLE), 182 mc_make_sec_cfg(AXIAPW, NON_SECURE, OVERRIDE, ENABLE), 183 mc_make_sec_cfg(ETRR, NON_SECURE, OVERRIDE, ENABLE), 184 mc_make_sec_cfg(ETRW, NON_SECURE, OVERRIDE, ENABLE), 185 mc_make_sec_cfg(TSECSRDB, NON_SECURE, NO_OVERRIDE, ENABLE), 186 mc_make_sec_cfg(TSECSWRB, NON_SECURE, NO_OVERRIDE, ENABLE), 187 mc_make_sec_cfg(AXISR, SECURE, NO_OVERRIDE, DISABLE), 188 mc_make_sec_cfg(AXISW, SECURE, NO_OVERRIDE, DISABLE), 189 mc_make_sec_cfg(EQOSR, NON_SECURE, OVERRIDE, ENABLE), 190 mc_make_sec_cfg(EQOSW, NON_SECURE, OVERRIDE, ENABLE), 191 mc_make_sec_cfg(UFSHCR, NON_SECURE, OVERRIDE, ENABLE), 192 mc_make_sec_cfg(UFSHCW, NON_SECURE, OVERRIDE, ENABLE), 193 mc_make_sec_cfg(NVDISPLAYR, NON_SECURE, OVERRIDE, ENABLE), 194 mc_make_sec_cfg(BPMPR, NON_SECURE, NO_OVERRIDE, ENABLE), 195 mc_make_sec_cfg(BPMPW, NON_SECURE, NO_OVERRIDE, ENABLE), 196 mc_make_sec_cfg(BPMPDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), 197 mc_make_sec_cfg(BPMPDMAW, NON_SECURE, NO_OVERRIDE, ENABLE), 198 mc_make_sec_cfg(AONR, NON_SECURE, NO_OVERRIDE, ENABLE), 199 mc_make_sec_cfg(AONW, NON_SECURE, NO_OVERRIDE, ENABLE), 200 mc_make_sec_cfg(AONDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), 201 mc_make_sec_cfg(AONDMAW, NON_SECURE, NO_OVERRIDE, ENABLE), 202 mc_make_sec_cfg(SCER, NON_SECURE, NO_OVERRIDE, ENABLE), 203 mc_make_sec_cfg(SCEW, NON_SECURE, NO_OVERRIDE, ENABLE), 204 mc_make_sec_cfg(SCEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), 205 mc_make_sec_cfg(SCEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE), 206 mc_make_sec_cfg(APEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), 207 mc_make_sec_cfg(APEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE), 208 mc_make_sec_cfg(NVDISPLAYR1, NON_SECURE, OVERRIDE, ENABLE), 209 mc_make_sec_cfg(VICSRD1, NON_SECURE, NO_OVERRIDE, ENABLE), 210 mc_make_sec_cfg(NVDECSRD1, NON_SECURE, NO_OVERRIDE, ENABLE), 211 mc_make_sec_cfg(VIFALR, NON_SECURE, NO_OVERRIDE, ENABLE), 212 mc_make_sec_cfg(VIFALW, NON_SECURE, NO_OVERRIDE, ENABLE), 213 mc_make_sec_cfg(DLA0RDA, NON_SECURE, NO_OVERRIDE, ENABLE), 214 mc_make_sec_cfg(DLA0FALRDB, NON_SECURE, NO_OVERRIDE, ENABLE), 215 mc_make_sec_cfg(DLA0WRA, NON_SECURE, NO_OVERRIDE, ENABLE), 216 mc_make_sec_cfg(DLA0FALWRB, NON_SECURE, NO_OVERRIDE, ENABLE), 217 mc_make_sec_cfg(DLA1RDA, NON_SECURE, NO_OVERRIDE, ENABLE), 218 mc_make_sec_cfg(DLA1FALRDB, NON_SECURE, NO_OVERRIDE, ENABLE), 219 mc_make_sec_cfg(DLA1WRA, NON_SECURE, NO_OVERRIDE, ENABLE), 220 mc_make_sec_cfg(DLA1FALWRB, NON_SECURE, NO_OVERRIDE, ENABLE), 221 mc_make_sec_cfg(PVA0RDA, NON_SECURE, NO_OVERRIDE, ENABLE), 222 mc_make_sec_cfg(PVA0RDB, NON_SECURE, NO_OVERRIDE, ENABLE), 223 mc_make_sec_cfg(PVA0RDC, NON_SECURE, NO_OVERRIDE, ENABLE), 224 mc_make_sec_cfg(PVA0WRA, NON_SECURE, NO_OVERRIDE, ENABLE), 225 mc_make_sec_cfg(PVA0WRB, NON_SECURE, NO_OVERRIDE, ENABLE), 226 mc_make_sec_cfg(PVA0WRC, NON_SECURE, NO_OVERRIDE, ENABLE), 227 mc_make_sec_cfg(PVA1RDA, NON_SECURE, NO_OVERRIDE, ENABLE), 228 mc_make_sec_cfg(PVA1RDB, NON_SECURE, NO_OVERRIDE, ENABLE), 229 mc_make_sec_cfg(PVA1RDC, NON_SECURE, NO_OVERRIDE, ENABLE), 230 mc_make_sec_cfg(PVA1WRA, NON_SECURE, NO_OVERRIDE, ENABLE), 231 mc_make_sec_cfg(PVA1WRB, NON_SECURE, NO_OVERRIDE, ENABLE), 232 mc_make_sec_cfg(PVA1WRC, NON_SECURE, NO_OVERRIDE, ENABLE), 233 mc_make_sec_cfg(RCER, NON_SECURE, NO_OVERRIDE, ENABLE), 234 mc_make_sec_cfg(RCEW, NON_SECURE, NO_OVERRIDE, ENABLE), 235 mc_make_sec_cfg(RCEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), 236 mc_make_sec_cfg(RCEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE), 237 mc_make_sec_cfg(NVENC1SRD, NON_SECURE, NO_OVERRIDE, ENABLE), 238 mc_make_sec_cfg(NVENC1SWR, NON_SECURE, NO_OVERRIDE, ENABLE), 239 mc_make_sec_cfg(PCIE0R, NON_SECURE, OVERRIDE, ENABLE), 240 mc_make_sec_cfg(PCIE0W, NON_SECURE, OVERRIDE, ENABLE), 241 mc_make_sec_cfg(PCIE1R, NON_SECURE, OVERRIDE, ENABLE), 242 mc_make_sec_cfg(PCIE1W, NON_SECURE, OVERRIDE, ENABLE), 243 mc_make_sec_cfg(PCIE2AR, NON_SECURE, OVERRIDE, ENABLE), 244 mc_make_sec_cfg(PCIE2AW, NON_SECURE, OVERRIDE, ENABLE), 245 mc_make_sec_cfg(PCIE3R, NON_SECURE, OVERRIDE, ENABLE), 246 mc_make_sec_cfg(PCIE3W, NON_SECURE, OVERRIDE, ENABLE), 247 mc_make_sec_cfg(PCIE4R, NON_SECURE, OVERRIDE, ENABLE), 248 mc_make_sec_cfg(PCIE4W, NON_SECURE, OVERRIDE, ENABLE), 249 mc_make_sec_cfg(PCIE5R, NON_SECURE, OVERRIDE, ENABLE), 250 mc_make_sec_cfg(PCIE5W, NON_SECURE, OVERRIDE, ENABLE), 251 mc_make_sec_cfg(ISPFALW, NON_SECURE, NO_OVERRIDE, ENABLE), 252 mc_make_sec_cfg(DLA0RDA1, NON_SECURE, NO_OVERRIDE, ENABLE), 253 mc_make_sec_cfg(DLA1RDA1, NON_SECURE, NO_OVERRIDE, ENABLE), 254 mc_make_sec_cfg(PVA0RDA1, NON_SECURE, NO_OVERRIDE, ENABLE), 255 mc_make_sec_cfg(PVA0RDB1, NON_SECURE, NO_OVERRIDE, ENABLE), 256 mc_make_sec_cfg(PVA1RDA1, NON_SECURE, NO_OVERRIDE, ENABLE), 257 mc_make_sec_cfg(PVA1RDB1, NON_SECURE, NO_OVERRIDE, ENABLE), 258 mc_make_sec_cfg(PCIE5R1, NON_SECURE, OVERRIDE, ENABLE), 259 mc_make_sec_cfg(NVENCSRD1, NON_SECURE, NO_OVERRIDE, ENABLE), 260 mc_make_sec_cfg(NVENC1SRD1, NON_SECURE, NO_OVERRIDE, ENABLE), 261 mc_make_sec_cfg(ISPRA1, NON_SECURE, NO_OVERRIDE, ENABLE), 262 mc_make_sec_cfg(MIU0R, NON_SECURE, OVERRIDE, ENABLE), 263 mc_make_sec_cfg(MIU0W, NON_SECURE, OVERRIDE, ENABLE), 264 mc_make_sec_cfg(MIU1R, NON_SECURE, OVERRIDE, ENABLE), 265 mc_make_sec_cfg(MIU1W, NON_SECURE, OVERRIDE, ENABLE), 266 mc_make_sec_cfg(MIU2R, NON_SECURE, OVERRIDE, ENABLE), 267 mc_make_sec_cfg(MIU2W, NON_SECURE, OVERRIDE, ENABLE), 268 mc_make_sec_cfg(MIU3R, NON_SECURE, OVERRIDE, ENABLE), 269 mc_make_sec_cfg(MIU3W, NON_SECURE, OVERRIDE, ENABLE), 270 }; 271 272 /* To be called by common memctrl_v2.c */ 273 static void tegra194_memctrl_reconfig_mss_clients(void) 274 { 275 uint32_t reg_val, wdata_0, wdata_1, wdata_2; 276 277 wdata_0 = MC_CLIENT_HOTRESET_CTRL0_HC_FLUSH_ENB | 278 MC_CLIENT_HOTRESET_CTRL0_SATA_FLUSH_ENB | 279 MC_CLIENT_HOTRESET_CTRL0_VIC_FLUSH_ENB | 280 MC_CLIENT_HOTRESET_CTRL0_XUSB_HOST_FLUSH_ENB | 281 MC_CLIENT_HOTRESET_CTRL0_XUSB_DEV_FLUSH_ENB | 282 MC_CLIENT_HOTRESET_CTRL0_TSEC_FLUSH_ENB | 283 MC_CLIENT_HOTRESET_CTRL0_SDMMC3A_FLUSH_ENB; 284 if (tegra_platform_is_silicon()) { 285 wdata_0 |= MC_CLIENT_HOTRESET_CTRL0_SDMMC1A_FLUSH_ENB; 286 } 287 288 tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL0, wdata_0); 289 290 /* Wait for HOTRESET STATUS to indicate FLUSH_DONE */ 291 do { 292 reg_val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS0); 293 } while ((reg_val & wdata_0) != wdata_0); 294 295 wdata_1 = MC_CLIENT_HOTRESET_CTRL1_SDMMC4A_FLUSH_ENB | 296 MC_CLIENT_HOTRESET_CTRL1_SE_FLUSH_ENB | 297 MC_CLIENT_HOTRESET_CTRL1_ETR_FLUSH_ENB | 298 MC_CLIENT_HOTRESET_CTRL1_TSECB_FLUSH_ENB| 299 MC_CLIENT_HOTRESET_CTRL1_AXIS_FLUSH_ENB | 300 MC_CLIENT_HOTRESET_CTRL1_UFSHC_FLUSH_ENB | 301 MC_CLIENT_HOTRESET_CTRL1_NVDISPLAY_FLUSH_ENB | 302 MC_CLIENT_HOTRESET_CTRL1_BPMP_FLUSH_ENB | 303 MC_CLIENT_HOTRESET_CTRL1_AON_FLUSH_ENB | 304 MC_CLIENT_HOTRESET_CTRL1_SCE_FLUSH_ENB | 305 MC_CLIENT_HOTRESET_CTRL1_VIFAL_FLUSH_ENB; 306 if (tegra_platform_is_silicon()) { 307 wdata_1 |= MC_CLIENT_HOTRESET_CTRL1_APE_FLUSH_ENB | 308 MC_CLIENT_HOTRESET_CTRL1_EQOS_FLUSH_ENB | 309 MC_CLIENT_HOTRESET_CTRL1_RCE_FLUSH_ENB; 310 } 311 tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL1, wdata_1); 312 /* Wait for HOTRESET STATUS to indicate FLUSH_DONE */ 313 do { 314 reg_val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS1); 315 } while ((reg_val & wdata_1) != wdata_1); 316 317 wdata_2 = MC_CLIENT_HOTRESET_CTRL2_PCIE_FLUSH_ENB | 318 MC_CLIENT_HOTRESET_CTRL2_AONDMA_FLUSH_ENB | 319 MC_CLIENT_HOTRESET_CTRL2_BPMPDMA_FLUSH_ENB | 320 MC_CLIENT_HOTRESET_CTRL2_SCEDMA_FLUSH_ENB; 321 if (tegra_platform_is_silicon()) { 322 wdata_2 |= MC_CLIENT_HOTRESET_CTRL2_RCEDMA_FLUSH_ENB | 323 MC_CLIENT_HOTRESET_CTRL2_PCIE_FLUSH_ENB | 324 MC_CLIENT_HOTRESET_CTRL2_PCIE5A_FLUSH_ENB | 325 MC_CLIENT_HOTRESET_CTRL2_PCIE3A_FLUSH_ENB | 326 MC_CLIENT_HOTRESET_CTRL2_PCIE3_FLUSH_ENB | 327 MC_CLIENT_HOTRESET_CTRL2_PCIE0A_FLUSH_ENB | 328 MC_CLIENT_HOTRESET_CTRL2_PCIE0A2_FLUSH_ENB | 329 MC_CLIENT_HOTRESET_CTRL2_PCIE4A_FLUSH_ENB; 330 } 331 tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL2, wdata_2); 332 /* Wait for HOTRESET STATUS to indicate FLUSH_DONE */ 333 do { 334 reg_val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS2); 335 } while ((reg_val & wdata_2) != wdata_2); 336 337 /* 338 * Change MEMTYPE_OVERRIDE from SO_DEV -> PASSTHRU for boot and 339 * strongly ordered MSS clients. 340 * 341 * MC clients with default SO_DEV override still enabled at TSA: 342 * EQOSW, SATAW, XUSB_DEVW, XUSB_HOSTW, PCIe0w, PCIe1w, PCIe2w, 343 * PCIe3w, PCIe4w and PCIe5w. 344 */ 345 mc_set_tsa_w_passthrough(AONDMAW); 346 mc_set_tsa_w_passthrough(AONW); 347 mc_set_tsa_w_passthrough(APEDMAW); 348 mc_set_tsa_w_passthrough(APEW); 349 mc_set_tsa_w_passthrough(AXISW); 350 mc_set_tsa_w_passthrough(BPMPDMAW); 351 mc_set_tsa_w_passthrough(BPMPW); 352 mc_set_tsa_w_passthrough(EQOSW); 353 mc_set_tsa_w_passthrough(ETRW); 354 mc_set_tsa_w_passthrough(RCEDMAW); 355 mc_set_tsa_w_passthrough(RCEW); 356 mc_set_tsa_w_passthrough(SCEDMAW); 357 mc_set_tsa_w_passthrough(SCEW); 358 mc_set_tsa_w_passthrough(SDMMCW); 359 mc_set_tsa_w_passthrough(SDMMCWA); 360 mc_set_tsa_w_passthrough(SDMMCWAB); 361 mc_set_tsa_w_passthrough(SESWR); 362 mc_set_tsa_w_passthrough(TSECSWR); 363 mc_set_tsa_w_passthrough(TSECSWRB); 364 mc_set_tsa_w_passthrough(UFSHCW); 365 mc_set_tsa_w_passthrough(VICSWR); 366 mc_set_tsa_w_passthrough(VIFALW); 367 /* 368 * set HUB2 as SO_DEV_HUBID 369 */ 370 reg_val = tsa_read_32(PCIE0W); 371 mc_set_tsa_hub2(reg_val, PCIE0W); 372 reg_val = tsa_read_32(PCIE1W); 373 mc_set_tsa_hub2(reg_val, PCIE1W); 374 reg_val = tsa_read_32(PCIE2AW); 375 mc_set_tsa_hub2(reg_val, PCIE2AW); 376 reg_val = tsa_read_32(PCIE3W); 377 mc_set_tsa_hub2(reg_val, PCIE3W); 378 reg_val = tsa_read_32(PCIE4W); 379 mc_set_tsa_hub2(reg_val, PCIE4W); 380 reg_val = tsa_read_32(SATAW); 381 mc_set_tsa_hub2(reg_val, SATAW); 382 reg_val = tsa_read_32(XUSB_DEVW); 383 mc_set_tsa_hub2(reg_val, XUSB_DEVW); 384 reg_val = tsa_read_32(XUSB_HOSTW); 385 mc_set_tsa_hub2(reg_val, XUSB_HOSTW); 386 387 /* Ordered MC Clients on Xavier are EQOS, SATA, XUSB, PCIe1 and PCIe3 388 * ISO clients(DISP, VI, EQOS) should never snoop caches and 389 * don't need ROC/PCFIFO ordering. 390 * ISO clients(EQOS) that need ordering should use PCFIFO ordering 391 * and bypass ROC ordering by using FORCE_NON_COHERENT path. 392 * FORCE_NON_COHERENT/FORCE_COHERENT config take precedence 393 * over SMMU attributes. 394 * Force all Normal memory transactions from ISO and non-ISO to be 395 * non-coherent(bypass ROC, avoid cache snoop to avoid perf hit). 396 * Force the SO_DEV transactions from ordered ISO clients(EQOS) to 397 * non-coherent path and enable MC PCFIFO interlock for ordering. 398 * Force the SO_DEV transactions from ordered non-ISO clients (PCIe, 399 * XUSB, SATA) to coherent so that the transactions are 400 * ordered by ROC. 401 * PCFIFO ensure write ordering. 402 * Read after Write ordering is maintained/enforced by MC clients. 403 * Clients that need PCIe type write ordering must 404 * go through ROC ordering. 405 * Ordering enable for Read clients is not necessary. 406 * R5's and A9 would get necessary ordering from AXI and 407 * don't need ROC ordering enable: 408 * - MMIO ordering is through dev mapping and MMIO 409 * accesses bypass SMMU. 410 * - Normal memory is accessed through SMMU and ordering is 411 * ensured by client and AXI. 412 * - Ack point for Normal memory is WCAM in MC. 413 * - MMIO's can be early acked and AXI ensures dev memory ordering, 414 * Client ensures read/write direction change ordering. 415 * - See Bug 200312466 for more details. 416 */ 417 mc_set_txn_override(AONDMAR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 418 mc_set_txn_override(AONDMAW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 419 mc_set_txn_override(AONR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 420 mc_set_txn_override(AONW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 421 mc_set_txn_override(APEDMAR, CGID_TAG_ADR, SO_DEV_CLIENT_AXI_ID, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 422 mc_set_txn_override(APEDMAW, CGID_TAG_ADR, SO_DEV_CLIENT_AXI_ID, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 423 mc_set_txn_override(APER, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 424 mc_set_txn_override(APEW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 425 mc_set_txn_override(AXISR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 426 mc_set_txn_override(AXISW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 427 mc_set_txn_override(BPMPDMAR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 428 mc_set_txn_override(BPMPDMAW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 429 mc_set_txn_override(BPMPR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 430 mc_set_txn_override(BPMPW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 431 mc_set_txn_override(EQOSR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 432 mc_set_txn_override(EQOSW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 433 mc_set_txn_override(ETRR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 434 mc_set_txn_override(ETRW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 435 mc_set_txn_override(HOST1XDMAR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 436 mc_set_txn_override(NVDISPLAYR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 437 mc_set_txn_override(NVDISPLAYR1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 438 mc_set_txn_override(PCIE0R, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); 439 mc_set_txn_override(PCIE0R1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); 440 mc_set_txn_override(PCIE0W, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); 441 mc_set_txn_override(PCIE1R, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); 442 mc_set_txn_override(PCIE1W, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); 443 if (tegra_platform_is_silicon()) { 444 mc_set_txn_override(PCIE2AR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); 445 mc_set_txn_override(PCIE2AW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); 446 mc_set_txn_override(PCIE3R, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); 447 mc_set_txn_override(PCIE3W, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); 448 mc_set_txn_override(PCIE4R, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); 449 mc_set_txn_override(PCIE4W, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); 450 mc_set_txn_override(PCIE5R, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); 451 mc_set_txn_override(PCIE5W, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); 452 mc_set_txn_override(PCIE5R1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); 453 } 454 mc_set_txn_override(RCEDMAR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 455 mc_set_txn_override(RCEDMAW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 456 mc_set_txn_override(RCER, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 457 mc_set_txn_override(RCEW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 458 mc_set_txn_override(SATAR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); 459 mc_set_txn_override(SATAW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); 460 mc_set_txn_override(SCEDMAR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 461 mc_set_txn_override(SCEDMAW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 462 mc_set_txn_override(SCER, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 463 mc_set_txn_override(SCEW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 464 mc_set_txn_override(SDMMCR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 465 mc_set_txn_override(SDMMCRAB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 466 mc_set_txn_override(SDMMCRA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 467 mc_set_txn_override(SDMMCW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 468 mc_set_txn_override(SDMMCWA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 469 mc_set_txn_override(SDMMCWAB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 470 /* 471 * TO DO: make SESRD/WR FORCE_COHERENT once SE+TZ with SMMU is enabled. 472 */ 473 mc_set_txn_override(SESRD, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); 474 mc_set_txn_override(SESWR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); 475 mc_set_txn_override(TSECSRD, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 476 mc_set_txn_override(TSECSRDB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 477 mc_set_txn_override(TSECSWR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 478 mc_set_txn_override(TSECSWRB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 479 mc_set_txn_override(UFSHCR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 480 mc_set_txn_override(UFSHCW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 481 mc_set_txn_override(VICSRD, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 482 mc_set_txn_override(VICSRD1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 483 mc_set_txn_override(VICSWR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 484 mc_set_txn_override(VIFALR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 485 mc_set_txn_override(VIFALW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 486 mc_set_txn_override(XUSB_DEVR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); 487 mc_set_txn_override(XUSB_DEVW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); 488 mc_set_txn_override(XUSB_HOSTR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); 489 mc_set_txn_override(XUSB_HOSTW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); 490 mc_set_txn_override(AXIAPR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 491 mc_set_txn_override(AXIAPW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 492 mc_set_txn_override(DLA0FALRDB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 493 mc_set_txn_override(DLA0FALWRB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 494 mc_set_txn_override(DLA0RDA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 495 mc_set_txn_override(DLA0RDA1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 496 mc_set_txn_override(DLA0WRA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 497 mc_set_txn_override(DLA1FALRDB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 498 mc_set_txn_override(DLA1FALWRB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 499 mc_set_txn_override(DLA1RDA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 500 mc_set_txn_override(DLA1RDA1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 501 mc_set_txn_override(DLA1WRA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 502 mc_set_txn_override(HDAR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 503 mc_set_txn_override(HDAW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 504 mc_set_txn_override(ISPFALR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 505 mc_set_txn_override(ISPFALW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 506 mc_set_txn_override(ISPRA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 507 mc_set_txn_override(ISPRA1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 508 mc_set_txn_override(ISPWA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 509 mc_set_txn_override(ISPWB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 510 mc_set_txn_override(NVDEC1SRD, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 511 mc_set_txn_override(NVDEC1SRD1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 512 mc_set_txn_override(NVDEC1SWR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 513 mc_set_txn_override(NVDECSRD, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 514 mc_set_txn_override(NVDECSRD1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 515 mc_set_txn_override(NVDECSWR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 516 mc_set_txn_override(NVENC1SRD, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 517 mc_set_txn_override(NVENC1SRD1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 518 mc_set_txn_override(NVENC1SWR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 519 mc_set_txn_override(NVENCSRD, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 520 mc_set_txn_override(NVENCSRD1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 521 mc_set_txn_override(NVENCSWR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 522 mc_set_txn_override(NVJPGSRD, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 523 mc_set_txn_override(NVJPGSWR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 524 mc_set_txn_override(PVA0RDA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 525 mc_set_txn_override(PVA0RDA1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 526 mc_set_txn_override(PVA0RDB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 527 mc_set_txn_override(PVA0RDB1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 528 mc_set_txn_override(PVA0RDC, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 529 mc_set_txn_override(PVA0WRA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 530 mc_set_txn_override(PVA0WRB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 531 mc_set_txn_override(PVA0WRC, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 532 mc_set_txn_override(PVA1RDA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 533 mc_set_txn_override(PVA1RDA1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 534 mc_set_txn_override(PVA1RDB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 535 mc_set_txn_override(PVA1RDB1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 536 mc_set_txn_override(PVA1RDC, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 537 mc_set_txn_override(PVA1WRA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 538 mc_set_txn_override(PVA1WRB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 539 mc_set_txn_override(PVA1WRC, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 540 mc_set_txn_override(VIW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 541 542 /* 543 * At this point, ordering can occur at SCF. So, remove PCFIFO's 544 * control over ordering requests. 545 * 546 * Change PCFIFO_*_ORDERED_CLIENT from ORDERED -> UNORDERED for 547 * boot and strongly ordered MSS clients 548 */ 549 reg_val = MC_PCFIFO_CLIENT_CONFIG2_RESET_VAL & 550 mc_set_pcfifo_unordered_boot_so_mss(2, XUSB_HOSTW) & 551 mc_set_pcfifo_unordered_boot_so_mss(2, TSECSWR); 552 tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG2, reg_val); 553 554 reg_val = MC_PCFIFO_CLIENT_CONFIG3_RESET_VAL & 555 mc_set_pcfifo_unordered_boot_so_mss(3, SDMMCWA) & 556 mc_set_pcfifo_unordered_boot_so_mss(3, SDMMCW) & 557 mc_set_pcfifo_unordered_boot_so_mss(3, SDMMCWAB) & 558 mc_set_pcfifo_unordered_boot_so_mss(3, VICSWR) & 559 mc_set_pcfifo_unordered_boot_so_mss(3, APEW); 560 tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG3, reg_val); 561 562 reg_val = MC_PCFIFO_CLIENT_CONFIG4_RESET_VAL & 563 mc_set_pcfifo_unordered_boot_so_mss(4, SESWR) & 564 mc_set_pcfifo_unordered_boot_so_mss(4, ETRW) & 565 mc_set_pcfifo_unordered_boot_so_mss(4, TSECSWRB) & 566 mc_set_pcfifo_unordered_boot_so_mss(4, AXISW) & 567 mc_set_pcfifo_unordered_boot_so_mss(4, UFSHCW) & 568 mc_set_pcfifo_unordered_boot_so_mss(4, BPMPW) & 569 mc_set_pcfifo_unordered_boot_so_mss(4, BPMPDMAW) & 570 mc_set_pcfifo_unordered_boot_so_mss(4, AONW) & 571 mc_set_pcfifo_unordered_boot_so_mss(4, AONDMAW) & 572 mc_set_pcfifo_unordered_boot_so_mss(4, SCEW) & 573 mc_set_pcfifo_unordered_boot_so_mss(4, SCEDMAW); 574 /* EQOSW has PCFIFO order enabled. */ 575 reg_val |= mc_set_pcfifo_unordered_boot_so_mss(4, EQOSW); 576 tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG4, reg_val); 577 578 reg_val = MC_PCFIFO_CLIENT_CONFIG5_RESET_VAL & 579 mc_set_pcfifo_unordered_boot_so_mss(5, APEDMAW) & 580 mc_set_pcfifo_unordered_boot_so_mss(5, VIFALW); 581 tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG5, reg_val); 582 583 reg_val = MC_PCFIFO_CLIENT_CONFIG6_RESET_VAL & 584 mc_set_pcfifo_unordered_boot_so_mss(6, RCEW) & 585 mc_set_pcfifo_unordered_boot_so_mss(6, RCEDMAW) & 586 mc_set_pcfifo_unordered_boot_so_mss(6, PCIE0W); 587 tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG6, reg_val); 588 589 reg_val = MC_PCFIFO_CLIENT_CONFIG7_RESET_VAL & 590 mc_set_pcfifo_unordered_boot_so_mss(7, PCIE4W) & 591 mc_set_pcfifo_unordered_boot_so_mss(7, PCIE5W); 592 tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG7, reg_val); 593 594 /* Set Order Id only for the clients having non zero order id */ 595 reg_val = mc_client_order_id(MC_CLIENT_ORDER_ID_9_RESET_VAL, 9, XUSB_HOSTW); 596 tegra_mc_write_32(MC_CLIENT_ORDER_ID_9, reg_val); 597 598 reg_val = mc_client_order_id(MC_CLIENT_ORDER_ID_27_RESET_VAL, 27, PCIE0W); 599 tegra_mc_write_32(MC_CLIENT_ORDER_ID_27, reg_val); 600 601 reg_val = mc_client_order_id(MC_CLIENT_ORDER_ID_28_RESET_VAL, 28, PCIE4W); 602 reg_val = mc_client_order_id(reg_val, 28, PCIE5W); 603 tegra_mc_write_32(MC_CLIENT_ORDER_ID_28, reg_val); 604 605 /* 606 * Set VC Id only for the clients having different reset values like 607 * SDMMCRAB, SDMMCWAB, SESRD, SESWR, TSECSRD,TSECSRDB, TSECSWR and 608 * TSECSWRB clients 609 */ 610 reg_val = mc_hub_vc_id(MC_HUB_PC_VC_ID_0_RESET_VAL, 0, APB); 611 tegra_mc_write_32(MC_HUB_PC_VC_ID_0, reg_val); 612 613 /* SDMMCRAB and SDMMCWAB clients */ 614 reg_val = mc_hub_vc_id(MC_HUB_PC_VC_ID_2_RESET_VAL, 2, SD); 615 tegra_mc_write_32(MC_HUB_PC_VC_ID_2, reg_val); 616 617 reg_val = mc_hub_vc_id(MC_HUB_PC_VC_ID_4_RESET_VAL, 4, NIC); 618 tegra_mc_write_32(MC_HUB_PC_VC_ID_4, reg_val); 619 620 reg_val = mc_hub_vc_id(MC_HUB_PC_VC_ID_12_RESET_VAL, 12, UFSHCPC2); 621 tegra_mc_write_32(MC_HUB_PC_VC_ID_12, reg_val); 622 623 wdata_0 = MC_CLIENT_HOTRESET_CTRL0_RESET_VAL; 624 tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL0, wdata_0); 625 626 wdata_1 = MC_CLIENT_HOTRESET_CTRL1_RESET_VAL; 627 tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL1, wdata_1); 628 629 wdata_2 = MC_CLIENT_HOTRESET_CTRL2_RESET_VAL; 630 tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL2, wdata_2); 631 632 reg_val = MC_COALESCE_CTRL_COALESCER_ENABLE; 633 tegra_mc_write_32(MC_COALESCE_CTRL, reg_val); 634 635 /* 636 * WAR to hardware bug 1953865: Coalescer must be disabled 637 * for PVA0RDC and PVA1RDC interfaces. 638 */ 639 reg_val = tegra_mc_read_32(MC_COALESCE_CONFIG_6_0); 640 reg_val &= ~(MC_COALESCE_CONFIG_6_0_PVA0RDC_COALESCER_ENABLED | 641 MC_COALESCE_CONFIG_6_0_PVA1RDC_COALESCER_ENABLED); 642 tegra_mc_write_32(MC_COALESCE_CONFIG_6_0, reg_val); 643 } 644 645 /******************************************************************************* 646 * Struct to hold the memory controller settings 647 ******************************************************************************/ 648 static tegra_mc_settings_t tegra194_mc_settings = { 649 .streamid_override_cfg = tegra194_streamid_override_regs, 650 .num_streamid_override_cfgs = (uint32_t)ARRAY_SIZE(tegra194_streamid_override_regs), 651 .streamid_security_cfg = tegra194_streamid_sec_cfgs, 652 .num_streamid_security_cfgs = (uint32_t)ARRAY_SIZE(tegra194_streamid_sec_cfgs), 653 .reconfig_mss_clients = tegra194_memctrl_reconfig_mss_clients 654 }; 655 656 /******************************************************************************* 657 * Handler to return the pointer to the memory controller's settings struct 658 ******************************************************************************/ 659 tegra_mc_settings_t *tegra_get_mc_settings(void) 660 { 661 return &tegra194_mc_settings; 662 } 663 664 /******************************************************************************* 665 * Handler to program the scratch registers with TZDRAM settings for the 666 * resume firmware 667 ******************************************************************************/ 668 void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes) 669 { 670 uint32_t sec_reg_ctrl = tegra_mc_read_32(MC_SECURITY_CFG_REG_CTRL_0); 671 672 /* 673 * Check TZDRAM carveout register access status. Setup TZDRAM fence 674 * only if access is enabled. 675 */ 676 if ((sec_reg_ctrl & SECURITY_CFG_WRITE_ACCESS_BIT) == 677 SECURITY_CFG_WRITE_ACCESS_ENABLE) { 678 679 /* 680 * Setup the Memory controller to allow only secure accesses to 681 * the TZDRAM carveout 682 */ 683 INFO("Configuring TrustZone DRAM Memory Carveout\n"); 684 685 tegra_mc_write_32(MC_SECURITY_CFG0_0, (uint32_t)phys_base); 686 tegra_mc_write_32(MC_SECURITY_CFG3_0, (uint32_t)(phys_base >> 32)); 687 tegra_mc_write_32(MC_SECURITY_CFG1_0, (uint32_t)(size_in_bytes >> 20)); 688 689 /* 690 * MCE propagates the security configuration values across the 691 * CCPLEX. 692 */ 693 (void)mce_update_gsc_tzdram(); 694 } 695 } 696