1 /* 2 * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <common/bl_common.h> 9 #include <mce.h> 10 #include <memctrl_v2.h> 11 #include <tegra_mc_def.h> 12 #include <tegra_platform.h> 13 14 /******************************************************************************* 15 * Array to hold stream_id override config register offsets 16 ******************************************************************************/ 17 const static uint32_t tegra194_streamid_override_regs[] = { 18 MC_STREAMID_OVERRIDE_CFG_PTCR, 19 MC_STREAMID_OVERRIDE_CFG_HDAR, 20 MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR, 21 MC_STREAMID_OVERRIDE_CFG_NVENCSRD, 22 MC_STREAMID_OVERRIDE_CFG_SATAR, 23 MC_STREAMID_OVERRIDE_CFG_MPCORER, 24 MC_STREAMID_OVERRIDE_CFG_NVENCSWR, 25 MC_STREAMID_OVERRIDE_CFG_HDAW, 26 MC_STREAMID_OVERRIDE_CFG_MPCOREW, 27 MC_STREAMID_OVERRIDE_CFG_SATAW, 28 MC_STREAMID_OVERRIDE_CFG_ISPRA, 29 MC_STREAMID_OVERRIDE_CFG_ISPFALR, 30 MC_STREAMID_OVERRIDE_CFG_ISPWA, 31 MC_STREAMID_OVERRIDE_CFG_ISPWB, 32 MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR, 33 MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW, 34 MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR, 35 MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW, 36 MC_STREAMID_OVERRIDE_CFG_TSECSRD, 37 MC_STREAMID_OVERRIDE_CFG_TSECSWR, 38 MC_STREAMID_OVERRIDE_CFG_SDMMCRA, 39 MC_STREAMID_OVERRIDE_CFG_SDMMCR, 40 MC_STREAMID_OVERRIDE_CFG_SDMMCRAB, 41 MC_STREAMID_OVERRIDE_CFG_SDMMCWA, 42 MC_STREAMID_OVERRIDE_CFG_SDMMCW, 43 MC_STREAMID_OVERRIDE_CFG_SDMMCWAB, 44 MC_STREAMID_OVERRIDE_CFG_VICSRD, 45 MC_STREAMID_OVERRIDE_CFG_VICSWR, 46 MC_STREAMID_OVERRIDE_CFG_VIW, 47 MC_STREAMID_OVERRIDE_CFG_NVDECSRD, 48 MC_STREAMID_OVERRIDE_CFG_NVDECSWR, 49 MC_STREAMID_OVERRIDE_CFG_APER, 50 MC_STREAMID_OVERRIDE_CFG_APEW, 51 MC_STREAMID_OVERRIDE_CFG_NVJPGSRD, 52 MC_STREAMID_OVERRIDE_CFG_NVJPGSWR, 53 MC_STREAMID_OVERRIDE_CFG_SESRD, 54 MC_STREAMID_OVERRIDE_CFG_SESWR, 55 MC_STREAMID_OVERRIDE_CFG_AXIAPR, 56 MC_STREAMID_OVERRIDE_CFG_AXIAPW, 57 MC_STREAMID_OVERRIDE_CFG_ETRR, 58 MC_STREAMID_OVERRIDE_CFG_ETRW, 59 MC_STREAMID_OVERRIDE_CFG_TSECSRDB, 60 MC_STREAMID_OVERRIDE_CFG_TSECSWRB, 61 MC_STREAMID_OVERRIDE_CFG_AXISR, 62 MC_STREAMID_OVERRIDE_CFG_AXISW, 63 MC_STREAMID_OVERRIDE_CFG_EQOSR, 64 MC_STREAMID_OVERRIDE_CFG_EQOSW, 65 MC_STREAMID_OVERRIDE_CFG_UFSHCR, 66 MC_STREAMID_OVERRIDE_CFG_UFSHCW, 67 MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR, 68 MC_STREAMID_OVERRIDE_CFG_BPMPR, 69 MC_STREAMID_OVERRIDE_CFG_BPMPW, 70 MC_STREAMID_OVERRIDE_CFG_BPMPDMAR, 71 MC_STREAMID_OVERRIDE_CFG_BPMPDMAW, 72 MC_STREAMID_OVERRIDE_CFG_AONR, 73 MC_STREAMID_OVERRIDE_CFG_AONW, 74 MC_STREAMID_OVERRIDE_CFG_AONDMAR, 75 MC_STREAMID_OVERRIDE_CFG_AONDMAW, 76 MC_STREAMID_OVERRIDE_CFG_SCER, 77 MC_STREAMID_OVERRIDE_CFG_SCEW, 78 MC_STREAMID_OVERRIDE_CFG_SCEDMAR, 79 MC_STREAMID_OVERRIDE_CFG_SCEDMAW, 80 MC_STREAMID_OVERRIDE_CFG_APEDMAR, 81 MC_STREAMID_OVERRIDE_CFG_APEDMAW, 82 MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1, 83 MC_STREAMID_OVERRIDE_CFG_VICSRD1, 84 MC_STREAMID_OVERRIDE_CFG_NVDECSRD1, 85 MC_STREAMID_OVERRIDE_CFG_VIFALR, 86 MC_STREAMID_OVERRIDE_CFG_VIFALW, 87 MC_STREAMID_OVERRIDE_CFG_DLA0RDA, 88 MC_STREAMID_OVERRIDE_CFG_DLA0FALRDB, 89 MC_STREAMID_OVERRIDE_CFG_DLA0WRA, 90 MC_STREAMID_OVERRIDE_CFG_DLA0FALWRB, 91 MC_STREAMID_OVERRIDE_CFG_DLA1RDA, 92 MC_STREAMID_OVERRIDE_CFG_DLA1FALRDB, 93 MC_STREAMID_OVERRIDE_CFG_DLA1WRA, 94 MC_STREAMID_OVERRIDE_CFG_DLA1FALWRB, 95 MC_STREAMID_OVERRIDE_CFG_PVA0RDA, 96 MC_STREAMID_OVERRIDE_CFG_PVA0RDB, 97 MC_STREAMID_OVERRIDE_CFG_PVA0RDC, 98 MC_STREAMID_OVERRIDE_CFG_PVA0WRA, 99 MC_STREAMID_OVERRIDE_CFG_PVA0WRB, 100 MC_STREAMID_OVERRIDE_CFG_PVA0WRC, 101 MC_STREAMID_OVERRIDE_CFG_PVA1RDA, 102 MC_STREAMID_OVERRIDE_CFG_PVA1RDB, 103 MC_STREAMID_OVERRIDE_CFG_PVA1RDC, 104 MC_STREAMID_OVERRIDE_CFG_PVA1WRA, 105 MC_STREAMID_OVERRIDE_CFG_PVA1WRB, 106 MC_STREAMID_OVERRIDE_CFG_PVA1WRC, 107 MC_STREAMID_OVERRIDE_CFG_RCER, 108 MC_STREAMID_OVERRIDE_CFG_RCEW, 109 MC_STREAMID_OVERRIDE_CFG_RCEDMAR, 110 MC_STREAMID_OVERRIDE_CFG_RCEDMAW, 111 MC_STREAMID_OVERRIDE_CFG_NVENC1SRD, 112 MC_STREAMID_OVERRIDE_CFG_NVENC1SWR, 113 MC_STREAMID_OVERRIDE_CFG_PCIE0R, 114 MC_STREAMID_OVERRIDE_CFG_PCIE0W, 115 MC_STREAMID_OVERRIDE_CFG_PCIE1R, 116 MC_STREAMID_OVERRIDE_CFG_PCIE1W, 117 MC_STREAMID_OVERRIDE_CFG_PCIE2AR, 118 MC_STREAMID_OVERRIDE_CFG_PCIE2AW, 119 MC_STREAMID_OVERRIDE_CFG_PCIE3R, 120 MC_STREAMID_OVERRIDE_CFG_PCIE3W, 121 MC_STREAMID_OVERRIDE_CFG_PCIE4R, 122 MC_STREAMID_OVERRIDE_CFG_PCIE4W, 123 MC_STREAMID_OVERRIDE_CFG_PCIE5R, 124 MC_STREAMID_OVERRIDE_CFG_PCIE5W, 125 MC_STREAMID_OVERRIDE_CFG_ISPFALW, 126 MC_STREAMID_OVERRIDE_CFG_DLA0RDA1, 127 MC_STREAMID_OVERRIDE_CFG_DLA1RDA1, 128 MC_STREAMID_OVERRIDE_CFG_PVA0RDA1, 129 MC_STREAMID_OVERRIDE_CFG_PVA0RDB1, 130 MC_STREAMID_OVERRIDE_CFG_PVA1RDA1, 131 MC_STREAMID_OVERRIDE_CFG_PVA1RDB1, 132 MC_STREAMID_OVERRIDE_CFG_PCIE5R1, 133 MC_STREAMID_OVERRIDE_CFG_NVENCSRD1, 134 MC_STREAMID_OVERRIDE_CFG_NVENC1SRD1, 135 MC_STREAMID_OVERRIDE_CFG_ISPRA1, 136 MC_STREAMID_OVERRIDE_CFG_PCIE0R1, 137 MC_STREAMID_OVERRIDE_CFG_NVDEC1SRD, 138 MC_STREAMID_OVERRIDE_CFG_NVDEC1SRD1, 139 MC_STREAMID_OVERRIDE_CFG_NVDEC1SWR, 140 MC_STREAMID_OVERRIDE_CFG_MIU0R, 141 MC_STREAMID_OVERRIDE_CFG_MIU0W, 142 MC_STREAMID_OVERRIDE_CFG_MIU1R, 143 MC_STREAMID_OVERRIDE_CFG_MIU1W, 144 MC_STREAMID_OVERRIDE_CFG_MIU2R, 145 MC_STREAMID_OVERRIDE_CFG_MIU2W, 146 MC_STREAMID_OVERRIDE_CFG_MIU3R, 147 MC_STREAMID_OVERRIDE_CFG_MIU3W, 148 MC_STREAMID_OVERRIDE_CFG_MIU4R, 149 MC_STREAMID_OVERRIDE_CFG_MIU4W, 150 MC_STREAMID_OVERRIDE_CFG_MIU5R, 151 MC_STREAMID_OVERRIDE_CFG_MIU5W, 152 MC_STREAMID_OVERRIDE_CFG_MIU6R, 153 MC_STREAMID_OVERRIDE_CFG_MIU6W, 154 MC_STREAMID_OVERRIDE_CFG_MIU7R, 155 MC_STREAMID_OVERRIDE_CFG_MIU7W 156 }; 157 158 /******************************************************************************* 159 * Array to hold the security configs for stream IDs 160 ******************************************************************************/ 161 const static mc_streamid_security_cfg_t tegra194_streamid_sec_cfgs[] = { 162 mc_make_sec_cfg(PTCR, NON_SECURE, OVERRIDE, DISABLE), 163 mc_make_sec_cfg(HDAR, NON_SECURE, OVERRIDE, DISABLE), 164 mc_make_sec_cfg(HOST1XDMAR, NON_SECURE, NO_OVERRIDE, DISABLE), 165 mc_make_sec_cfg(NVENCSRD, NON_SECURE, NO_OVERRIDE, DISABLE), 166 mc_make_sec_cfg(SATAR, NON_SECURE, OVERRIDE, DISABLE), 167 mc_make_sec_cfg(MPCORER, NON_SECURE, OVERRIDE, DISABLE), 168 mc_make_sec_cfg(NVENCSWR, NON_SECURE, NO_OVERRIDE, DISABLE), 169 mc_make_sec_cfg(HDAW, NON_SECURE, OVERRIDE, DISABLE), 170 mc_make_sec_cfg(MPCOREW, NON_SECURE, OVERRIDE, DISABLE), 171 mc_make_sec_cfg(SATAW, NON_SECURE, OVERRIDE, DISABLE), 172 mc_make_sec_cfg(ISPRA, NON_SECURE, NO_OVERRIDE, ENABLE), 173 mc_make_sec_cfg(ISPFALR, NON_SECURE, NO_OVERRIDE, ENABLE), 174 mc_make_sec_cfg(ISPWA, NON_SECURE, NO_OVERRIDE, ENABLE), 175 mc_make_sec_cfg(ISPWB, NON_SECURE, NO_OVERRIDE, ENABLE), 176 mc_make_sec_cfg(XUSB_HOSTR, NON_SECURE, NO_OVERRIDE, ENABLE), 177 mc_make_sec_cfg(XUSB_HOSTW, NON_SECURE, NO_OVERRIDE, ENABLE), 178 mc_make_sec_cfg(XUSB_DEVR, NON_SECURE, NO_OVERRIDE, ENABLE), 179 mc_make_sec_cfg(XUSB_DEVW, NON_SECURE, NO_OVERRIDE, ENABLE), 180 mc_make_sec_cfg(TSECSRD, NON_SECURE, NO_OVERRIDE, DISABLE), 181 mc_make_sec_cfg(TSECSWR, NON_SECURE, NO_OVERRIDE, DISABLE), 182 mc_make_sec_cfg(SDMMCRA, NON_SECURE, OVERRIDE, DISABLE), 183 mc_make_sec_cfg(SDMMCR, NON_SECURE, OVERRIDE, DISABLE), 184 mc_make_sec_cfg(SDMMCRAB, NON_SECURE, OVERRIDE, DISABLE), 185 mc_make_sec_cfg(SDMMCWA, NON_SECURE, OVERRIDE, DISABLE), 186 mc_make_sec_cfg(SDMMCW, NON_SECURE, OVERRIDE, DISABLE), 187 mc_make_sec_cfg(SDMMCWAB, NON_SECURE, OVERRIDE, DISABLE), 188 mc_make_sec_cfg(VICSRD, NON_SECURE, NO_OVERRIDE, DISABLE), 189 mc_make_sec_cfg(VICSWR, NON_SECURE, NO_OVERRIDE, DISABLE), 190 mc_make_sec_cfg(VIW, NON_SECURE, NO_OVERRIDE, ENABLE), 191 mc_make_sec_cfg(NVDECSRD, NON_SECURE, NO_OVERRIDE, DISABLE), 192 mc_make_sec_cfg(NVDECSWR, NON_SECURE, NO_OVERRIDE, DISABLE), 193 mc_make_sec_cfg(APER, NON_SECURE, NO_OVERRIDE, DISABLE), 194 mc_make_sec_cfg(APEW, NON_SECURE, NO_OVERRIDE, DISABLE), 195 mc_make_sec_cfg(NVJPGSRD, NON_SECURE, NO_OVERRIDE, DISABLE), 196 mc_make_sec_cfg(NVJPGSWR, NON_SECURE, NO_OVERRIDE, DISABLE), 197 mc_make_sec_cfg(SESRD, NON_SECURE, NO_OVERRIDE, DISABLE), 198 mc_make_sec_cfg(SESWR, NON_SECURE, NO_OVERRIDE, DISABLE), 199 mc_make_sec_cfg(AXIAPR, NON_SECURE, OVERRIDE, DISABLE), 200 mc_make_sec_cfg(AXIAPW, NON_SECURE, OVERRIDE, DISABLE), 201 mc_make_sec_cfg(ETRR, NON_SECURE, OVERRIDE, DISABLE), 202 mc_make_sec_cfg(ETRW, NON_SECURE, OVERRIDE, DISABLE), 203 mc_make_sec_cfg(TSECSRDB, NON_SECURE, NO_OVERRIDE, DISABLE), 204 mc_make_sec_cfg(TSECSWRB, NON_SECURE, NO_OVERRIDE, DISABLE), 205 mc_make_sec_cfg(AXISR, SECURE, NO_OVERRIDE, DISABLE), 206 mc_make_sec_cfg(AXISW, SECURE, NO_OVERRIDE, DISABLE), 207 mc_make_sec_cfg(EQOSR, NON_SECURE, OVERRIDE, DISABLE), 208 mc_make_sec_cfg(EQOSW, NON_SECURE, OVERRIDE, DISABLE), 209 mc_make_sec_cfg(UFSHCR, NON_SECURE, OVERRIDE, DISABLE), 210 mc_make_sec_cfg(UFSHCW, NON_SECURE, OVERRIDE, DISABLE), 211 mc_make_sec_cfg(NVDISPLAYR, NON_SECURE, OVERRIDE, DISABLE), 212 mc_make_sec_cfg(BPMPR, NON_SECURE, NO_OVERRIDE, DISABLE), 213 mc_make_sec_cfg(BPMPW, NON_SECURE, NO_OVERRIDE, DISABLE), 214 mc_make_sec_cfg(BPMPDMAR, NON_SECURE, NO_OVERRIDE, DISABLE), 215 mc_make_sec_cfg(BPMPDMAW, NON_SECURE, NO_OVERRIDE, DISABLE), 216 mc_make_sec_cfg(AONR, NON_SECURE, NO_OVERRIDE, DISABLE), 217 mc_make_sec_cfg(AONW, NON_SECURE, NO_OVERRIDE, DISABLE), 218 mc_make_sec_cfg(AONDMAR, NON_SECURE, NO_OVERRIDE, DISABLE), 219 mc_make_sec_cfg(AONDMAW, NON_SECURE, NO_OVERRIDE, DISABLE), 220 mc_make_sec_cfg(SCER, NON_SECURE, NO_OVERRIDE, DISABLE), 221 mc_make_sec_cfg(SCEW, NON_SECURE, NO_OVERRIDE, DISABLE), 222 mc_make_sec_cfg(SCEDMAR, NON_SECURE, NO_OVERRIDE, DISABLE), 223 mc_make_sec_cfg(SCEDMAW, NON_SECURE, NO_OVERRIDE, DISABLE), 224 mc_make_sec_cfg(APEDMAR, NON_SECURE, NO_OVERRIDE, DISABLE), 225 mc_make_sec_cfg(APEDMAW, NON_SECURE, NO_OVERRIDE, DISABLE), 226 mc_make_sec_cfg(NVDISPLAYR1, NON_SECURE, OVERRIDE, DISABLE), 227 mc_make_sec_cfg(VICSRD1, NON_SECURE, NO_OVERRIDE, DISABLE), 228 mc_make_sec_cfg(NVDECSRD1, NON_SECURE, NO_OVERRIDE, DISABLE), 229 mc_make_sec_cfg(VIFALR, NON_SECURE, NO_OVERRIDE, ENABLE), 230 mc_make_sec_cfg(VIFALW, NON_SECURE, NO_OVERRIDE, ENABLE), 231 mc_make_sec_cfg(DLA0RDA, NON_SECURE, NO_OVERRIDE, DISABLE), 232 mc_make_sec_cfg(DLA0FALRDB, NON_SECURE, NO_OVERRIDE, DISABLE), 233 mc_make_sec_cfg(DLA0WRA, NON_SECURE, NO_OVERRIDE, DISABLE), 234 mc_make_sec_cfg(DLA0FALWRB, NON_SECURE, NO_OVERRIDE, DISABLE), 235 mc_make_sec_cfg(DLA1RDA, NON_SECURE, NO_OVERRIDE, DISABLE), 236 mc_make_sec_cfg(DLA1FALRDB, NON_SECURE, NO_OVERRIDE, DISABLE), 237 mc_make_sec_cfg(DLA1WRA, NON_SECURE, NO_OVERRIDE, DISABLE), 238 mc_make_sec_cfg(DLA1FALWRB, NON_SECURE, NO_OVERRIDE, DISABLE), 239 mc_make_sec_cfg(PVA0RDA, NON_SECURE, NO_OVERRIDE, DISABLE), 240 mc_make_sec_cfg(PVA0RDB, NON_SECURE, NO_OVERRIDE, DISABLE), 241 mc_make_sec_cfg(PVA0RDC, NON_SECURE, NO_OVERRIDE, DISABLE), 242 mc_make_sec_cfg(PVA0WRA, NON_SECURE, NO_OVERRIDE, DISABLE), 243 mc_make_sec_cfg(PVA0WRB, NON_SECURE, NO_OVERRIDE, DISABLE), 244 mc_make_sec_cfg(PVA0WRC, NON_SECURE, NO_OVERRIDE, DISABLE), 245 mc_make_sec_cfg(PVA1RDA, NON_SECURE, NO_OVERRIDE, DISABLE), 246 mc_make_sec_cfg(PVA1RDB, NON_SECURE, NO_OVERRIDE, DISABLE), 247 mc_make_sec_cfg(PVA1RDC, NON_SECURE, NO_OVERRIDE, DISABLE), 248 mc_make_sec_cfg(PVA1WRA, NON_SECURE, NO_OVERRIDE, DISABLE), 249 mc_make_sec_cfg(PVA1WRB, NON_SECURE, NO_OVERRIDE, DISABLE), 250 mc_make_sec_cfg(PVA1WRC, NON_SECURE, NO_OVERRIDE, DISABLE), 251 mc_make_sec_cfg(RCER, NON_SECURE, NO_OVERRIDE, DISABLE), 252 mc_make_sec_cfg(RCEW, NON_SECURE, NO_OVERRIDE, DISABLE), 253 mc_make_sec_cfg(RCEDMAR, NON_SECURE, NO_OVERRIDE, DISABLE), 254 mc_make_sec_cfg(RCEDMAW, NON_SECURE, NO_OVERRIDE, DISABLE), 255 mc_make_sec_cfg(NVENC1SRD, NON_SECURE, NO_OVERRIDE, DISABLE), 256 mc_make_sec_cfg(NVENC1SWR, NON_SECURE, NO_OVERRIDE, DISABLE), 257 mc_make_sec_cfg(PCIE0R, NON_SECURE, OVERRIDE, DISABLE), 258 mc_make_sec_cfg(PCIE0W, NON_SECURE, OVERRIDE, DISABLE), 259 mc_make_sec_cfg(PCIE1R, NON_SECURE, OVERRIDE, DISABLE), 260 mc_make_sec_cfg(PCIE1W, NON_SECURE, OVERRIDE, DISABLE), 261 mc_make_sec_cfg(PCIE2AR, NON_SECURE, OVERRIDE, DISABLE), 262 mc_make_sec_cfg(PCIE2AW, NON_SECURE, OVERRIDE, DISABLE), 263 mc_make_sec_cfg(PCIE3R, NON_SECURE, OVERRIDE, DISABLE), 264 mc_make_sec_cfg(PCIE3W, NON_SECURE, OVERRIDE, DISABLE), 265 mc_make_sec_cfg(PCIE4R, NON_SECURE, OVERRIDE, DISABLE), 266 mc_make_sec_cfg(PCIE4W, NON_SECURE, OVERRIDE, DISABLE), 267 mc_make_sec_cfg(PCIE5R, NON_SECURE, OVERRIDE, DISABLE), 268 mc_make_sec_cfg(PCIE5W, NON_SECURE, OVERRIDE, DISABLE), 269 mc_make_sec_cfg(ISPFALW, NON_SECURE, NO_OVERRIDE, ENABLE), 270 mc_make_sec_cfg(DLA0RDA1, NON_SECURE, NO_OVERRIDE, DISABLE), 271 mc_make_sec_cfg(DLA1RDA1, NON_SECURE, NO_OVERRIDE, DISABLE), 272 mc_make_sec_cfg(PVA0RDA1, NON_SECURE, NO_OVERRIDE, DISABLE), 273 mc_make_sec_cfg(PVA0RDB1, NON_SECURE, NO_OVERRIDE, DISABLE), 274 mc_make_sec_cfg(PVA1RDA1, NON_SECURE, NO_OVERRIDE, DISABLE), 275 mc_make_sec_cfg(PVA1RDB1, NON_SECURE, NO_OVERRIDE, DISABLE), 276 mc_make_sec_cfg(PCIE5R1, NON_SECURE, OVERRIDE, DISABLE), 277 mc_make_sec_cfg(NVENCSRD1, NON_SECURE, NO_OVERRIDE, DISABLE), 278 mc_make_sec_cfg(NVENC1SRD1, NON_SECURE, NO_OVERRIDE, DISABLE), 279 mc_make_sec_cfg(ISPRA1, NON_SECURE, NO_OVERRIDE, ENABLE), 280 mc_make_sec_cfg(PCIE0R1, NON_SECURE, OVERRIDE, DISABLE), 281 mc_make_sec_cfg(NVDEC1SRD, NON_SECURE, NO_OVERRIDE, DISABLE), 282 mc_make_sec_cfg(NVDEC1SRD1, NON_SECURE, NO_OVERRIDE, DISABLE), 283 mc_make_sec_cfg(NVDEC1SWR, NON_SECURE, NO_OVERRIDE, DISABLE), 284 mc_make_sec_cfg(MIU0R, NON_SECURE, OVERRIDE, DISABLE), 285 mc_make_sec_cfg(MIU0W, NON_SECURE, OVERRIDE, DISABLE), 286 mc_make_sec_cfg(MIU1R, NON_SECURE, OVERRIDE, DISABLE), 287 mc_make_sec_cfg(MIU1W, NON_SECURE, OVERRIDE, DISABLE), 288 mc_make_sec_cfg(MIU2R, NON_SECURE, OVERRIDE, DISABLE), 289 mc_make_sec_cfg(MIU2W, NON_SECURE, OVERRIDE, DISABLE), 290 mc_make_sec_cfg(MIU3R, NON_SECURE, OVERRIDE, DISABLE), 291 mc_make_sec_cfg(MIU3W, NON_SECURE, OVERRIDE, DISABLE), 292 mc_make_sec_cfg(MIU4R, NON_SECURE, OVERRIDE, DISABLE), 293 mc_make_sec_cfg(MIU4W, NON_SECURE, OVERRIDE, DISABLE), 294 mc_make_sec_cfg(MIU5R, NON_SECURE, OVERRIDE, DISABLE), 295 mc_make_sec_cfg(MIU5W, NON_SECURE, OVERRIDE, DISABLE), 296 mc_make_sec_cfg(MIU6R, NON_SECURE, OVERRIDE, DISABLE), 297 mc_make_sec_cfg(MIU6W, NON_SECURE, OVERRIDE, DISABLE), 298 mc_make_sec_cfg(MIU7R, NON_SECURE, OVERRIDE, DISABLE), 299 mc_make_sec_cfg(MIU7W, NON_SECURE, OVERRIDE, DISABLE) 300 }; 301 302 /******************************************************************************* 303 * Array to hold MC context for Tegra194 304 ******************************************************************************/ 305 static __attribute__((aligned(16))) mc_regs_t tegra194_mc_context[] = { 306 _START_OF_TABLE_, 307 mc_make_sid_security_cfg(HDAR), 308 mc_make_sid_security_cfg(HOST1XDMAR), 309 mc_make_sid_security_cfg(NVENCSRD), 310 mc_make_sid_security_cfg(SATAR), 311 mc_make_sid_security_cfg(NVENCSWR), 312 mc_make_sid_security_cfg(HDAW), 313 mc_make_sid_security_cfg(SATAW), 314 mc_make_sid_security_cfg(ISPRA), 315 mc_make_sid_security_cfg(ISPFALR), 316 mc_make_sid_security_cfg(ISPWA), 317 mc_make_sid_security_cfg(ISPWB), 318 mc_make_sid_security_cfg(XUSB_HOSTR), 319 mc_make_sid_security_cfg(XUSB_HOSTW), 320 mc_make_sid_security_cfg(XUSB_DEVR), 321 mc_make_sid_security_cfg(XUSB_DEVW), 322 mc_make_sid_security_cfg(TSECSRD), 323 mc_make_sid_security_cfg(TSECSWR), 324 mc_make_sid_security_cfg(SDMMCRA), 325 mc_make_sid_security_cfg(SDMMCR), 326 mc_make_sid_security_cfg(SDMMCRAB), 327 mc_make_sid_security_cfg(SDMMCWA), 328 mc_make_sid_security_cfg(SDMMCW), 329 mc_make_sid_security_cfg(SDMMCWAB), 330 mc_make_sid_security_cfg(VICSRD), 331 mc_make_sid_security_cfg(VICSWR), 332 mc_make_sid_security_cfg(VIW), 333 mc_make_sid_security_cfg(NVDECSRD), 334 mc_make_sid_security_cfg(NVDECSWR), 335 mc_make_sid_security_cfg(APER), 336 mc_make_sid_security_cfg(APEW), 337 mc_make_sid_security_cfg(NVJPGSRD), 338 mc_make_sid_security_cfg(NVJPGSWR), 339 mc_make_sid_security_cfg(SESRD), 340 mc_make_sid_security_cfg(SESWR), 341 mc_make_sid_security_cfg(AXIAPR), 342 mc_make_sid_security_cfg(AXIAPW), 343 mc_make_sid_security_cfg(ETRR), 344 mc_make_sid_security_cfg(ETRW), 345 mc_make_sid_security_cfg(TSECSRDB), 346 mc_make_sid_security_cfg(TSECSWRB), 347 mc_make_sid_security_cfg(AXISR), 348 mc_make_sid_security_cfg(AXISW), 349 mc_make_sid_security_cfg(EQOSR), 350 mc_make_sid_security_cfg(EQOSW), 351 mc_make_sid_security_cfg(UFSHCR), 352 mc_make_sid_security_cfg(UFSHCW), 353 mc_make_sid_security_cfg(NVDISPLAYR), 354 mc_make_sid_security_cfg(BPMPR), 355 mc_make_sid_security_cfg(BPMPW), 356 mc_make_sid_security_cfg(BPMPDMAR), 357 mc_make_sid_security_cfg(BPMPDMAW), 358 mc_make_sid_security_cfg(AONR), 359 mc_make_sid_security_cfg(AONW), 360 mc_make_sid_security_cfg(AONDMAR), 361 mc_make_sid_security_cfg(AONDMAW), 362 mc_make_sid_security_cfg(SCER), 363 mc_make_sid_security_cfg(SCEW), 364 mc_make_sid_security_cfg(SCEDMAR), 365 mc_make_sid_security_cfg(SCEDMAW), 366 mc_make_sid_security_cfg(APEDMAR), 367 mc_make_sid_security_cfg(APEDMAW), 368 mc_make_sid_security_cfg(NVDISPLAYR1), 369 mc_make_sid_security_cfg(VICSRD1), 370 mc_make_sid_security_cfg(NVDECSRD1), 371 mc_make_sid_security_cfg(VIFALR), 372 mc_make_sid_security_cfg(VIFALW), 373 mc_make_sid_security_cfg(DLA0RDA), 374 mc_make_sid_security_cfg(DLA0FALRDB), 375 mc_make_sid_security_cfg(DLA0WRA), 376 mc_make_sid_security_cfg(DLA0FALWRB), 377 mc_make_sid_security_cfg(DLA1RDA), 378 mc_make_sid_security_cfg(DLA1FALRDB), 379 mc_make_sid_security_cfg(DLA1WRA), 380 mc_make_sid_security_cfg(DLA1FALWRB), 381 mc_make_sid_security_cfg(PVA0RDA), 382 mc_make_sid_security_cfg(PVA0RDB), 383 mc_make_sid_security_cfg(PVA0RDC), 384 mc_make_sid_security_cfg(PVA0WRA), 385 mc_make_sid_security_cfg(PVA0WRB), 386 mc_make_sid_security_cfg(PVA0WRC), 387 mc_make_sid_security_cfg(PVA1RDA), 388 mc_make_sid_security_cfg(PVA1RDB), 389 mc_make_sid_security_cfg(PVA1RDC), 390 mc_make_sid_security_cfg(PVA1WRA), 391 mc_make_sid_security_cfg(PVA1WRB), 392 mc_make_sid_security_cfg(PVA1WRC), 393 mc_make_sid_security_cfg(RCER), 394 mc_make_sid_security_cfg(RCEW), 395 mc_make_sid_security_cfg(RCEDMAR), 396 mc_make_sid_security_cfg(RCEDMAW), 397 mc_make_sid_security_cfg(NVENC1SRD), 398 mc_make_sid_security_cfg(NVENC1SWR), 399 mc_make_sid_security_cfg(PCIE0R), 400 mc_make_sid_security_cfg(PCIE0W), 401 mc_make_sid_security_cfg(PCIE1R), 402 mc_make_sid_security_cfg(PCIE1W), 403 mc_make_sid_security_cfg(PCIE2AR), 404 mc_make_sid_security_cfg(PCIE2AW), 405 mc_make_sid_security_cfg(PCIE3R), 406 mc_make_sid_security_cfg(PCIE3W), 407 mc_make_sid_security_cfg(PCIE4R), 408 mc_make_sid_security_cfg(PCIE4W), 409 mc_make_sid_security_cfg(PCIE5R), 410 mc_make_sid_security_cfg(PCIE5W), 411 mc_make_sid_security_cfg(ISPFALW), 412 mc_make_sid_security_cfg(DLA0RDA1), 413 mc_make_sid_security_cfg(DLA1RDA1), 414 mc_make_sid_security_cfg(PVA0RDA1), 415 mc_make_sid_security_cfg(PVA0RDB1), 416 mc_make_sid_security_cfg(PVA1RDA1), 417 mc_make_sid_security_cfg(PVA1RDB1), 418 mc_make_sid_security_cfg(PCIE5R1), 419 mc_make_sid_security_cfg(NVENCSRD1), 420 mc_make_sid_security_cfg(NVENC1SRD1), 421 mc_make_sid_security_cfg(ISPRA1), 422 mc_make_sid_security_cfg(PCIE0R1), 423 mc_make_sid_security_cfg(MIU0R), 424 mc_make_sid_security_cfg(MIU0W), 425 mc_make_sid_security_cfg(MIU1R), 426 mc_make_sid_security_cfg(MIU1W), 427 mc_make_sid_security_cfg(MIU2R), 428 mc_make_sid_security_cfg(MIU2W), 429 mc_make_sid_security_cfg(MIU3R), 430 mc_make_sid_security_cfg(MIU3W), 431 mc_make_sid_override_cfg(HDAR), 432 mc_make_sid_override_cfg(HOST1XDMAR), 433 mc_make_sid_override_cfg(NVENCSRD), 434 mc_make_sid_override_cfg(SATAR), 435 mc_make_sid_override_cfg(NVENCSWR), 436 mc_make_sid_override_cfg(HDAW), 437 mc_make_sid_override_cfg(SATAW), 438 mc_make_sid_override_cfg(ISPRA), 439 mc_make_sid_override_cfg(ISPFALR), 440 mc_make_sid_override_cfg(ISPWA), 441 mc_make_sid_override_cfg(ISPWB), 442 mc_make_sid_override_cfg(XUSB_HOSTR), 443 mc_make_sid_override_cfg(XUSB_HOSTW), 444 mc_make_sid_override_cfg(XUSB_DEVR), 445 mc_make_sid_override_cfg(XUSB_DEVW), 446 mc_make_sid_override_cfg(TSECSRD), 447 mc_make_sid_override_cfg(TSECSWR), 448 mc_make_sid_override_cfg(SDMMCRA), 449 mc_make_sid_override_cfg(SDMMCR), 450 mc_make_sid_override_cfg(SDMMCRAB), 451 mc_make_sid_override_cfg(SDMMCWA), 452 mc_make_sid_override_cfg(SDMMCW), 453 mc_make_sid_override_cfg(SDMMCWAB), 454 mc_make_sid_override_cfg(VICSRD), 455 mc_make_sid_override_cfg(VICSWR), 456 mc_make_sid_override_cfg(VIW), 457 mc_make_sid_override_cfg(NVDECSRD), 458 mc_make_sid_override_cfg(NVDECSWR), 459 mc_make_sid_override_cfg(APER), 460 mc_make_sid_override_cfg(APEW), 461 mc_make_sid_override_cfg(NVJPGSRD), 462 mc_make_sid_override_cfg(NVJPGSWR), 463 mc_make_sid_override_cfg(SESRD), 464 mc_make_sid_override_cfg(SESWR), 465 mc_make_sid_override_cfg(AXIAPR), 466 mc_make_sid_override_cfg(AXIAPW), 467 mc_make_sid_override_cfg(ETRR), 468 mc_make_sid_override_cfg(ETRW), 469 mc_make_sid_override_cfg(TSECSRDB), 470 mc_make_sid_override_cfg(TSECSWRB), 471 mc_make_sid_override_cfg(AXISR), 472 mc_make_sid_override_cfg(AXISW), 473 mc_make_sid_override_cfg(EQOSR), 474 mc_make_sid_override_cfg(EQOSW), 475 mc_make_sid_override_cfg(UFSHCR), 476 mc_make_sid_override_cfg(UFSHCW), 477 mc_make_sid_override_cfg(NVDISPLAYR), 478 mc_make_sid_override_cfg(BPMPR), 479 mc_make_sid_override_cfg(BPMPW), 480 mc_make_sid_override_cfg(BPMPDMAR), 481 mc_make_sid_override_cfg(BPMPDMAW), 482 mc_make_sid_override_cfg(AONR), 483 mc_make_sid_override_cfg(AONW), 484 mc_make_sid_override_cfg(AONDMAR), 485 mc_make_sid_override_cfg(AONDMAW), 486 mc_make_sid_override_cfg(SCER), 487 mc_make_sid_override_cfg(SCEW), 488 mc_make_sid_override_cfg(SCEDMAR), 489 mc_make_sid_override_cfg(SCEDMAW), 490 mc_make_sid_override_cfg(APEDMAR), 491 mc_make_sid_override_cfg(APEDMAW), 492 mc_make_sid_override_cfg(NVDISPLAYR1), 493 mc_make_sid_override_cfg(VICSRD1), 494 mc_make_sid_override_cfg(NVDECSRD1), 495 mc_make_sid_override_cfg(VIFALR), 496 mc_make_sid_override_cfg(VIFALW), 497 mc_make_sid_override_cfg(DLA0RDA), 498 mc_make_sid_override_cfg(DLA0FALRDB), 499 mc_make_sid_override_cfg(DLA0WRA), 500 mc_make_sid_override_cfg(DLA0FALWRB), 501 mc_make_sid_override_cfg(DLA1RDA), 502 mc_make_sid_override_cfg(DLA1FALRDB), 503 mc_make_sid_override_cfg(DLA1WRA), 504 mc_make_sid_override_cfg(DLA1FALWRB), 505 mc_make_sid_override_cfg(PVA0RDA), 506 mc_make_sid_override_cfg(PVA0RDB), 507 mc_make_sid_override_cfg(PVA0RDC), 508 mc_make_sid_override_cfg(PVA0WRA), 509 mc_make_sid_override_cfg(PVA0WRB), 510 mc_make_sid_override_cfg(PVA0WRC), 511 mc_make_sid_override_cfg(PVA1RDA), 512 mc_make_sid_override_cfg(PVA1RDB), 513 mc_make_sid_override_cfg(PVA1RDC), 514 mc_make_sid_override_cfg(PVA1WRA), 515 mc_make_sid_override_cfg(PVA1WRB), 516 mc_make_sid_override_cfg(PVA1WRC), 517 mc_make_sid_override_cfg(RCER), 518 mc_make_sid_override_cfg(RCEW), 519 mc_make_sid_override_cfg(RCEDMAR), 520 mc_make_sid_override_cfg(RCEDMAW), 521 mc_make_sid_override_cfg(NVENC1SRD), 522 mc_make_sid_override_cfg(NVENC1SWR), 523 mc_make_sid_override_cfg(PCIE0R), 524 mc_make_sid_override_cfg(PCIE0W), 525 mc_make_sid_override_cfg(PCIE1R), 526 mc_make_sid_override_cfg(PCIE1W), 527 mc_make_sid_override_cfg(PCIE2AR), 528 mc_make_sid_override_cfg(PCIE2AW), 529 mc_make_sid_override_cfg(PCIE3R), 530 mc_make_sid_override_cfg(PCIE3W), 531 mc_make_sid_override_cfg(PCIE4R), 532 mc_make_sid_override_cfg(PCIE4W), 533 mc_make_sid_override_cfg(PCIE5R), 534 mc_make_sid_override_cfg(PCIE5W), 535 mc_make_sid_override_cfg(ISPFALW), 536 mc_make_sid_override_cfg(DLA0RDA1), 537 mc_make_sid_override_cfg(DLA1RDA1), 538 mc_make_sid_override_cfg(PVA0RDA1), 539 mc_make_sid_override_cfg(PVA0RDB1), 540 mc_make_sid_override_cfg(PVA1RDA1), 541 mc_make_sid_override_cfg(PVA1RDB1), 542 mc_make_sid_override_cfg(PCIE5R1), 543 mc_make_sid_override_cfg(NVENCSRD1), 544 mc_make_sid_override_cfg(NVENC1SRD1), 545 mc_make_sid_override_cfg(ISPRA1), 546 mc_make_sid_override_cfg(PCIE0R1), 547 mc_make_sid_override_cfg(MIU0R), 548 mc_make_sid_override_cfg(MIU0W), 549 mc_make_sid_override_cfg(MIU1R), 550 mc_make_sid_override_cfg(MIU1W), 551 mc_make_sid_override_cfg(MIU2R), 552 mc_make_sid_override_cfg(MIU2W), 553 mc_make_sid_override_cfg(MIU3R), 554 mc_make_sid_override_cfg(MIU3W), 555 mc_smmu_bypass_cfg, /* TBU settings */ 556 _END_OF_TABLE_, 557 }; 558 559 /******************************************************************************* 560 * Handler to return the pointer to the MC's context struct 561 ******************************************************************************/ 562 static mc_regs_t *tegra194_get_mc_system_suspend_ctx(void) 563 { 564 /* index of _END_OF_TABLE_ */ 565 tegra194_mc_context[0].val = (uint32_t)ARRAY_SIZE(tegra194_mc_context) - 1U; 566 567 return tegra194_mc_context; 568 } 569 570 /******************************************************************************* 571 * Struct to hold the memory controller settings 572 ******************************************************************************/ 573 static tegra_mc_settings_t tegra194_mc_settings = { 574 .streamid_override_cfg = tegra194_streamid_override_regs, 575 .num_streamid_override_cfgs = (uint32_t)ARRAY_SIZE(tegra194_streamid_override_regs), 576 .streamid_security_cfg = tegra194_streamid_sec_cfgs, 577 .num_streamid_security_cfgs = (uint32_t)ARRAY_SIZE(tegra194_streamid_sec_cfgs), 578 .get_mc_system_suspend_ctx = tegra194_get_mc_system_suspend_ctx 579 }; 580 581 /******************************************************************************* 582 * Handler to return the pointer to the memory controller's settings struct 583 ******************************************************************************/ 584 tegra_mc_settings_t *tegra_get_mc_settings(void) 585 { 586 return &tegra194_mc_settings; 587 } 588 589 /******************************************************************************* 590 * Handler to program the scratch registers with TZDRAM settings for the 591 * resume firmware 592 ******************************************************************************/ 593 void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes) 594 { 595 uint32_t sec_reg_ctrl = tegra_mc_read_32(MC_SECURITY_CFG_REG_CTRL_0); 596 597 /* 598 * Check TZDRAM carveout register access status. Setup TZDRAM fence 599 * only if access is enabled. 600 */ 601 if ((sec_reg_ctrl & SECURITY_CFG_WRITE_ACCESS_BIT) == 602 SECURITY_CFG_WRITE_ACCESS_ENABLE) { 603 604 /* 605 * Setup the Memory controller to allow only secure accesses to 606 * the TZDRAM carveout 607 */ 608 INFO("Configuring TrustZone DRAM Memory Carveout\n"); 609 610 tegra_mc_write_32(MC_SECURITY_CFG0_0, (uint32_t)phys_base); 611 tegra_mc_write_32(MC_SECURITY_CFG3_0, (uint32_t)(phys_base >> 32)); 612 tegra_mc_write_32(MC_SECURITY_CFG1_0, (uint32_t)(size_in_bytes >> 20)); 613 614 /* 615 * MCE propagates the security configuration values across the 616 * CCPLEX. 617 */ 618 (void)mce_update_gsc_tzdram(); 619 } 620 } 621