1 /* 2 * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <common/bl_common.h> 9 #include <mce.h> 10 #include <memctrl_v2.h> 11 #include <tegra_mc_def.h> 12 #include <tegra_platform.h> 13 14 /******************************************************************************* 15 * Array to hold the security configs for stream IDs 16 ******************************************************************************/ 17 const static mc_streamid_security_cfg_t tegra194_streamid_sec_cfgs[] = { 18 mc_make_sec_cfg(PTCR, NON_SECURE, OVERRIDE, DISABLE), 19 mc_make_sec_cfg(HDAR, NON_SECURE, OVERRIDE, DISABLE), 20 mc_make_sec_cfg(HOST1XDMAR, NON_SECURE, NO_OVERRIDE, DISABLE), 21 mc_make_sec_cfg(NVENCSRD, NON_SECURE, NO_OVERRIDE, DISABLE), 22 mc_make_sec_cfg(SATAR, NON_SECURE, OVERRIDE, DISABLE), 23 mc_make_sec_cfg(MPCORER, NON_SECURE, OVERRIDE, DISABLE), 24 mc_make_sec_cfg(NVENCSWR, NON_SECURE, NO_OVERRIDE, DISABLE), 25 mc_make_sec_cfg(HDAW, NON_SECURE, OVERRIDE, DISABLE), 26 mc_make_sec_cfg(MPCOREW, NON_SECURE, OVERRIDE, DISABLE), 27 mc_make_sec_cfg(SATAW, NON_SECURE, OVERRIDE, DISABLE), 28 mc_make_sec_cfg(ISPRA, NON_SECURE, NO_OVERRIDE, ENABLE), 29 mc_make_sec_cfg(ISPFALR, NON_SECURE, NO_OVERRIDE, ENABLE), 30 mc_make_sec_cfg(ISPWA, NON_SECURE, NO_OVERRIDE, ENABLE), 31 mc_make_sec_cfg(ISPWB, NON_SECURE, NO_OVERRIDE, ENABLE), 32 mc_make_sec_cfg(XUSB_HOSTR, NON_SECURE, NO_OVERRIDE, ENABLE), 33 mc_make_sec_cfg(XUSB_HOSTW, NON_SECURE, NO_OVERRIDE, ENABLE), 34 mc_make_sec_cfg(XUSB_DEVR, NON_SECURE, NO_OVERRIDE, ENABLE), 35 mc_make_sec_cfg(XUSB_DEVW, NON_SECURE, NO_OVERRIDE, ENABLE), 36 mc_make_sec_cfg(TSECSRD, NON_SECURE, NO_OVERRIDE, DISABLE), 37 mc_make_sec_cfg(TSECSWR, NON_SECURE, NO_OVERRIDE, DISABLE), 38 mc_make_sec_cfg(SDMMCRA, NON_SECURE, OVERRIDE, DISABLE), 39 mc_make_sec_cfg(SDMMCR, NON_SECURE, OVERRIDE, DISABLE), 40 mc_make_sec_cfg(SDMMCRAB, NON_SECURE, OVERRIDE, DISABLE), 41 mc_make_sec_cfg(SDMMCWA, NON_SECURE, OVERRIDE, DISABLE), 42 mc_make_sec_cfg(SDMMCW, NON_SECURE, OVERRIDE, DISABLE), 43 mc_make_sec_cfg(SDMMCWAB, NON_SECURE, OVERRIDE, DISABLE), 44 mc_make_sec_cfg(VICSRD, NON_SECURE, NO_OVERRIDE, DISABLE), 45 mc_make_sec_cfg(VICSWR, NON_SECURE, NO_OVERRIDE, DISABLE), 46 mc_make_sec_cfg(VIW, NON_SECURE, NO_OVERRIDE, ENABLE), 47 mc_make_sec_cfg(NVDECSRD, NON_SECURE, NO_OVERRIDE, DISABLE), 48 mc_make_sec_cfg(NVDECSWR, NON_SECURE, NO_OVERRIDE, DISABLE), 49 mc_make_sec_cfg(APER, NON_SECURE, NO_OVERRIDE, DISABLE), 50 mc_make_sec_cfg(APEW, NON_SECURE, NO_OVERRIDE, DISABLE), 51 mc_make_sec_cfg(NVJPGSRD, NON_SECURE, NO_OVERRIDE, DISABLE), 52 mc_make_sec_cfg(NVJPGSWR, NON_SECURE, NO_OVERRIDE, DISABLE), 53 mc_make_sec_cfg(SESRD, NON_SECURE, NO_OVERRIDE, DISABLE), 54 mc_make_sec_cfg(SESWR, NON_SECURE, NO_OVERRIDE, DISABLE), 55 mc_make_sec_cfg(AXIAPR, NON_SECURE, OVERRIDE, DISABLE), 56 mc_make_sec_cfg(AXIAPW, NON_SECURE, OVERRIDE, DISABLE), 57 mc_make_sec_cfg(ETRR, NON_SECURE, OVERRIDE, DISABLE), 58 mc_make_sec_cfg(ETRW, NON_SECURE, OVERRIDE, DISABLE), 59 mc_make_sec_cfg(TSECSRDB, NON_SECURE, NO_OVERRIDE, DISABLE), 60 mc_make_sec_cfg(TSECSWRB, NON_SECURE, NO_OVERRIDE, DISABLE), 61 mc_make_sec_cfg(AXISR, SECURE, NO_OVERRIDE, DISABLE), 62 mc_make_sec_cfg(AXISW, SECURE, NO_OVERRIDE, DISABLE), 63 mc_make_sec_cfg(EQOSR, NON_SECURE, OVERRIDE, DISABLE), 64 mc_make_sec_cfg(EQOSW, NON_SECURE, OVERRIDE, DISABLE), 65 mc_make_sec_cfg(UFSHCR, NON_SECURE, OVERRIDE, DISABLE), 66 mc_make_sec_cfg(UFSHCW, NON_SECURE, OVERRIDE, DISABLE), 67 mc_make_sec_cfg(NVDISPLAYR, NON_SECURE, OVERRIDE, DISABLE), 68 mc_make_sec_cfg(BPMPR, NON_SECURE, NO_OVERRIDE, DISABLE), 69 mc_make_sec_cfg(BPMPW, NON_SECURE, NO_OVERRIDE, DISABLE), 70 mc_make_sec_cfg(BPMPDMAR, NON_SECURE, NO_OVERRIDE, DISABLE), 71 mc_make_sec_cfg(BPMPDMAW, NON_SECURE, NO_OVERRIDE, DISABLE), 72 mc_make_sec_cfg(AONR, NON_SECURE, NO_OVERRIDE, DISABLE), 73 mc_make_sec_cfg(AONW, NON_SECURE, NO_OVERRIDE, DISABLE), 74 mc_make_sec_cfg(AONDMAR, NON_SECURE, NO_OVERRIDE, DISABLE), 75 mc_make_sec_cfg(AONDMAW, NON_SECURE, NO_OVERRIDE, DISABLE), 76 mc_make_sec_cfg(SCER, NON_SECURE, NO_OVERRIDE, DISABLE), 77 mc_make_sec_cfg(SCEW, NON_SECURE, NO_OVERRIDE, DISABLE), 78 mc_make_sec_cfg(SCEDMAR, NON_SECURE, NO_OVERRIDE, DISABLE), 79 mc_make_sec_cfg(SCEDMAW, NON_SECURE, NO_OVERRIDE, DISABLE), 80 mc_make_sec_cfg(APEDMAR, NON_SECURE, NO_OVERRIDE, DISABLE), 81 mc_make_sec_cfg(APEDMAW, NON_SECURE, NO_OVERRIDE, DISABLE), 82 mc_make_sec_cfg(NVDISPLAYR1, NON_SECURE, OVERRIDE, DISABLE), 83 mc_make_sec_cfg(VICSRD1, NON_SECURE, NO_OVERRIDE, DISABLE), 84 mc_make_sec_cfg(NVDECSRD1, NON_SECURE, NO_OVERRIDE, DISABLE), 85 mc_make_sec_cfg(VIFALR, NON_SECURE, NO_OVERRIDE, ENABLE), 86 mc_make_sec_cfg(VIFALW, NON_SECURE, NO_OVERRIDE, ENABLE), 87 mc_make_sec_cfg(DLA0RDA, NON_SECURE, NO_OVERRIDE, DISABLE), 88 mc_make_sec_cfg(DLA0FALRDB, NON_SECURE, NO_OVERRIDE, DISABLE), 89 mc_make_sec_cfg(DLA0WRA, NON_SECURE, NO_OVERRIDE, DISABLE), 90 mc_make_sec_cfg(DLA0FALWRB, NON_SECURE, NO_OVERRIDE, DISABLE), 91 mc_make_sec_cfg(DLA1RDA, NON_SECURE, NO_OVERRIDE, DISABLE), 92 mc_make_sec_cfg(DLA1FALRDB, NON_SECURE, NO_OVERRIDE, DISABLE), 93 mc_make_sec_cfg(DLA1WRA, NON_SECURE, NO_OVERRIDE, DISABLE), 94 mc_make_sec_cfg(DLA1FALWRB, NON_SECURE, NO_OVERRIDE, DISABLE), 95 mc_make_sec_cfg(PVA0RDA, NON_SECURE, NO_OVERRIDE, DISABLE), 96 mc_make_sec_cfg(PVA0RDB, NON_SECURE, NO_OVERRIDE, DISABLE), 97 mc_make_sec_cfg(PVA0RDC, NON_SECURE, NO_OVERRIDE, DISABLE), 98 mc_make_sec_cfg(PVA0WRA, NON_SECURE, NO_OVERRIDE, DISABLE), 99 mc_make_sec_cfg(PVA0WRB, NON_SECURE, NO_OVERRIDE, DISABLE), 100 mc_make_sec_cfg(PVA0WRC, NON_SECURE, NO_OVERRIDE, DISABLE), 101 mc_make_sec_cfg(PVA1RDA, NON_SECURE, NO_OVERRIDE, DISABLE), 102 mc_make_sec_cfg(PVA1RDB, NON_SECURE, NO_OVERRIDE, DISABLE), 103 mc_make_sec_cfg(PVA1RDC, NON_SECURE, NO_OVERRIDE, DISABLE), 104 mc_make_sec_cfg(PVA1WRA, NON_SECURE, NO_OVERRIDE, DISABLE), 105 mc_make_sec_cfg(PVA1WRB, NON_SECURE, NO_OVERRIDE, DISABLE), 106 mc_make_sec_cfg(PVA1WRC, NON_SECURE, NO_OVERRIDE, DISABLE), 107 mc_make_sec_cfg(RCER, NON_SECURE, NO_OVERRIDE, DISABLE), 108 mc_make_sec_cfg(RCEW, NON_SECURE, NO_OVERRIDE, DISABLE), 109 mc_make_sec_cfg(RCEDMAR, NON_SECURE, NO_OVERRIDE, DISABLE), 110 mc_make_sec_cfg(RCEDMAW, NON_SECURE, NO_OVERRIDE, DISABLE), 111 mc_make_sec_cfg(NVENC1SRD, NON_SECURE, NO_OVERRIDE, DISABLE), 112 mc_make_sec_cfg(NVENC1SWR, NON_SECURE, NO_OVERRIDE, DISABLE), 113 mc_make_sec_cfg(PCIE0R, NON_SECURE, OVERRIDE, DISABLE), 114 mc_make_sec_cfg(PCIE0W, NON_SECURE, OVERRIDE, DISABLE), 115 mc_make_sec_cfg(PCIE1R, NON_SECURE, OVERRIDE, DISABLE), 116 mc_make_sec_cfg(PCIE1W, NON_SECURE, OVERRIDE, DISABLE), 117 mc_make_sec_cfg(PCIE2AR, NON_SECURE, OVERRIDE, DISABLE), 118 mc_make_sec_cfg(PCIE2AW, NON_SECURE, OVERRIDE, DISABLE), 119 mc_make_sec_cfg(PCIE3R, NON_SECURE, OVERRIDE, DISABLE), 120 mc_make_sec_cfg(PCIE3W, NON_SECURE, OVERRIDE, DISABLE), 121 mc_make_sec_cfg(PCIE4R, NON_SECURE, OVERRIDE, DISABLE), 122 mc_make_sec_cfg(PCIE4W, NON_SECURE, OVERRIDE, DISABLE), 123 mc_make_sec_cfg(PCIE5R, NON_SECURE, OVERRIDE, DISABLE), 124 mc_make_sec_cfg(PCIE5W, NON_SECURE, OVERRIDE, DISABLE), 125 mc_make_sec_cfg(ISPFALW, NON_SECURE, NO_OVERRIDE, ENABLE), 126 mc_make_sec_cfg(DLA0RDA1, NON_SECURE, NO_OVERRIDE, DISABLE), 127 mc_make_sec_cfg(DLA1RDA1, NON_SECURE, NO_OVERRIDE, DISABLE), 128 mc_make_sec_cfg(PVA0RDA1, NON_SECURE, NO_OVERRIDE, DISABLE), 129 mc_make_sec_cfg(PVA0RDB1, NON_SECURE, NO_OVERRIDE, DISABLE), 130 mc_make_sec_cfg(PVA1RDA1, NON_SECURE, NO_OVERRIDE, DISABLE), 131 mc_make_sec_cfg(PVA1RDB1, NON_SECURE, NO_OVERRIDE, DISABLE), 132 mc_make_sec_cfg(PCIE5R1, NON_SECURE, OVERRIDE, DISABLE), 133 mc_make_sec_cfg(NVENCSRD1, NON_SECURE, NO_OVERRIDE, DISABLE), 134 mc_make_sec_cfg(NVENC1SRD1, NON_SECURE, NO_OVERRIDE, DISABLE), 135 mc_make_sec_cfg(ISPRA1, NON_SECURE, NO_OVERRIDE, ENABLE), 136 mc_make_sec_cfg(PCIE0R1, NON_SECURE, OVERRIDE, DISABLE), 137 mc_make_sec_cfg(NVDEC1SRD, NON_SECURE, NO_OVERRIDE, DISABLE), 138 mc_make_sec_cfg(NVDEC1SRD1, NON_SECURE, NO_OVERRIDE, DISABLE), 139 mc_make_sec_cfg(NVDEC1SWR, NON_SECURE, NO_OVERRIDE, DISABLE), 140 mc_make_sec_cfg(MIU0R, NON_SECURE, OVERRIDE, DISABLE), 141 mc_make_sec_cfg(MIU0W, NON_SECURE, OVERRIDE, DISABLE), 142 mc_make_sec_cfg(MIU1R, NON_SECURE, OVERRIDE, DISABLE), 143 mc_make_sec_cfg(MIU1W, NON_SECURE, OVERRIDE, DISABLE), 144 mc_make_sec_cfg(MIU2R, NON_SECURE, OVERRIDE, DISABLE), 145 mc_make_sec_cfg(MIU2W, NON_SECURE, OVERRIDE, DISABLE), 146 mc_make_sec_cfg(MIU3R, NON_SECURE, OVERRIDE, DISABLE), 147 mc_make_sec_cfg(MIU3W, NON_SECURE, OVERRIDE, DISABLE), 148 mc_make_sec_cfg(MIU4R, NON_SECURE, OVERRIDE, DISABLE), 149 mc_make_sec_cfg(MIU4W, NON_SECURE, OVERRIDE, DISABLE), 150 mc_make_sec_cfg(MIU5R, NON_SECURE, OVERRIDE, DISABLE), 151 mc_make_sec_cfg(MIU5W, NON_SECURE, OVERRIDE, DISABLE), 152 mc_make_sec_cfg(MIU6R, NON_SECURE, OVERRIDE, DISABLE), 153 mc_make_sec_cfg(MIU6W, NON_SECURE, OVERRIDE, DISABLE), 154 mc_make_sec_cfg(MIU7R, NON_SECURE, OVERRIDE, DISABLE), 155 mc_make_sec_cfg(MIU7W, NON_SECURE, OVERRIDE, DISABLE) 156 }; 157 158 /******************************************************************************* 159 * Array to hold MC context for Tegra194 160 ******************************************************************************/ 161 static __attribute__((aligned(16))) mc_regs_t tegra194_mc_context[] = { 162 _START_OF_TABLE_, 163 mc_make_sid_security_cfg(HDAR), 164 mc_make_sid_security_cfg(HOST1XDMAR), 165 mc_make_sid_security_cfg(NVENCSRD), 166 mc_make_sid_security_cfg(SATAR), 167 mc_make_sid_security_cfg(NVENCSWR), 168 mc_make_sid_security_cfg(HDAW), 169 mc_make_sid_security_cfg(SATAW), 170 mc_make_sid_security_cfg(ISPRA), 171 mc_make_sid_security_cfg(ISPFALR), 172 mc_make_sid_security_cfg(ISPWA), 173 mc_make_sid_security_cfg(ISPWB), 174 mc_make_sid_security_cfg(XUSB_HOSTR), 175 mc_make_sid_security_cfg(XUSB_HOSTW), 176 mc_make_sid_security_cfg(XUSB_DEVR), 177 mc_make_sid_security_cfg(XUSB_DEVW), 178 mc_make_sid_security_cfg(TSECSRD), 179 mc_make_sid_security_cfg(TSECSWR), 180 mc_make_sid_security_cfg(SDMMCRA), 181 mc_make_sid_security_cfg(SDMMCR), 182 mc_make_sid_security_cfg(SDMMCRAB), 183 mc_make_sid_security_cfg(SDMMCWA), 184 mc_make_sid_security_cfg(SDMMCW), 185 mc_make_sid_security_cfg(SDMMCWAB), 186 mc_make_sid_security_cfg(VICSRD), 187 mc_make_sid_security_cfg(VICSWR), 188 mc_make_sid_security_cfg(VIW), 189 mc_make_sid_security_cfg(NVDECSRD), 190 mc_make_sid_security_cfg(NVDECSWR), 191 mc_make_sid_security_cfg(APER), 192 mc_make_sid_security_cfg(APEW), 193 mc_make_sid_security_cfg(NVJPGSRD), 194 mc_make_sid_security_cfg(NVJPGSWR), 195 mc_make_sid_security_cfg(SESRD), 196 mc_make_sid_security_cfg(SESWR), 197 mc_make_sid_security_cfg(AXIAPR), 198 mc_make_sid_security_cfg(AXIAPW), 199 mc_make_sid_security_cfg(ETRR), 200 mc_make_sid_security_cfg(ETRW), 201 mc_make_sid_security_cfg(TSECSRDB), 202 mc_make_sid_security_cfg(TSECSWRB), 203 mc_make_sid_security_cfg(AXISR), 204 mc_make_sid_security_cfg(AXISW), 205 mc_make_sid_security_cfg(EQOSR), 206 mc_make_sid_security_cfg(EQOSW), 207 mc_make_sid_security_cfg(UFSHCR), 208 mc_make_sid_security_cfg(UFSHCW), 209 mc_make_sid_security_cfg(NVDISPLAYR), 210 mc_make_sid_security_cfg(BPMPR), 211 mc_make_sid_security_cfg(BPMPW), 212 mc_make_sid_security_cfg(BPMPDMAR), 213 mc_make_sid_security_cfg(BPMPDMAW), 214 mc_make_sid_security_cfg(AONR), 215 mc_make_sid_security_cfg(AONW), 216 mc_make_sid_security_cfg(AONDMAR), 217 mc_make_sid_security_cfg(AONDMAW), 218 mc_make_sid_security_cfg(SCER), 219 mc_make_sid_security_cfg(SCEW), 220 mc_make_sid_security_cfg(SCEDMAR), 221 mc_make_sid_security_cfg(SCEDMAW), 222 mc_make_sid_security_cfg(APEDMAR), 223 mc_make_sid_security_cfg(APEDMAW), 224 mc_make_sid_security_cfg(NVDISPLAYR1), 225 mc_make_sid_security_cfg(VICSRD1), 226 mc_make_sid_security_cfg(NVDECSRD1), 227 mc_make_sid_security_cfg(VIFALR), 228 mc_make_sid_security_cfg(VIFALW), 229 mc_make_sid_security_cfg(DLA0RDA), 230 mc_make_sid_security_cfg(DLA0FALRDB), 231 mc_make_sid_security_cfg(DLA0WRA), 232 mc_make_sid_security_cfg(DLA0FALWRB), 233 mc_make_sid_security_cfg(DLA1RDA), 234 mc_make_sid_security_cfg(DLA1FALRDB), 235 mc_make_sid_security_cfg(DLA1WRA), 236 mc_make_sid_security_cfg(DLA1FALWRB), 237 mc_make_sid_security_cfg(PVA0RDA), 238 mc_make_sid_security_cfg(PVA0RDB), 239 mc_make_sid_security_cfg(PVA0RDC), 240 mc_make_sid_security_cfg(PVA0WRA), 241 mc_make_sid_security_cfg(PVA0WRB), 242 mc_make_sid_security_cfg(PVA0WRC), 243 mc_make_sid_security_cfg(PVA1RDA), 244 mc_make_sid_security_cfg(PVA1RDB), 245 mc_make_sid_security_cfg(PVA1RDC), 246 mc_make_sid_security_cfg(PVA1WRA), 247 mc_make_sid_security_cfg(PVA1WRB), 248 mc_make_sid_security_cfg(PVA1WRC), 249 mc_make_sid_security_cfg(RCER), 250 mc_make_sid_security_cfg(RCEW), 251 mc_make_sid_security_cfg(RCEDMAR), 252 mc_make_sid_security_cfg(RCEDMAW), 253 mc_make_sid_security_cfg(NVENC1SRD), 254 mc_make_sid_security_cfg(NVENC1SWR), 255 mc_make_sid_security_cfg(PCIE0R), 256 mc_make_sid_security_cfg(PCIE0W), 257 mc_make_sid_security_cfg(PCIE1R), 258 mc_make_sid_security_cfg(PCIE1W), 259 mc_make_sid_security_cfg(PCIE2AR), 260 mc_make_sid_security_cfg(PCIE2AW), 261 mc_make_sid_security_cfg(PCIE3R), 262 mc_make_sid_security_cfg(PCIE3W), 263 mc_make_sid_security_cfg(PCIE4R), 264 mc_make_sid_security_cfg(PCIE4W), 265 mc_make_sid_security_cfg(PCIE5R), 266 mc_make_sid_security_cfg(PCIE5W), 267 mc_make_sid_security_cfg(ISPFALW), 268 mc_make_sid_security_cfg(DLA0RDA1), 269 mc_make_sid_security_cfg(DLA1RDA1), 270 mc_make_sid_security_cfg(PVA0RDA1), 271 mc_make_sid_security_cfg(PVA0RDB1), 272 mc_make_sid_security_cfg(PVA1RDA1), 273 mc_make_sid_security_cfg(PVA1RDB1), 274 mc_make_sid_security_cfg(PCIE5R1), 275 mc_make_sid_security_cfg(NVENCSRD1), 276 mc_make_sid_security_cfg(NVENC1SRD1), 277 mc_make_sid_security_cfg(ISPRA1), 278 mc_make_sid_security_cfg(PCIE0R1), 279 mc_make_sid_security_cfg(MIU0R), 280 mc_make_sid_security_cfg(MIU0W), 281 mc_make_sid_security_cfg(MIU1R), 282 mc_make_sid_security_cfg(MIU1W), 283 mc_make_sid_security_cfg(MIU2R), 284 mc_make_sid_security_cfg(MIU2W), 285 mc_make_sid_security_cfg(MIU3R), 286 mc_make_sid_security_cfg(MIU3W), 287 mc_make_sid_override_cfg(HDAR), 288 mc_make_sid_override_cfg(HOST1XDMAR), 289 mc_make_sid_override_cfg(NVENCSRD), 290 mc_make_sid_override_cfg(SATAR), 291 mc_make_sid_override_cfg(NVENCSWR), 292 mc_make_sid_override_cfg(HDAW), 293 mc_make_sid_override_cfg(SATAW), 294 mc_make_sid_override_cfg(ISPRA), 295 mc_make_sid_override_cfg(ISPFALR), 296 mc_make_sid_override_cfg(ISPWA), 297 mc_make_sid_override_cfg(ISPWB), 298 mc_make_sid_override_cfg(XUSB_HOSTR), 299 mc_make_sid_override_cfg(XUSB_HOSTW), 300 mc_make_sid_override_cfg(XUSB_DEVR), 301 mc_make_sid_override_cfg(XUSB_DEVW), 302 mc_make_sid_override_cfg(TSECSRD), 303 mc_make_sid_override_cfg(TSECSWR), 304 mc_make_sid_override_cfg(SDMMCRA), 305 mc_make_sid_override_cfg(SDMMCR), 306 mc_make_sid_override_cfg(SDMMCRAB), 307 mc_make_sid_override_cfg(SDMMCWA), 308 mc_make_sid_override_cfg(SDMMCW), 309 mc_make_sid_override_cfg(SDMMCWAB), 310 mc_make_sid_override_cfg(VICSRD), 311 mc_make_sid_override_cfg(VICSWR), 312 mc_make_sid_override_cfg(VIW), 313 mc_make_sid_override_cfg(NVDECSRD), 314 mc_make_sid_override_cfg(NVDECSWR), 315 mc_make_sid_override_cfg(APER), 316 mc_make_sid_override_cfg(APEW), 317 mc_make_sid_override_cfg(NVJPGSRD), 318 mc_make_sid_override_cfg(NVJPGSWR), 319 mc_make_sid_override_cfg(SESRD), 320 mc_make_sid_override_cfg(SESWR), 321 mc_make_sid_override_cfg(AXIAPR), 322 mc_make_sid_override_cfg(AXIAPW), 323 mc_make_sid_override_cfg(ETRR), 324 mc_make_sid_override_cfg(ETRW), 325 mc_make_sid_override_cfg(TSECSRDB), 326 mc_make_sid_override_cfg(TSECSWRB), 327 mc_make_sid_override_cfg(AXISR), 328 mc_make_sid_override_cfg(AXISW), 329 mc_make_sid_override_cfg(EQOSR), 330 mc_make_sid_override_cfg(EQOSW), 331 mc_make_sid_override_cfg(UFSHCR), 332 mc_make_sid_override_cfg(UFSHCW), 333 mc_make_sid_override_cfg(NVDISPLAYR), 334 mc_make_sid_override_cfg(BPMPR), 335 mc_make_sid_override_cfg(BPMPW), 336 mc_make_sid_override_cfg(BPMPDMAR), 337 mc_make_sid_override_cfg(BPMPDMAW), 338 mc_make_sid_override_cfg(AONR), 339 mc_make_sid_override_cfg(AONW), 340 mc_make_sid_override_cfg(AONDMAR), 341 mc_make_sid_override_cfg(AONDMAW), 342 mc_make_sid_override_cfg(SCER), 343 mc_make_sid_override_cfg(SCEW), 344 mc_make_sid_override_cfg(SCEDMAR), 345 mc_make_sid_override_cfg(SCEDMAW), 346 mc_make_sid_override_cfg(APEDMAR), 347 mc_make_sid_override_cfg(APEDMAW), 348 mc_make_sid_override_cfg(NVDISPLAYR1), 349 mc_make_sid_override_cfg(VICSRD1), 350 mc_make_sid_override_cfg(NVDECSRD1), 351 mc_make_sid_override_cfg(VIFALR), 352 mc_make_sid_override_cfg(VIFALW), 353 mc_make_sid_override_cfg(DLA0RDA), 354 mc_make_sid_override_cfg(DLA0FALRDB), 355 mc_make_sid_override_cfg(DLA0WRA), 356 mc_make_sid_override_cfg(DLA0FALWRB), 357 mc_make_sid_override_cfg(DLA1RDA), 358 mc_make_sid_override_cfg(DLA1FALRDB), 359 mc_make_sid_override_cfg(DLA1WRA), 360 mc_make_sid_override_cfg(DLA1FALWRB), 361 mc_make_sid_override_cfg(PVA0RDA), 362 mc_make_sid_override_cfg(PVA0RDB), 363 mc_make_sid_override_cfg(PVA0RDC), 364 mc_make_sid_override_cfg(PVA0WRA), 365 mc_make_sid_override_cfg(PVA0WRB), 366 mc_make_sid_override_cfg(PVA0WRC), 367 mc_make_sid_override_cfg(PVA1RDA), 368 mc_make_sid_override_cfg(PVA1RDB), 369 mc_make_sid_override_cfg(PVA1RDC), 370 mc_make_sid_override_cfg(PVA1WRA), 371 mc_make_sid_override_cfg(PVA1WRB), 372 mc_make_sid_override_cfg(PVA1WRC), 373 mc_make_sid_override_cfg(RCER), 374 mc_make_sid_override_cfg(RCEW), 375 mc_make_sid_override_cfg(RCEDMAR), 376 mc_make_sid_override_cfg(RCEDMAW), 377 mc_make_sid_override_cfg(NVENC1SRD), 378 mc_make_sid_override_cfg(NVENC1SWR), 379 mc_make_sid_override_cfg(PCIE0R), 380 mc_make_sid_override_cfg(PCIE0W), 381 mc_make_sid_override_cfg(PCIE1R), 382 mc_make_sid_override_cfg(PCIE1W), 383 mc_make_sid_override_cfg(PCIE2AR), 384 mc_make_sid_override_cfg(PCIE2AW), 385 mc_make_sid_override_cfg(PCIE3R), 386 mc_make_sid_override_cfg(PCIE3W), 387 mc_make_sid_override_cfg(PCIE4R), 388 mc_make_sid_override_cfg(PCIE4W), 389 mc_make_sid_override_cfg(PCIE5R), 390 mc_make_sid_override_cfg(PCIE5W), 391 mc_make_sid_override_cfg(ISPFALW), 392 mc_make_sid_override_cfg(DLA0RDA1), 393 mc_make_sid_override_cfg(DLA1RDA1), 394 mc_make_sid_override_cfg(PVA0RDA1), 395 mc_make_sid_override_cfg(PVA0RDB1), 396 mc_make_sid_override_cfg(PVA1RDA1), 397 mc_make_sid_override_cfg(PVA1RDB1), 398 mc_make_sid_override_cfg(PCIE5R1), 399 mc_make_sid_override_cfg(NVENCSRD1), 400 mc_make_sid_override_cfg(NVENC1SRD1), 401 mc_make_sid_override_cfg(ISPRA1), 402 mc_make_sid_override_cfg(PCIE0R1), 403 mc_make_sid_override_cfg(MIU0R), 404 mc_make_sid_override_cfg(MIU0W), 405 mc_make_sid_override_cfg(MIU1R), 406 mc_make_sid_override_cfg(MIU1W), 407 mc_make_sid_override_cfg(MIU2R), 408 mc_make_sid_override_cfg(MIU2W), 409 mc_make_sid_override_cfg(MIU3R), 410 mc_make_sid_override_cfg(MIU3W), 411 mc_smmu_bypass_cfg, /* TBU settings */ 412 _END_OF_TABLE_, 413 }; 414 415 /******************************************************************************* 416 * Handler to return the pointer to the MC's context struct 417 ******************************************************************************/ 418 static mc_regs_t *tegra194_get_mc_system_suspend_ctx(void) 419 { 420 /* index of _END_OF_TABLE_ */ 421 tegra194_mc_context[0].val = (uint32_t)ARRAY_SIZE(tegra194_mc_context) - 1U; 422 423 return tegra194_mc_context; 424 } 425 426 /******************************************************************************* 427 * Struct to hold the memory controller settings 428 ******************************************************************************/ 429 static tegra_mc_settings_t tegra194_mc_settings = { 430 .streamid_security_cfg = tegra194_streamid_sec_cfgs, 431 .num_streamid_security_cfgs = (uint32_t)ARRAY_SIZE(tegra194_streamid_sec_cfgs), 432 .get_mc_system_suspend_ctx = tegra194_get_mc_system_suspend_ctx 433 }; 434 435 /******************************************************************************* 436 * Handler to return the pointer to the memory controller's settings struct 437 ******************************************************************************/ 438 tegra_mc_settings_t *tegra_get_mc_settings(void) 439 { 440 return &tegra194_mc_settings; 441 } 442 443 /******************************************************************************* 444 * Handler to program the scratch registers with TZDRAM settings for the 445 * resume firmware 446 ******************************************************************************/ 447 void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes) 448 { 449 uint32_t sec_reg_ctrl = tegra_mc_read_32(MC_SECURITY_CFG_REG_CTRL_0); 450 451 /* 452 * Check TZDRAM carveout register access status. Setup TZDRAM fence 453 * only if access is enabled. 454 */ 455 if ((sec_reg_ctrl & SECURITY_CFG_WRITE_ACCESS_BIT) == 456 SECURITY_CFG_WRITE_ACCESS_ENABLE) { 457 458 /* 459 * Setup the Memory controller to allow only secure accesses to 460 * the TZDRAM carveout 461 */ 462 INFO("Configuring TrustZone DRAM Memory Carveout\n"); 463 464 tegra_mc_write_32(MC_SECURITY_CFG0_0, (uint32_t)phys_base); 465 tegra_mc_write_32(MC_SECURITY_CFG3_0, (uint32_t)(phys_base >> 32)); 466 tegra_mc_write_32(MC_SECURITY_CFG1_0, (uint32_t)(size_in_bytes >> 20)); 467 468 /* 469 * MCE propagates the security configuration values across the 470 * CCPLEX. 471 */ 472 (void)mce_update_gsc_tzdram(); 473 } 474 } 475