1719fdb6eSVarun Wadekar /* 2c766adceSPritesh Raithatha * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. 3719fdb6eSVarun Wadekar * 4719fdb6eSVarun Wadekar * SPDX-License-Identifier: BSD-3-Clause 5719fdb6eSVarun Wadekar */ 6719fdb6eSVarun Wadekar 7f32e8525SVarun Wadekar #include <assert.h> 8f32e8525SVarun Wadekar #include <common/bl_common.h> 9f32e8525SVarun Wadekar #include <mce.h> 10719fdb6eSVarun Wadekar #include <memctrl_v2.h> 11f32e8525SVarun Wadekar #include <tegra_mc_def.h> 12f32e8525SVarun Wadekar #include <tegra_platform.h> 13719fdb6eSVarun Wadekar 14719fdb6eSVarun Wadekar /******************************************************************************* 15719fdb6eSVarun Wadekar * Array to hold stream_id override config register offsets 16719fdb6eSVarun Wadekar ******************************************************************************/ 17719fdb6eSVarun Wadekar const static uint32_t tegra194_streamid_override_regs[] = { 18719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_HDAR, 19719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR, 20719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_NVENCSRD, 21719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_SATAR, 22719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_NVENCSWR, 23719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_HDAW, 24719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_SATAW, 25719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_ISPRA, 26719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_ISPFALR, 27719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_ISPWA, 28719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_ISPWB, 29719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR, 30719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW, 31719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR, 32719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW, 33719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_TSECSRD, 34719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_TSECSWR, 35719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_SDMMCRA, 36719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_SDMMCR, 37719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_SDMMCRAB, 38719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_SDMMCWA, 39719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_SDMMCW, 40719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_SDMMCWAB, 41719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_VICSRD, 42719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_VICSWR, 43719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_VIW, 44719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_NVDECSRD, 45719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_NVDECSWR, 46719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_APER, 47719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_APEW, 48719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_NVJPGSRD, 49719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_NVJPGSWR, 50719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_SESRD, 51719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_SESWR, 52719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_AXIAPR, 53719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_AXIAPW, 54719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_ETRR, 55719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_ETRW, 56719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_TSECSRDB, 57719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_TSECSWRB, 58719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_AXISR, 59719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_AXISW, 60719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_EQOSR, 61719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_EQOSW, 62719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_UFSHCR, 63719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_UFSHCW, 64719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR, 65719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_BPMPR, 66719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_BPMPW, 67719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_BPMPDMAR, 68719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_BPMPDMAW, 69719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_AONR, 70719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_AONW, 71719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_AONDMAR, 72719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_AONDMAW, 73719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_SCER, 74719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_SCEW, 75719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_SCEDMAR, 76719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_SCEDMAW, 77719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_APEDMAR, 78719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_APEDMAW, 79719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1, 80719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_VICSRD1, 81719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_NVDECSRD1, 82719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_VIFALR, 83719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_VIFALW, 84719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_DLA0RDA, 85719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_DLA0FALRDB, 86719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_DLA0WRA, 87719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_DLA0FALWRB, 88719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_DLA1RDA, 89719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_DLA1FALRDB, 90719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_DLA1WRA, 91719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_DLA1FALWRB, 92719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PVA0RDA, 93719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PVA0RDB, 94719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PVA0RDC, 95719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PVA0WRA, 96719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PVA0WRB, 97719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PVA0WRC, 98719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PVA1RDA, 99719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PVA1RDB, 100719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PVA1RDC, 101719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PVA1WRA, 102719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PVA1WRB, 103719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PVA1WRC, 104719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_RCER, 105719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_RCEW, 106719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_RCEDMAR, 107719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_RCEDMAW, 108719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_NVENC1SRD, 109719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_NVENC1SWR, 110719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PCIE0R, 111719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PCIE0W, 112719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PCIE1R, 113719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PCIE1W, 114719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PCIE2AR, 115719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PCIE2AW, 116719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PCIE3R, 117719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PCIE3W, 118719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PCIE4R, 119719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PCIE4W, 120719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PCIE5R, 121719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PCIE5W, 122719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_ISPFALW, 123719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_DLA0RDA1, 124719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_DLA1RDA1, 125719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PVA0RDA1, 126719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PVA0RDB1, 127719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PVA1RDA1, 128719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PVA1RDB1, 129719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PCIE5R1, 130719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_NVENCSRD1, 131719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_NVENC1SRD1, 132719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_ISPRA1, 133719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_MIU0R, 134719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_MIU0W, 135719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_MIU1R, 136719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_MIU1W, 137719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_MIU2R, 138719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_MIU2W, 139719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_MIU3R, 140719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_MIU3W 141719fdb6eSVarun Wadekar }; 142719fdb6eSVarun Wadekar 143719fdb6eSVarun Wadekar /******************************************************************************* 144719fdb6eSVarun Wadekar * Array to hold the security configs for stream IDs 145719fdb6eSVarun Wadekar ******************************************************************************/ 146719fdb6eSVarun Wadekar const static mc_streamid_security_cfg_t tegra194_streamid_sec_cfgs[] = { 147719fdb6eSVarun Wadekar mc_make_sec_cfg(HDAR, NON_SECURE, OVERRIDE, ENABLE), 148719fdb6eSVarun Wadekar mc_make_sec_cfg(HOST1XDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), 149719fdb6eSVarun Wadekar mc_make_sec_cfg(NVENCSRD, NON_SECURE, NO_OVERRIDE, ENABLE), 150719fdb6eSVarun Wadekar mc_make_sec_cfg(SATAR, NON_SECURE, OVERRIDE, ENABLE), 151719fdb6eSVarun Wadekar mc_make_sec_cfg(NVENCSWR, NON_SECURE, NO_OVERRIDE, ENABLE), 152719fdb6eSVarun Wadekar mc_make_sec_cfg(HDAW, NON_SECURE, OVERRIDE, ENABLE), 153719fdb6eSVarun Wadekar mc_make_sec_cfg(SATAW, NON_SECURE, OVERRIDE, ENABLE), 154719fdb6eSVarun Wadekar mc_make_sec_cfg(ISPRA, NON_SECURE, NO_OVERRIDE, ENABLE), 155719fdb6eSVarun Wadekar mc_make_sec_cfg(ISPFALR, NON_SECURE, NO_OVERRIDE, ENABLE), 156719fdb6eSVarun Wadekar mc_make_sec_cfg(ISPWA, NON_SECURE, NO_OVERRIDE, ENABLE), 157719fdb6eSVarun Wadekar mc_make_sec_cfg(ISPWB, NON_SECURE, NO_OVERRIDE, ENABLE), 158bc019041SAjay Gupta mc_make_sec_cfg(XUSB_HOSTR, NON_SECURE, NO_OVERRIDE, ENABLE), 159bc019041SAjay Gupta mc_make_sec_cfg(XUSB_HOSTW, NON_SECURE, NO_OVERRIDE, ENABLE), 160bc019041SAjay Gupta mc_make_sec_cfg(XUSB_DEVR, NON_SECURE, NO_OVERRIDE, ENABLE), 161bc019041SAjay Gupta mc_make_sec_cfg(XUSB_DEVW, NON_SECURE, NO_OVERRIDE, ENABLE), 162719fdb6eSVarun Wadekar mc_make_sec_cfg(TSECSRD, NON_SECURE, NO_OVERRIDE, ENABLE), 163719fdb6eSVarun Wadekar mc_make_sec_cfg(TSECSWR, NON_SECURE, NO_OVERRIDE, ENABLE), 164719fdb6eSVarun Wadekar mc_make_sec_cfg(SDMMCRA, NON_SECURE, OVERRIDE, ENABLE), 165719fdb6eSVarun Wadekar mc_make_sec_cfg(SDMMCR, NON_SECURE, OVERRIDE, ENABLE), 166719fdb6eSVarun Wadekar mc_make_sec_cfg(SDMMCRAB, NON_SECURE, OVERRIDE, ENABLE), 167719fdb6eSVarun Wadekar mc_make_sec_cfg(SDMMCWA, NON_SECURE, OVERRIDE, ENABLE), 168719fdb6eSVarun Wadekar mc_make_sec_cfg(SDMMCW, NON_SECURE, OVERRIDE, ENABLE), 169719fdb6eSVarun Wadekar mc_make_sec_cfg(SDMMCWAB, NON_SECURE, OVERRIDE, ENABLE), 170719fdb6eSVarun Wadekar mc_make_sec_cfg(VICSRD, NON_SECURE, NO_OVERRIDE, ENABLE), 171719fdb6eSVarun Wadekar mc_make_sec_cfg(VICSWR, NON_SECURE, NO_OVERRIDE, ENABLE), 172719fdb6eSVarun Wadekar mc_make_sec_cfg(VIW, NON_SECURE, NO_OVERRIDE, ENABLE), 173719fdb6eSVarun Wadekar mc_make_sec_cfg(NVDECSRD, NON_SECURE, NO_OVERRIDE, ENABLE), 174719fdb6eSVarun Wadekar mc_make_sec_cfg(NVDECSWR, NON_SECURE, NO_OVERRIDE, ENABLE), 175719fdb6eSVarun Wadekar mc_make_sec_cfg(APER, NON_SECURE, NO_OVERRIDE, ENABLE), 176719fdb6eSVarun Wadekar mc_make_sec_cfg(APEW, NON_SECURE, NO_OVERRIDE, ENABLE), 177719fdb6eSVarun Wadekar mc_make_sec_cfg(NVJPGSRD, NON_SECURE, NO_OVERRIDE, ENABLE), 178719fdb6eSVarun Wadekar mc_make_sec_cfg(NVJPGSWR, NON_SECURE, NO_OVERRIDE, ENABLE), 179719fdb6eSVarun Wadekar mc_make_sec_cfg(SESRD, NON_SECURE, NO_OVERRIDE, ENABLE), 180719fdb6eSVarun Wadekar mc_make_sec_cfg(SESWR, NON_SECURE, NO_OVERRIDE, ENABLE), 181719fdb6eSVarun Wadekar mc_make_sec_cfg(AXIAPR, NON_SECURE, OVERRIDE, ENABLE), 182719fdb6eSVarun Wadekar mc_make_sec_cfg(AXIAPW, NON_SECURE, OVERRIDE, ENABLE), 183719fdb6eSVarun Wadekar mc_make_sec_cfg(ETRR, NON_SECURE, OVERRIDE, ENABLE), 184719fdb6eSVarun Wadekar mc_make_sec_cfg(ETRW, NON_SECURE, OVERRIDE, ENABLE), 185719fdb6eSVarun Wadekar mc_make_sec_cfg(TSECSRDB, NON_SECURE, NO_OVERRIDE, ENABLE), 186719fdb6eSVarun Wadekar mc_make_sec_cfg(TSECSWRB, NON_SECURE, NO_OVERRIDE, ENABLE), 187719fdb6eSVarun Wadekar mc_make_sec_cfg(AXISR, SECURE, NO_OVERRIDE, DISABLE), 188719fdb6eSVarun Wadekar mc_make_sec_cfg(AXISW, SECURE, NO_OVERRIDE, DISABLE), 189719fdb6eSVarun Wadekar mc_make_sec_cfg(EQOSR, NON_SECURE, OVERRIDE, ENABLE), 190719fdb6eSVarun Wadekar mc_make_sec_cfg(EQOSW, NON_SECURE, OVERRIDE, ENABLE), 191719fdb6eSVarun Wadekar mc_make_sec_cfg(UFSHCR, NON_SECURE, OVERRIDE, ENABLE), 192719fdb6eSVarun Wadekar mc_make_sec_cfg(UFSHCW, NON_SECURE, OVERRIDE, ENABLE), 193719fdb6eSVarun Wadekar mc_make_sec_cfg(NVDISPLAYR, NON_SECURE, OVERRIDE, ENABLE), 194719fdb6eSVarun Wadekar mc_make_sec_cfg(BPMPR, NON_SECURE, NO_OVERRIDE, ENABLE), 195719fdb6eSVarun Wadekar mc_make_sec_cfg(BPMPW, NON_SECURE, NO_OVERRIDE, ENABLE), 196719fdb6eSVarun Wadekar mc_make_sec_cfg(BPMPDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), 197719fdb6eSVarun Wadekar mc_make_sec_cfg(BPMPDMAW, NON_SECURE, NO_OVERRIDE, ENABLE), 198719fdb6eSVarun Wadekar mc_make_sec_cfg(AONR, NON_SECURE, NO_OVERRIDE, ENABLE), 199719fdb6eSVarun Wadekar mc_make_sec_cfg(AONW, NON_SECURE, NO_OVERRIDE, ENABLE), 200719fdb6eSVarun Wadekar mc_make_sec_cfg(AONDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), 201719fdb6eSVarun Wadekar mc_make_sec_cfg(AONDMAW, NON_SECURE, NO_OVERRIDE, ENABLE), 202719fdb6eSVarun Wadekar mc_make_sec_cfg(SCER, NON_SECURE, NO_OVERRIDE, ENABLE), 203719fdb6eSVarun Wadekar mc_make_sec_cfg(SCEW, NON_SECURE, NO_OVERRIDE, ENABLE), 204719fdb6eSVarun Wadekar mc_make_sec_cfg(SCEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), 205719fdb6eSVarun Wadekar mc_make_sec_cfg(SCEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE), 206719fdb6eSVarun Wadekar mc_make_sec_cfg(APEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), 207719fdb6eSVarun Wadekar mc_make_sec_cfg(APEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE), 208719fdb6eSVarun Wadekar mc_make_sec_cfg(NVDISPLAYR1, NON_SECURE, OVERRIDE, ENABLE), 209719fdb6eSVarun Wadekar mc_make_sec_cfg(VICSRD1, NON_SECURE, NO_OVERRIDE, ENABLE), 210719fdb6eSVarun Wadekar mc_make_sec_cfg(NVDECSRD1, NON_SECURE, NO_OVERRIDE, ENABLE), 211719fdb6eSVarun Wadekar mc_make_sec_cfg(VIFALR, NON_SECURE, NO_OVERRIDE, ENABLE), 212719fdb6eSVarun Wadekar mc_make_sec_cfg(VIFALW, NON_SECURE, NO_OVERRIDE, ENABLE), 213719fdb6eSVarun Wadekar mc_make_sec_cfg(DLA0RDA, NON_SECURE, NO_OVERRIDE, ENABLE), 214719fdb6eSVarun Wadekar mc_make_sec_cfg(DLA0FALRDB, NON_SECURE, NO_OVERRIDE, ENABLE), 215719fdb6eSVarun Wadekar mc_make_sec_cfg(DLA0WRA, NON_SECURE, NO_OVERRIDE, ENABLE), 216719fdb6eSVarun Wadekar mc_make_sec_cfg(DLA0FALWRB, NON_SECURE, NO_OVERRIDE, ENABLE), 217719fdb6eSVarun Wadekar mc_make_sec_cfg(DLA1RDA, NON_SECURE, NO_OVERRIDE, ENABLE), 218719fdb6eSVarun Wadekar mc_make_sec_cfg(DLA1FALRDB, NON_SECURE, NO_OVERRIDE, ENABLE), 219719fdb6eSVarun Wadekar mc_make_sec_cfg(DLA1WRA, NON_SECURE, NO_OVERRIDE, ENABLE), 220719fdb6eSVarun Wadekar mc_make_sec_cfg(DLA1FALWRB, NON_SECURE, NO_OVERRIDE, ENABLE), 221719fdb6eSVarun Wadekar mc_make_sec_cfg(PVA0RDA, NON_SECURE, NO_OVERRIDE, ENABLE), 222719fdb6eSVarun Wadekar mc_make_sec_cfg(PVA0RDB, NON_SECURE, NO_OVERRIDE, ENABLE), 223719fdb6eSVarun Wadekar mc_make_sec_cfg(PVA0RDC, NON_SECURE, NO_OVERRIDE, ENABLE), 224719fdb6eSVarun Wadekar mc_make_sec_cfg(PVA0WRA, NON_SECURE, NO_OVERRIDE, ENABLE), 225719fdb6eSVarun Wadekar mc_make_sec_cfg(PVA0WRB, NON_SECURE, NO_OVERRIDE, ENABLE), 226719fdb6eSVarun Wadekar mc_make_sec_cfg(PVA0WRC, NON_SECURE, NO_OVERRIDE, ENABLE), 227719fdb6eSVarun Wadekar mc_make_sec_cfg(PVA1RDA, NON_SECURE, NO_OVERRIDE, ENABLE), 228719fdb6eSVarun Wadekar mc_make_sec_cfg(PVA1RDB, NON_SECURE, NO_OVERRIDE, ENABLE), 229719fdb6eSVarun Wadekar mc_make_sec_cfg(PVA1RDC, NON_SECURE, NO_OVERRIDE, ENABLE), 230719fdb6eSVarun Wadekar mc_make_sec_cfg(PVA1WRA, NON_SECURE, NO_OVERRIDE, ENABLE), 231719fdb6eSVarun Wadekar mc_make_sec_cfg(PVA1WRB, NON_SECURE, NO_OVERRIDE, ENABLE), 232719fdb6eSVarun Wadekar mc_make_sec_cfg(PVA1WRC, NON_SECURE, NO_OVERRIDE, ENABLE), 233719fdb6eSVarun Wadekar mc_make_sec_cfg(RCER, NON_SECURE, NO_OVERRIDE, ENABLE), 234719fdb6eSVarun Wadekar mc_make_sec_cfg(RCEW, NON_SECURE, NO_OVERRIDE, ENABLE), 235719fdb6eSVarun Wadekar mc_make_sec_cfg(RCEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), 236719fdb6eSVarun Wadekar mc_make_sec_cfg(RCEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE), 237719fdb6eSVarun Wadekar mc_make_sec_cfg(NVENC1SRD, NON_SECURE, NO_OVERRIDE, ENABLE), 238719fdb6eSVarun Wadekar mc_make_sec_cfg(NVENC1SWR, NON_SECURE, NO_OVERRIDE, ENABLE), 239719fdb6eSVarun Wadekar mc_make_sec_cfg(PCIE0R, NON_SECURE, OVERRIDE, ENABLE), 240719fdb6eSVarun Wadekar mc_make_sec_cfg(PCIE0W, NON_SECURE, OVERRIDE, ENABLE), 241719fdb6eSVarun Wadekar mc_make_sec_cfg(PCIE1R, NON_SECURE, OVERRIDE, ENABLE), 242719fdb6eSVarun Wadekar mc_make_sec_cfg(PCIE1W, NON_SECURE, OVERRIDE, ENABLE), 243719fdb6eSVarun Wadekar mc_make_sec_cfg(PCIE2AR, NON_SECURE, OVERRIDE, ENABLE), 244719fdb6eSVarun Wadekar mc_make_sec_cfg(PCIE2AW, NON_SECURE, OVERRIDE, ENABLE), 245719fdb6eSVarun Wadekar mc_make_sec_cfg(PCIE3R, NON_SECURE, OVERRIDE, ENABLE), 246719fdb6eSVarun Wadekar mc_make_sec_cfg(PCIE3W, NON_SECURE, OVERRIDE, ENABLE), 247719fdb6eSVarun Wadekar mc_make_sec_cfg(PCIE4R, NON_SECURE, OVERRIDE, ENABLE), 248719fdb6eSVarun Wadekar mc_make_sec_cfg(PCIE4W, NON_SECURE, OVERRIDE, ENABLE), 249719fdb6eSVarun Wadekar mc_make_sec_cfg(PCIE5R, NON_SECURE, OVERRIDE, ENABLE), 250719fdb6eSVarun Wadekar mc_make_sec_cfg(PCIE5W, NON_SECURE, OVERRIDE, ENABLE), 251719fdb6eSVarun Wadekar mc_make_sec_cfg(ISPFALW, NON_SECURE, NO_OVERRIDE, ENABLE), 252719fdb6eSVarun Wadekar mc_make_sec_cfg(DLA0RDA1, NON_SECURE, NO_OVERRIDE, ENABLE), 253719fdb6eSVarun Wadekar mc_make_sec_cfg(DLA1RDA1, NON_SECURE, NO_OVERRIDE, ENABLE), 254719fdb6eSVarun Wadekar mc_make_sec_cfg(PVA0RDA1, NON_SECURE, NO_OVERRIDE, ENABLE), 255719fdb6eSVarun Wadekar mc_make_sec_cfg(PVA0RDB1, NON_SECURE, NO_OVERRIDE, ENABLE), 256719fdb6eSVarun Wadekar mc_make_sec_cfg(PVA1RDA1, NON_SECURE, NO_OVERRIDE, ENABLE), 257719fdb6eSVarun Wadekar mc_make_sec_cfg(PVA1RDB1, NON_SECURE, NO_OVERRIDE, ENABLE), 258719fdb6eSVarun Wadekar mc_make_sec_cfg(PCIE5R1, NON_SECURE, OVERRIDE, ENABLE), 259719fdb6eSVarun Wadekar mc_make_sec_cfg(NVENCSRD1, NON_SECURE, NO_OVERRIDE, ENABLE), 260719fdb6eSVarun Wadekar mc_make_sec_cfg(NVENC1SRD1, NON_SECURE, NO_OVERRIDE, ENABLE), 261719fdb6eSVarun Wadekar mc_make_sec_cfg(ISPRA1, NON_SECURE, NO_OVERRIDE, ENABLE), 262719fdb6eSVarun Wadekar mc_make_sec_cfg(MIU0R, NON_SECURE, OVERRIDE, ENABLE), 263719fdb6eSVarun Wadekar mc_make_sec_cfg(MIU0W, NON_SECURE, OVERRIDE, ENABLE), 264719fdb6eSVarun Wadekar mc_make_sec_cfg(MIU1R, NON_SECURE, OVERRIDE, ENABLE), 265719fdb6eSVarun Wadekar mc_make_sec_cfg(MIU1W, NON_SECURE, OVERRIDE, ENABLE), 266719fdb6eSVarun Wadekar mc_make_sec_cfg(MIU2R, NON_SECURE, OVERRIDE, ENABLE), 267719fdb6eSVarun Wadekar mc_make_sec_cfg(MIU2W, NON_SECURE, OVERRIDE, ENABLE), 268719fdb6eSVarun Wadekar mc_make_sec_cfg(MIU3R, NON_SECURE, OVERRIDE, ENABLE), 269719fdb6eSVarun Wadekar mc_make_sec_cfg(MIU3W, NON_SECURE, OVERRIDE, ENABLE), 270719fdb6eSVarun Wadekar }; 271719fdb6eSVarun Wadekar 272f32e8525SVarun Wadekar /* To be called by common memctrl_v2.c */ 273f32e8525SVarun Wadekar static void tegra194_memctrl_reconfig_mss_clients(void) 274f32e8525SVarun Wadekar { 275f32e8525SVarun Wadekar uint32_t reg_val, wdata_0, wdata_1, wdata_2; 276f32e8525SVarun Wadekar 277f32e8525SVarun Wadekar wdata_0 = MC_CLIENT_HOTRESET_CTRL0_HC_FLUSH_ENB | 278f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL0_SATA_FLUSH_ENB | 279f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL0_VIC_FLUSH_ENB | 280f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL0_XUSB_HOST_FLUSH_ENB | 281f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL0_XUSB_DEV_FLUSH_ENB | 282f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL0_TSEC_FLUSH_ENB | 283f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL0_SDMMC3A_FLUSH_ENB; 284f32e8525SVarun Wadekar if (tegra_platform_is_silicon()) { 285f32e8525SVarun Wadekar wdata_0 |= MC_CLIENT_HOTRESET_CTRL0_SDMMC1A_FLUSH_ENB; 286f32e8525SVarun Wadekar } 287f32e8525SVarun Wadekar 288f32e8525SVarun Wadekar tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL0, wdata_0); 289f32e8525SVarun Wadekar 290f32e8525SVarun Wadekar /* Wait for HOTRESET STATUS to indicate FLUSH_DONE */ 291f32e8525SVarun Wadekar do { 292f32e8525SVarun Wadekar reg_val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS0); 293f32e8525SVarun Wadekar } while ((reg_val & wdata_0) != wdata_0); 294f32e8525SVarun Wadekar 295f32e8525SVarun Wadekar wdata_1 = MC_CLIENT_HOTRESET_CTRL1_SDMMC4A_FLUSH_ENB | 296f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL1_SE_FLUSH_ENB | 297f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL1_ETR_FLUSH_ENB | 298f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL1_TSECB_FLUSH_ENB| 299f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL1_AXIS_FLUSH_ENB | 300f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL1_UFSHC_FLUSH_ENB | 301f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL1_NVDISPLAY_FLUSH_ENB | 302f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL1_BPMP_FLUSH_ENB | 303f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL1_AON_FLUSH_ENB | 304f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL1_SCE_FLUSH_ENB | 305f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL1_VIFAL_FLUSH_ENB; 306f32e8525SVarun Wadekar if (tegra_platform_is_silicon()) { 307f32e8525SVarun Wadekar wdata_1 |= MC_CLIENT_HOTRESET_CTRL1_APE_FLUSH_ENB | 308f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL1_EQOS_FLUSH_ENB | 309f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL1_RCE_FLUSH_ENB; 310f32e8525SVarun Wadekar } 311f32e8525SVarun Wadekar tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL1, wdata_1); 312f32e8525SVarun Wadekar /* Wait for HOTRESET STATUS to indicate FLUSH_DONE */ 313f32e8525SVarun Wadekar do { 314f32e8525SVarun Wadekar reg_val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS1); 315f32e8525SVarun Wadekar } while ((reg_val & wdata_1) != wdata_1); 316f32e8525SVarun Wadekar 317f32e8525SVarun Wadekar wdata_2 = MC_CLIENT_HOTRESET_CTRL2_PCIE_FLUSH_ENB | 318f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL2_AONDMA_FLUSH_ENB | 319f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL2_BPMPDMA_FLUSH_ENB | 320f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL2_SCEDMA_FLUSH_ENB; 321f32e8525SVarun Wadekar if (tegra_platform_is_silicon()) { 322f32e8525SVarun Wadekar wdata_2 |= MC_CLIENT_HOTRESET_CTRL2_RCEDMA_FLUSH_ENB | 323f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL2_PCIE_FLUSH_ENB | 324f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL2_PCIE5A_FLUSH_ENB | 325f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL2_PCIE3A_FLUSH_ENB | 326f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL2_PCIE3_FLUSH_ENB | 327f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL2_PCIE0A_FLUSH_ENB | 328f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL2_PCIE0A2_FLUSH_ENB | 329f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL2_PCIE4A_FLUSH_ENB; 330f32e8525SVarun Wadekar } 331f32e8525SVarun Wadekar tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL2, wdata_2); 332f32e8525SVarun Wadekar /* Wait for HOTRESET STATUS to indicate FLUSH_DONE */ 333f32e8525SVarun Wadekar do { 334f32e8525SVarun Wadekar reg_val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS2); 335f32e8525SVarun Wadekar } while ((reg_val & wdata_2) != wdata_2); 336f32e8525SVarun Wadekar 337f32e8525SVarun Wadekar /* 338f32e8525SVarun Wadekar * Change MEMTYPE_OVERRIDE from SO_DEV -> PASSTHRU for boot and 339f32e8525SVarun Wadekar * strongly ordered MSS clients. 340f32e8525SVarun Wadekar * 341f32e8525SVarun Wadekar * MC clients with default SO_DEV override still enabled at TSA: 342f32e8525SVarun Wadekar * EQOSW, SATAW, XUSB_DEVW, XUSB_HOSTW, PCIe0w, PCIe1w, PCIe2w, 343f32e8525SVarun Wadekar * PCIe3w, PCIe4w and PCIe5w. 344f32e8525SVarun Wadekar */ 345f32e8525SVarun Wadekar mc_set_tsa_w_passthrough(AONDMAW); 346f32e8525SVarun Wadekar mc_set_tsa_w_passthrough(AONW); 347f32e8525SVarun Wadekar mc_set_tsa_w_passthrough(APEDMAW); 348f32e8525SVarun Wadekar mc_set_tsa_w_passthrough(APEW); 349f32e8525SVarun Wadekar mc_set_tsa_w_passthrough(AXISW); 350f32e8525SVarun Wadekar mc_set_tsa_w_passthrough(BPMPDMAW); 351f32e8525SVarun Wadekar mc_set_tsa_w_passthrough(BPMPW); 3521296da6dSPuneet Saxena mc_set_tsa_w_passthrough(EQOSW); 353f32e8525SVarun Wadekar mc_set_tsa_w_passthrough(ETRW); 354f32e8525SVarun Wadekar mc_set_tsa_w_passthrough(RCEDMAW); 355f32e8525SVarun Wadekar mc_set_tsa_w_passthrough(RCEW); 3561296da6dSPuneet Saxena mc_set_tsa_w_passthrough(SCEDMAW); 3571296da6dSPuneet Saxena mc_set_tsa_w_passthrough(SCEW); 358f32e8525SVarun Wadekar mc_set_tsa_w_passthrough(SDMMCW); 359f32e8525SVarun Wadekar mc_set_tsa_w_passthrough(SDMMCWA); 360f32e8525SVarun Wadekar mc_set_tsa_w_passthrough(SDMMCWAB); 36121e22fe3SPuneet Saxena mc_set_tsa_w_passthrough(SESWR); 362f32e8525SVarun Wadekar mc_set_tsa_w_passthrough(TSECSWR); 363f32e8525SVarun Wadekar mc_set_tsa_w_passthrough(TSECSWRB); 364f32e8525SVarun Wadekar mc_set_tsa_w_passthrough(UFSHCW); 365f32e8525SVarun Wadekar mc_set_tsa_w_passthrough(VICSWR); 366f32e8525SVarun Wadekar mc_set_tsa_w_passthrough(VIFALW); 3671296da6dSPuneet Saxena /* 3681296da6dSPuneet Saxena * set HUB2 as SO_DEV_HUBID 3691296da6dSPuneet Saxena */ 3701296da6dSPuneet Saxena reg_val = tsa_read_32(PCIE0W); 3711296da6dSPuneet Saxena mc_set_tsa_hub2(reg_val, PCIE0W); 3721296da6dSPuneet Saxena reg_val = tsa_read_32(PCIE1W); 3731296da6dSPuneet Saxena mc_set_tsa_hub2(reg_val, PCIE1W); 3741296da6dSPuneet Saxena reg_val = tsa_read_32(PCIE2AW); 3751296da6dSPuneet Saxena mc_set_tsa_hub2(reg_val, PCIE2AW); 3761296da6dSPuneet Saxena reg_val = tsa_read_32(PCIE3W); 3771296da6dSPuneet Saxena mc_set_tsa_hub2(reg_val, PCIE3W); 3781296da6dSPuneet Saxena reg_val = tsa_read_32(PCIE4W); 3791296da6dSPuneet Saxena mc_set_tsa_hub2(reg_val, PCIE4W); 3801296da6dSPuneet Saxena reg_val = tsa_read_32(SATAW); 3811296da6dSPuneet Saxena mc_set_tsa_hub2(reg_val, SATAW); 3821296da6dSPuneet Saxena reg_val = tsa_read_32(XUSB_DEVW); 3831296da6dSPuneet Saxena mc_set_tsa_hub2(reg_val, XUSB_DEVW); 3841296da6dSPuneet Saxena reg_val = tsa_read_32(XUSB_HOSTW); 3851296da6dSPuneet Saxena mc_set_tsa_hub2(reg_val, XUSB_HOSTW); 386f32e8525SVarun Wadekar 387f32e8525SVarun Wadekar /* Ordered MC Clients on Xavier are EQOS, SATA, XUSB, PCIe1 and PCIe3 388f32e8525SVarun Wadekar * ISO clients(DISP, VI, EQOS) should never snoop caches and 389f32e8525SVarun Wadekar * don't need ROC/PCFIFO ordering. 390f32e8525SVarun Wadekar * ISO clients(EQOS) that need ordering should use PCFIFO ordering 391f32e8525SVarun Wadekar * and bypass ROC ordering by using FORCE_NON_COHERENT path. 392f32e8525SVarun Wadekar * FORCE_NON_COHERENT/FORCE_COHERENT config take precedence 393f32e8525SVarun Wadekar * over SMMU attributes. 394f32e8525SVarun Wadekar * Force all Normal memory transactions from ISO and non-ISO to be 395f32e8525SVarun Wadekar * non-coherent(bypass ROC, avoid cache snoop to avoid perf hit). 396f32e8525SVarun Wadekar * Force the SO_DEV transactions from ordered ISO clients(EQOS) to 397f32e8525SVarun Wadekar * non-coherent path and enable MC PCFIFO interlock for ordering. 398f32e8525SVarun Wadekar * Force the SO_DEV transactions from ordered non-ISO clients (PCIe, 399f32e8525SVarun Wadekar * XUSB, SATA) to coherent so that the transactions are 400f32e8525SVarun Wadekar * ordered by ROC. 401f32e8525SVarun Wadekar * PCFIFO ensure write ordering. 402f32e8525SVarun Wadekar * Read after Write ordering is maintained/enforced by MC clients. 403f32e8525SVarun Wadekar * Clients that need PCIe type write ordering must 404f32e8525SVarun Wadekar * go through ROC ordering. 405f32e8525SVarun Wadekar * Ordering enable for Read clients is not necessary. 406f32e8525SVarun Wadekar * R5's and A9 would get necessary ordering from AXI and 407f32e8525SVarun Wadekar * don't need ROC ordering enable: 408f32e8525SVarun Wadekar * - MMIO ordering is through dev mapping and MMIO 409f32e8525SVarun Wadekar * accesses bypass SMMU. 410f32e8525SVarun Wadekar * - Normal memory is accessed through SMMU and ordering is 411f32e8525SVarun Wadekar * ensured by client and AXI. 412f32e8525SVarun Wadekar * - Ack point for Normal memory is WCAM in MC. 413f32e8525SVarun Wadekar * - MMIO's can be early acked and AXI ensures dev memory ordering, 414f32e8525SVarun Wadekar * Client ensures read/write direction change ordering. 415f32e8525SVarun Wadekar * - See Bug 200312466 for more details. 416f32e8525SVarun Wadekar */ 41790dce0f9SPritesh Raithatha mc_set_txn_override(AONDMAR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 41890dce0f9SPritesh Raithatha mc_set_txn_override(AONDMAW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 41990dce0f9SPritesh Raithatha mc_set_txn_override(AONR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 42090dce0f9SPritesh Raithatha mc_set_txn_override(AONW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 42190dce0f9SPritesh Raithatha mc_set_txn_override(APEDMAR, CGID_TAG_ADR, SO_DEV_CLIENT_AXI_ID, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 42290dce0f9SPritesh Raithatha mc_set_txn_override(APEDMAW, CGID_TAG_ADR, SO_DEV_CLIENT_AXI_ID, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 42390dce0f9SPritesh Raithatha mc_set_txn_override(APER, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 42490dce0f9SPritesh Raithatha mc_set_txn_override(APEW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 42590dce0f9SPritesh Raithatha mc_set_txn_override(AXISR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 42690dce0f9SPritesh Raithatha mc_set_txn_override(AXISW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 42790dce0f9SPritesh Raithatha mc_set_txn_override(BPMPDMAR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 42890dce0f9SPritesh Raithatha mc_set_txn_override(BPMPDMAW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 42990dce0f9SPritesh Raithatha mc_set_txn_override(BPMPR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 43090dce0f9SPritesh Raithatha mc_set_txn_override(BPMPW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 43190dce0f9SPritesh Raithatha mc_set_txn_override(EQOSR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 43290dce0f9SPritesh Raithatha mc_set_txn_override(EQOSW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 43390dce0f9SPritesh Raithatha mc_set_txn_override(ETRR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 43490dce0f9SPritesh Raithatha mc_set_txn_override(ETRW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 43590dce0f9SPritesh Raithatha mc_set_txn_override(HOST1XDMAR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 436*eb41fee4SPritesh Raithatha mc_set_txn_override(MPCORER, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 437*eb41fee4SPritesh Raithatha mc_set_txn_override(MPCOREW, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 43890dce0f9SPritesh Raithatha mc_set_txn_override(NVDISPLAYR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 43990dce0f9SPritesh Raithatha mc_set_txn_override(NVDISPLAYR1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 44090dce0f9SPritesh Raithatha mc_set_txn_override(PCIE0R, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); 44190dce0f9SPritesh Raithatha mc_set_txn_override(PCIE0R1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); 44290dce0f9SPritesh Raithatha mc_set_txn_override(PCIE0W, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); 44390dce0f9SPritesh Raithatha mc_set_txn_override(PCIE1R, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); 44490dce0f9SPritesh Raithatha mc_set_txn_override(PCIE1W, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); 4451296da6dSPuneet Saxena if (tegra_platform_is_silicon()) { 44690dce0f9SPritesh Raithatha mc_set_txn_override(PCIE2AR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); 44790dce0f9SPritesh Raithatha mc_set_txn_override(PCIE2AW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); 44890dce0f9SPritesh Raithatha mc_set_txn_override(PCIE3R, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); 44990dce0f9SPritesh Raithatha mc_set_txn_override(PCIE3W, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); 45090dce0f9SPritesh Raithatha mc_set_txn_override(PCIE4R, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); 45190dce0f9SPritesh Raithatha mc_set_txn_override(PCIE4W, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); 45290dce0f9SPritesh Raithatha mc_set_txn_override(PCIE5R, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); 45390dce0f9SPritesh Raithatha mc_set_txn_override(PCIE5W, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); 45490dce0f9SPritesh Raithatha mc_set_txn_override(PCIE5R1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); 4551296da6dSPuneet Saxena } 456*eb41fee4SPritesh Raithatha mc_set_txn_override(PTCR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 45790dce0f9SPritesh Raithatha mc_set_txn_override(RCEDMAR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 45890dce0f9SPritesh Raithatha mc_set_txn_override(RCEDMAW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 45990dce0f9SPritesh Raithatha mc_set_txn_override(RCER, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 46090dce0f9SPritesh Raithatha mc_set_txn_override(RCEW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 46190dce0f9SPritesh Raithatha mc_set_txn_override(SATAR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); 46290dce0f9SPritesh Raithatha mc_set_txn_override(SATAW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); 46390dce0f9SPritesh Raithatha mc_set_txn_override(SCEDMAR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 46490dce0f9SPritesh Raithatha mc_set_txn_override(SCEDMAW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 46590dce0f9SPritesh Raithatha mc_set_txn_override(SCER, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 46690dce0f9SPritesh Raithatha mc_set_txn_override(SCEW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 46790dce0f9SPritesh Raithatha mc_set_txn_override(SDMMCR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 46890dce0f9SPritesh Raithatha mc_set_txn_override(SDMMCRAB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 46990dce0f9SPritesh Raithatha mc_set_txn_override(SDMMCRA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 47090dce0f9SPritesh Raithatha mc_set_txn_override(SDMMCW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 47190dce0f9SPritesh Raithatha mc_set_txn_override(SDMMCWA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 47290dce0f9SPritesh Raithatha mc_set_txn_override(SDMMCWAB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 47321e22fe3SPuneet Saxena /* 47421e22fe3SPuneet Saxena * TO DO: make SESRD/WR FORCE_COHERENT once SE+TZ with SMMU is enabled. 47521e22fe3SPuneet Saxena */ 47690dce0f9SPritesh Raithatha mc_set_txn_override(SESRD, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); 47790dce0f9SPritesh Raithatha mc_set_txn_override(SESWR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); 47890dce0f9SPritesh Raithatha mc_set_txn_override(TSECSRD, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 47990dce0f9SPritesh Raithatha mc_set_txn_override(TSECSRDB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 48090dce0f9SPritesh Raithatha mc_set_txn_override(TSECSWR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 48190dce0f9SPritesh Raithatha mc_set_txn_override(TSECSWRB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 48290dce0f9SPritesh Raithatha mc_set_txn_override(UFSHCR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 48390dce0f9SPritesh Raithatha mc_set_txn_override(UFSHCW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 48490dce0f9SPritesh Raithatha mc_set_txn_override(VICSRD, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 48590dce0f9SPritesh Raithatha mc_set_txn_override(VICSRD1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 48690dce0f9SPritesh Raithatha mc_set_txn_override(VICSWR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 48790dce0f9SPritesh Raithatha mc_set_txn_override(VIFALR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 48890dce0f9SPritesh Raithatha mc_set_txn_override(VIFALW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 48990dce0f9SPritesh Raithatha mc_set_txn_override(XUSB_DEVR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); 49090dce0f9SPritesh Raithatha mc_set_txn_override(XUSB_DEVW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); 49190dce0f9SPritesh Raithatha mc_set_txn_override(XUSB_HOSTR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); 49290dce0f9SPritesh Raithatha mc_set_txn_override(XUSB_HOSTW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); 49390dce0f9SPritesh Raithatha mc_set_txn_override(AXIAPR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 49490dce0f9SPritesh Raithatha mc_set_txn_override(AXIAPW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 49590dce0f9SPritesh Raithatha mc_set_txn_override(DLA0FALRDB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 49690dce0f9SPritesh Raithatha mc_set_txn_override(DLA0FALWRB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 49790dce0f9SPritesh Raithatha mc_set_txn_override(DLA0RDA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 49890dce0f9SPritesh Raithatha mc_set_txn_override(DLA0RDA1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 49990dce0f9SPritesh Raithatha mc_set_txn_override(DLA0WRA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 50090dce0f9SPritesh Raithatha mc_set_txn_override(DLA1FALRDB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 50190dce0f9SPritesh Raithatha mc_set_txn_override(DLA1FALWRB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 50290dce0f9SPritesh Raithatha mc_set_txn_override(DLA1RDA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 50390dce0f9SPritesh Raithatha mc_set_txn_override(DLA1RDA1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 50490dce0f9SPritesh Raithatha mc_set_txn_override(DLA1WRA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 50590dce0f9SPritesh Raithatha mc_set_txn_override(HDAR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 50690dce0f9SPritesh Raithatha mc_set_txn_override(HDAW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 50790dce0f9SPritesh Raithatha mc_set_txn_override(ISPFALR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 50890dce0f9SPritesh Raithatha mc_set_txn_override(ISPFALW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 50990dce0f9SPritesh Raithatha mc_set_txn_override(ISPRA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 51090dce0f9SPritesh Raithatha mc_set_txn_override(ISPRA1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 51190dce0f9SPritesh Raithatha mc_set_txn_override(ISPWA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 51290dce0f9SPritesh Raithatha mc_set_txn_override(ISPWB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 51390dce0f9SPritesh Raithatha mc_set_txn_override(NVDEC1SRD, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 51490dce0f9SPritesh Raithatha mc_set_txn_override(NVDEC1SRD1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 51590dce0f9SPritesh Raithatha mc_set_txn_override(NVDEC1SWR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 51690dce0f9SPritesh Raithatha mc_set_txn_override(NVDECSRD, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 51790dce0f9SPritesh Raithatha mc_set_txn_override(NVDECSRD1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 51890dce0f9SPritesh Raithatha mc_set_txn_override(NVDECSWR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 51990dce0f9SPritesh Raithatha mc_set_txn_override(NVENC1SRD, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 52090dce0f9SPritesh Raithatha mc_set_txn_override(NVENC1SRD1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 52190dce0f9SPritesh Raithatha mc_set_txn_override(NVENC1SWR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 52290dce0f9SPritesh Raithatha mc_set_txn_override(NVENCSRD, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 52390dce0f9SPritesh Raithatha mc_set_txn_override(NVENCSRD1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 52490dce0f9SPritesh Raithatha mc_set_txn_override(NVENCSWR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 52590dce0f9SPritesh Raithatha mc_set_txn_override(NVJPGSRD, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 52690dce0f9SPritesh Raithatha mc_set_txn_override(NVJPGSWR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 52790dce0f9SPritesh Raithatha mc_set_txn_override(PVA0RDA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 52890dce0f9SPritesh Raithatha mc_set_txn_override(PVA0RDA1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 52990dce0f9SPritesh Raithatha mc_set_txn_override(PVA0RDB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 53090dce0f9SPritesh Raithatha mc_set_txn_override(PVA0RDB1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 53190dce0f9SPritesh Raithatha mc_set_txn_override(PVA0RDC, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 53290dce0f9SPritesh Raithatha mc_set_txn_override(PVA0WRA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 53390dce0f9SPritesh Raithatha mc_set_txn_override(PVA0WRB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 53490dce0f9SPritesh Raithatha mc_set_txn_override(PVA0WRC, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 53590dce0f9SPritesh Raithatha mc_set_txn_override(PVA1RDA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 53690dce0f9SPritesh Raithatha mc_set_txn_override(PVA1RDA1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 53790dce0f9SPritesh Raithatha mc_set_txn_override(PVA1RDB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 53890dce0f9SPritesh Raithatha mc_set_txn_override(PVA1RDB1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 53990dce0f9SPritesh Raithatha mc_set_txn_override(PVA1RDC, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 54090dce0f9SPritesh Raithatha mc_set_txn_override(PVA1WRA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 54190dce0f9SPritesh Raithatha mc_set_txn_override(PVA1WRB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 54290dce0f9SPritesh Raithatha mc_set_txn_override(PVA1WRC, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); 54390dce0f9SPritesh Raithatha mc_set_txn_override(VIW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 5441296da6dSPuneet Saxena 545*eb41fee4SPritesh Raithatha if (tegra_platform_is_silicon()) { 546*eb41fee4SPritesh Raithatha mc_set_txn_override(MIU0R, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 547*eb41fee4SPritesh Raithatha mc_set_txn_override(MIU0W, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 548*eb41fee4SPritesh Raithatha mc_set_txn_override(MIU1R, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 549*eb41fee4SPritesh Raithatha mc_set_txn_override(MIU1W, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 550*eb41fee4SPritesh Raithatha mc_set_txn_override(MIU2R, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 551*eb41fee4SPritesh Raithatha mc_set_txn_override(MIU2W, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 552*eb41fee4SPritesh Raithatha mc_set_txn_override(MIU3R, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 553*eb41fee4SPritesh Raithatha mc_set_txn_override(MIU3W, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 554*eb41fee4SPritesh Raithatha mc_set_txn_override(MIU4R, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 555*eb41fee4SPritesh Raithatha mc_set_txn_override(MIU4W, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 556*eb41fee4SPritesh Raithatha mc_set_txn_override(MIU5R, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 557*eb41fee4SPritesh Raithatha mc_set_txn_override(MIU5W, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 558*eb41fee4SPritesh Raithatha mc_set_txn_override(MIU6R, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 559*eb41fee4SPritesh Raithatha mc_set_txn_override(MIU6W, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 560*eb41fee4SPritesh Raithatha mc_set_txn_override(MIU7R, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 561*eb41fee4SPritesh Raithatha mc_set_txn_override(MIU7W, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 562*eb41fee4SPritesh Raithatha } 563*eb41fee4SPritesh Raithatha 564f32e8525SVarun Wadekar /* 5651296da6dSPuneet Saxena * At this point, ordering can occur at SCF. So, remove PCFIFO's 566f32e8525SVarun Wadekar * control over ordering requests. 567f32e8525SVarun Wadekar * 568f32e8525SVarun Wadekar * Change PCFIFO_*_ORDERED_CLIENT from ORDERED -> UNORDERED for 569f32e8525SVarun Wadekar * boot and strongly ordered MSS clients 570f32e8525SVarun Wadekar */ 571f32e8525SVarun Wadekar reg_val = MC_PCFIFO_CLIENT_CONFIG2_RESET_VAL & 572f32e8525SVarun Wadekar mc_set_pcfifo_unordered_boot_so_mss(2, XUSB_HOSTW) & 573f32e8525SVarun Wadekar mc_set_pcfifo_unordered_boot_so_mss(2, TSECSWR); 574f32e8525SVarun Wadekar tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG2, reg_val); 575f32e8525SVarun Wadekar 576f32e8525SVarun Wadekar reg_val = MC_PCFIFO_CLIENT_CONFIG3_RESET_VAL & 577f32e8525SVarun Wadekar mc_set_pcfifo_unordered_boot_so_mss(3, SDMMCWA) & 578f32e8525SVarun Wadekar mc_set_pcfifo_unordered_boot_so_mss(3, SDMMCW) & 579f32e8525SVarun Wadekar mc_set_pcfifo_unordered_boot_so_mss(3, SDMMCWAB) & 580f32e8525SVarun Wadekar mc_set_pcfifo_unordered_boot_so_mss(3, VICSWR) & 581f32e8525SVarun Wadekar mc_set_pcfifo_unordered_boot_so_mss(3, APEW); 582f32e8525SVarun Wadekar tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG3, reg_val); 583f32e8525SVarun Wadekar 584f32e8525SVarun Wadekar reg_val = MC_PCFIFO_CLIENT_CONFIG4_RESET_VAL & 585f32e8525SVarun Wadekar mc_set_pcfifo_unordered_boot_so_mss(4, SESWR) & 586f32e8525SVarun Wadekar mc_set_pcfifo_unordered_boot_so_mss(4, ETRW) & 587f32e8525SVarun Wadekar mc_set_pcfifo_unordered_boot_so_mss(4, TSECSWRB) & 588f32e8525SVarun Wadekar mc_set_pcfifo_unordered_boot_so_mss(4, AXISW) & 589f32e8525SVarun Wadekar mc_set_pcfifo_unordered_boot_so_mss(4, UFSHCW) & 590f32e8525SVarun Wadekar mc_set_pcfifo_unordered_boot_so_mss(4, BPMPW) & 591f32e8525SVarun Wadekar mc_set_pcfifo_unordered_boot_so_mss(4, BPMPDMAW) & 592f32e8525SVarun Wadekar mc_set_pcfifo_unordered_boot_so_mss(4, AONW) & 593f32e8525SVarun Wadekar mc_set_pcfifo_unordered_boot_so_mss(4, AONDMAW) & 594f32e8525SVarun Wadekar mc_set_pcfifo_unordered_boot_so_mss(4, SCEW) & 595f32e8525SVarun Wadekar mc_set_pcfifo_unordered_boot_so_mss(4, SCEDMAW); 596f32e8525SVarun Wadekar /* EQOSW has PCFIFO order enabled. */ 5971296da6dSPuneet Saxena reg_val |= mc_set_pcfifo_unordered_boot_so_mss(4, EQOSW); 598f32e8525SVarun Wadekar tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG4, reg_val); 599f32e8525SVarun Wadekar 600f32e8525SVarun Wadekar reg_val = MC_PCFIFO_CLIENT_CONFIG5_RESET_VAL & 601f32e8525SVarun Wadekar mc_set_pcfifo_unordered_boot_so_mss(5, APEDMAW) & 602f32e8525SVarun Wadekar mc_set_pcfifo_unordered_boot_so_mss(5, VIFALW); 603f32e8525SVarun Wadekar tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG5, reg_val); 604f32e8525SVarun Wadekar 605f32e8525SVarun Wadekar reg_val = MC_PCFIFO_CLIENT_CONFIG6_RESET_VAL & 606f32e8525SVarun Wadekar mc_set_pcfifo_unordered_boot_so_mss(6, RCEW) & 607f32e8525SVarun Wadekar mc_set_pcfifo_unordered_boot_so_mss(6, RCEDMAW) & 608f32e8525SVarun Wadekar mc_set_pcfifo_unordered_boot_so_mss(6, PCIE0W); 609f32e8525SVarun Wadekar tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG6, reg_val); 610f32e8525SVarun Wadekar 611f32e8525SVarun Wadekar reg_val = MC_PCFIFO_CLIENT_CONFIG7_RESET_VAL & 612f32e8525SVarun Wadekar mc_set_pcfifo_unordered_boot_so_mss(7, PCIE4W) & 613f32e8525SVarun Wadekar mc_set_pcfifo_unordered_boot_so_mss(7, PCIE5W); 614f32e8525SVarun Wadekar tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG7, reg_val); 615f32e8525SVarun Wadekar 616f32e8525SVarun Wadekar /* Set Order Id only for the clients having non zero order id */ 61795f68bc4SKrishna Reddy reg_val = mc_client_order_id(MC_CLIENT_ORDER_ID_9_RESET_VAL, 9, XUSB_HOSTW); 618f32e8525SVarun Wadekar tegra_mc_write_32(MC_CLIENT_ORDER_ID_9, reg_val); 619f32e8525SVarun Wadekar 62095f68bc4SKrishna Reddy reg_val = mc_client_order_id(MC_CLIENT_ORDER_ID_27_RESET_VAL, 27, PCIE0W); 621f32e8525SVarun Wadekar tegra_mc_write_32(MC_CLIENT_ORDER_ID_27, reg_val); 622f32e8525SVarun Wadekar 62395f68bc4SKrishna Reddy reg_val = mc_client_order_id(MC_CLIENT_ORDER_ID_28_RESET_VAL, 28, PCIE4W); 62495f68bc4SKrishna Reddy reg_val = mc_client_order_id(reg_val, 28, PCIE5W); 625f32e8525SVarun Wadekar tegra_mc_write_32(MC_CLIENT_ORDER_ID_28, reg_val); 626f32e8525SVarun Wadekar 627f32e8525SVarun Wadekar /* 628221b8e57SKrishna Reddy * Set VC Id only for the clients having different reset values like 629221b8e57SKrishna Reddy * SDMMCRAB, SDMMCWAB, SESRD, SESWR, TSECSRD,TSECSRDB, TSECSWR and 630221b8e57SKrishna Reddy * TSECSWRB clients 631f32e8525SVarun Wadekar */ 632221b8e57SKrishna Reddy reg_val = mc_hub_vc_id(MC_HUB_PC_VC_ID_0_RESET_VAL, 0, APB); 633f32e8525SVarun Wadekar tegra_mc_write_32(MC_HUB_PC_VC_ID_0, reg_val); 634f32e8525SVarun Wadekar 635f32e8525SVarun Wadekar /* SDMMCRAB and SDMMCWAB clients */ 636221b8e57SKrishna Reddy reg_val = mc_hub_vc_id(MC_HUB_PC_VC_ID_2_RESET_VAL, 2, SD); 637f32e8525SVarun Wadekar tegra_mc_write_32(MC_HUB_PC_VC_ID_2, reg_val); 638f32e8525SVarun Wadekar 639221b8e57SKrishna Reddy reg_val = mc_hub_vc_id(MC_HUB_PC_VC_ID_4_RESET_VAL, 4, NIC); 640f32e8525SVarun Wadekar tegra_mc_write_32(MC_HUB_PC_VC_ID_4, reg_val); 641f32e8525SVarun Wadekar 6421296da6dSPuneet Saxena reg_val = mc_hub_vc_id(MC_HUB_PC_VC_ID_12_RESET_VAL, 12, UFSHCPC2); 6431296da6dSPuneet Saxena tegra_mc_write_32(MC_HUB_PC_VC_ID_12, reg_val); 6441296da6dSPuneet Saxena 645f32e8525SVarun Wadekar wdata_0 = MC_CLIENT_HOTRESET_CTRL0_RESET_VAL; 646f32e8525SVarun Wadekar tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL0, wdata_0); 647f32e8525SVarun Wadekar 648f32e8525SVarun Wadekar wdata_1 = MC_CLIENT_HOTRESET_CTRL1_RESET_VAL; 649f32e8525SVarun Wadekar tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL1, wdata_1); 650f32e8525SVarun Wadekar 651f32e8525SVarun Wadekar wdata_2 = MC_CLIENT_HOTRESET_CTRL2_RESET_VAL; 652f32e8525SVarun Wadekar tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL2, wdata_2); 653c766adceSPritesh Raithatha 654c766adceSPritesh Raithatha reg_val = MC_COALESCE_CTRL_COALESCER_ENABLE; 655c766adceSPritesh Raithatha tegra_mc_write_32(MC_COALESCE_CTRL, reg_val); 656a0cacc95SArto Merilainen 657a0cacc95SArto Merilainen /* 658a0cacc95SArto Merilainen * WAR to hardware bug 1953865: Coalescer must be disabled 659a0cacc95SArto Merilainen * for PVA0RDC and PVA1RDC interfaces. 660a0cacc95SArto Merilainen */ 661a0cacc95SArto Merilainen reg_val = tegra_mc_read_32(MC_COALESCE_CONFIG_6_0); 662a0cacc95SArto Merilainen reg_val &= ~(MC_COALESCE_CONFIG_6_0_PVA0RDC_COALESCER_ENABLED | 663a0cacc95SArto Merilainen MC_COALESCE_CONFIG_6_0_PVA1RDC_COALESCER_ENABLED); 664a0cacc95SArto Merilainen tegra_mc_write_32(MC_COALESCE_CONFIG_6_0, reg_val); 665f32e8525SVarun Wadekar } 666f32e8525SVarun Wadekar 667719fdb6eSVarun Wadekar /******************************************************************************* 668719fdb6eSVarun Wadekar * Struct to hold the memory controller settings 669719fdb6eSVarun Wadekar ******************************************************************************/ 670719fdb6eSVarun Wadekar static tegra_mc_settings_t tegra194_mc_settings = { 671719fdb6eSVarun Wadekar .streamid_override_cfg = tegra194_streamid_override_regs, 672b6533b56SAnthony Zhou .num_streamid_override_cfgs = (uint32_t)ARRAY_SIZE(tegra194_streamid_override_regs), 673719fdb6eSVarun Wadekar .streamid_security_cfg = tegra194_streamid_sec_cfgs, 674b6533b56SAnthony Zhou .num_streamid_security_cfgs = (uint32_t)ARRAY_SIZE(tegra194_streamid_sec_cfgs), 675f32e8525SVarun Wadekar .reconfig_mss_clients = tegra194_memctrl_reconfig_mss_clients 676719fdb6eSVarun Wadekar }; 677719fdb6eSVarun Wadekar 678719fdb6eSVarun Wadekar /******************************************************************************* 679719fdb6eSVarun Wadekar * Handler to return the pointer to the memory controller's settings struct 680719fdb6eSVarun Wadekar ******************************************************************************/ 681719fdb6eSVarun Wadekar tegra_mc_settings_t *tegra_get_mc_settings(void) 682719fdb6eSVarun Wadekar { 683719fdb6eSVarun Wadekar return &tegra194_mc_settings; 684719fdb6eSVarun Wadekar } 6854e697b77SSteven Kao 6864e697b77SSteven Kao /******************************************************************************* 6874e697b77SSteven Kao * Handler to program the scratch registers with TZDRAM settings for the 6884e697b77SSteven Kao * resume firmware 6894e697b77SSteven Kao ******************************************************************************/ 6904e697b77SSteven Kao void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes) 6914e697b77SSteven Kao { 69295397d96SSteven Kao uint32_t sec_reg_ctrl = tegra_mc_read_32(MC_SECURITY_CFG_REG_CTRL_0); 69395397d96SSteven Kao 6944e697b77SSteven Kao /* 69595397d96SSteven Kao * Check TZDRAM carveout register access status. Setup TZDRAM fence 69695397d96SSteven Kao * only if access is enabled. 6974e697b77SSteven Kao */ 69895397d96SSteven Kao if ((sec_reg_ctrl & SECURITY_CFG_WRITE_ACCESS_BIT) == 69995397d96SSteven Kao SECURITY_CFG_WRITE_ACCESS_ENABLE) { 7004e697b77SSteven Kao 7014e697b77SSteven Kao /* 7024e697b77SSteven Kao * Setup the Memory controller to allow only secure accesses to 7034e697b77SSteven Kao * the TZDRAM carveout 7044e697b77SSteven Kao */ 7054e697b77SSteven Kao INFO("Configuring TrustZone DRAM Memory Carveout\n"); 7064e697b77SSteven Kao 7074e697b77SSteven Kao tegra_mc_write_32(MC_SECURITY_CFG0_0, (uint32_t)phys_base); 7084e697b77SSteven Kao tegra_mc_write_32(MC_SECURITY_CFG3_0, (uint32_t)(phys_base >> 32)); 7094e697b77SSteven Kao tegra_mc_write_32(MC_SECURITY_CFG1_0, (uint32_t)(size_in_bytes >> 20)); 7104e697b77SSteven Kao 7114e697b77SSteven Kao /* 7124e697b77SSteven Kao * MCE propagates the security configuration values across the 7134e697b77SSteven Kao * CCPLEX. 7144e697b77SSteven Kao */ 7154e697b77SSteven Kao (void)mce_update_gsc_tzdram(); 7164e697b77SSteven Kao } 7174e697b77SSteven Kao } 718