xref: /rk3399_ARM-atf/plat/nvidia/tegra/soc/t194/plat_memctrl.c (revision a69a30ff238822539104ffc304696cd796685557)

/*
 * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

#include <assert.h>
#include <common/bl_common.h>
#include <mce.h>
#include <memctrl_v2.h>
#include <tegra_mc_def.h>
#include <tegra_platform.h>

/*******************************************************************************
 * Array to hold stream_id override config register offsets
 ******************************************************************************/
const static uint32_t tegra194_streamid_override_regs[] = {
	MC_STREAMID_OVERRIDE_CFG_HDAR,
	MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR,
	MC_STREAMID_OVERRIDE_CFG_NVENCSRD,
	MC_STREAMID_OVERRIDE_CFG_SATAR,
	MC_STREAMID_OVERRIDE_CFG_NVENCSWR,
	MC_STREAMID_OVERRIDE_CFG_HDAW,
	MC_STREAMID_OVERRIDE_CFG_SATAW,
	MC_STREAMID_OVERRIDE_CFG_ISPRA,
	MC_STREAMID_OVERRIDE_CFG_ISPFALR,
	MC_STREAMID_OVERRIDE_CFG_ISPWA,
	MC_STREAMID_OVERRIDE_CFG_ISPWB,
	MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR,
	MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW,
	MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR,
	MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW,
	MC_STREAMID_OVERRIDE_CFG_TSECSRD,
	MC_STREAMID_OVERRIDE_CFG_TSECSWR,
	MC_STREAMID_OVERRIDE_CFG_SDMMCRA,
	MC_STREAMID_OVERRIDE_CFG_SDMMCR,
	MC_STREAMID_OVERRIDE_CFG_SDMMCRAB,
	MC_STREAMID_OVERRIDE_CFG_SDMMCWA,
	MC_STREAMID_OVERRIDE_CFG_SDMMCW,
	MC_STREAMID_OVERRIDE_CFG_SDMMCWAB,
	MC_STREAMID_OVERRIDE_CFG_VICSRD,
	MC_STREAMID_OVERRIDE_CFG_VICSWR,
	MC_STREAMID_OVERRIDE_CFG_VIW,
	MC_STREAMID_OVERRIDE_CFG_NVDECSRD,
	MC_STREAMID_OVERRIDE_CFG_NVDECSWR,
	MC_STREAMID_OVERRIDE_CFG_APER,
	MC_STREAMID_OVERRIDE_CFG_APEW,
	MC_STREAMID_OVERRIDE_CFG_NVJPGSRD,
	MC_STREAMID_OVERRIDE_CFG_NVJPGSWR,
	MC_STREAMID_OVERRIDE_CFG_SESRD,
	MC_STREAMID_OVERRIDE_CFG_SESWR,
	MC_STREAMID_OVERRIDE_CFG_AXIAPR,
	MC_STREAMID_OVERRIDE_CFG_AXIAPW,
	MC_STREAMID_OVERRIDE_CFG_ETRR,
	MC_STREAMID_OVERRIDE_CFG_ETRW,
	MC_STREAMID_OVERRIDE_CFG_TSECSRDB,
	MC_STREAMID_OVERRIDE_CFG_TSECSWRB,
	MC_STREAMID_OVERRIDE_CFG_AXISR,
	MC_STREAMID_OVERRIDE_CFG_AXISW,
	MC_STREAMID_OVERRIDE_CFG_EQOSR,
	MC_STREAMID_OVERRIDE_CFG_EQOSW,
	MC_STREAMID_OVERRIDE_CFG_UFSHCR,
	MC_STREAMID_OVERRIDE_CFG_UFSHCW,
	MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR,
	MC_STREAMID_OVERRIDE_CFG_BPMPR,
	MC_STREAMID_OVERRIDE_CFG_BPMPW,
	MC_STREAMID_OVERRIDE_CFG_BPMPDMAR,
	MC_STREAMID_OVERRIDE_CFG_BPMPDMAW,
	MC_STREAMID_OVERRIDE_CFG_AONR,
	MC_STREAMID_OVERRIDE_CFG_AONW,
	MC_STREAMID_OVERRIDE_CFG_AONDMAR,
	MC_STREAMID_OVERRIDE_CFG_AONDMAW,
	MC_STREAMID_OVERRIDE_CFG_SCER,
	MC_STREAMID_OVERRIDE_CFG_SCEW,
	MC_STREAMID_OVERRIDE_CFG_SCEDMAR,
	MC_STREAMID_OVERRIDE_CFG_SCEDMAW,
	MC_STREAMID_OVERRIDE_CFG_APEDMAR,
	MC_STREAMID_OVERRIDE_CFG_APEDMAW,
	MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1,
	MC_STREAMID_OVERRIDE_CFG_VICSRD1,
	MC_STREAMID_OVERRIDE_CFG_NVDECSRD1,
	MC_STREAMID_OVERRIDE_CFG_VIFALR,
	MC_STREAMID_OVERRIDE_CFG_VIFALW,
	MC_STREAMID_OVERRIDE_CFG_DLA0RDA,
	MC_STREAMID_OVERRIDE_CFG_DLA0FALRDB,
	MC_STREAMID_OVERRIDE_CFG_DLA0WRA,
	MC_STREAMID_OVERRIDE_CFG_DLA0FALWRB,
	MC_STREAMID_OVERRIDE_CFG_DLA1RDA,
	MC_STREAMID_OVERRIDE_CFG_DLA1FALRDB,
	MC_STREAMID_OVERRIDE_CFG_DLA1WRA,
	MC_STREAMID_OVERRIDE_CFG_DLA1FALWRB,
	MC_STREAMID_OVERRIDE_CFG_PVA0RDA,
	MC_STREAMID_OVERRIDE_CFG_PVA0RDB,
	MC_STREAMID_OVERRIDE_CFG_PVA0RDC,
	MC_STREAMID_OVERRIDE_CFG_PVA0WRA,
	MC_STREAMID_OVERRIDE_CFG_PVA0WRB,
	MC_STREAMID_OVERRIDE_CFG_PVA0WRC,
	MC_STREAMID_OVERRIDE_CFG_PVA1RDA,
	MC_STREAMID_OVERRIDE_CFG_PVA1RDB,
	MC_STREAMID_OVERRIDE_CFG_PVA1RDC,
	MC_STREAMID_OVERRIDE_CFG_PVA1WRA,
	MC_STREAMID_OVERRIDE_CFG_PVA1WRB,
	MC_STREAMID_OVERRIDE_CFG_PVA1WRC,
	MC_STREAMID_OVERRIDE_CFG_RCER,
	MC_STREAMID_OVERRIDE_CFG_RCEW,
	MC_STREAMID_OVERRIDE_CFG_RCEDMAR,
	MC_STREAMID_OVERRIDE_CFG_RCEDMAW,
	MC_STREAMID_OVERRIDE_CFG_NVENC1SRD,
	MC_STREAMID_OVERRIDE_CFG_NVENC1SWR,
	MC_STREAMID_OVERRIDE_CFG_PCIE0R,
	MC_STREAMID_OVERRIDE_CFG_PCIE0W,
	MC_STREAMID_OVERRIDE_CFG_PCIE1R,
	MC_STREAMID_OVERRIDE_CFG_PCIE1W,
	MC_STREAMID_OVERRIDE_CFG_PCIE2AR,
	MC_STREAMID_OVERRIDE_CFG_PCIE2AW,
	MC_STREAMID_OVERRIDE_CFG_PCIE3R,
	MC_STREAMID_OVERRIDE_CFG_PCIE3W,
	MC_STREAMID_OVERRIDE_CFG_PCIE4R,
	MC_STREAMID_OVERRIDE_CFG_PCIE4W,
	MC_STREAMID_OVERRIDE_CFG_PCIE5R,
	MC_STREAMID_OVERRIDE_CFG_PCIE5W,
	MC_STREAMID_OVERRIDE_CFG_ISPFALW,
	MC_STREAMID_OVERRIDE_CFG_DLA0RDA1,
	MC_STREAMID_OVERRIDE_CFG_DLA1RDA1,
	MC_STREAMID_OVERRIDE_CFG_PVA0RDA1,
	MC_STREAMID_OVERRIDE_CFG_PVA0RDB1,
	MC_STREAMID_OVERRIDE_CFG_PVA1RDA1,
	MC_STREAMID_OVERRIDE_CFG_PVA1RDB1,
	MC_STREAMID_OVERRIDE_CFG_PCIE5R1,
	MC_STREAMID_OVERRIDE_CFG_NVENCSRD1,
	MC_STREAMID_OVERRIDE_CFG_NVENC1SRD1,
	MC_STREAMID_OVERRIDE_CFG_ISPRA1,
	MC_STREAMID_OVERRIDE_CFG_PCIE0R1,
	MC_STREAMID_OVERRIDE_CFG_MIU0R,
	MC_STREAMID_OVERRIDE_CFG_MIU0W,
	MC_STREAMID_OVERRIDE_CFG_MIU1R,
	MC_STREAMID_OVERRIDE_CFG_MIU1W,
	MC_STREAMID_OVERRIDE_CFG_MIU2R,
	MC_STREAMID_OVERRIDE_CFG_MIU2W,
	MC_STREAMID_OVERRIDE_CFG_MIU3R,
	MC_STREAMID_OVERRIDE_CFG_MIU3W,
	MC_STREAMID_OVERRIDE_CFG_MIU4R,
	MC_STREAMID_OVERRIDE_CFG_MIU4W,
	MC_STREAMID_OVERRIDE_CFG_MIU5R,
	MC_STREAMID_OVERRIDE_CFG_MIU5W
};

/*******************************************************************************
 * Array to hold the security configs for stream IDs
 ******************************************************************************/
const static mc_streamid_security_cfg_t tegra194_streamid_sec_cfgs[] = {
	mc_make_sec_cfg(HDAR, NON_SECURE, OVERRIDE, DISABLE),
	mc_make_sec_cfg(HOST1XDMAR, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(NVENCSRD, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(SATAR, NON_SECURE, OVERRIDE, DISABLE),
	mc_make_sec_cfg(NVENCSWR, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(HDAW, NON_SECURE, OVERRIDE, DISABLE),
	mc_make_sec_cfg(SATAW, NON_SECURE, OVERRIDE, DISABLE),
	mc_make_sec_cfg(ISPRA, NON_SECURE, NO_OVERRIDE, ENABLE),
	mc_make_sec_cfg(ISPFALR, NON_SECURE, NO_OVERRIDE, ENABLE),
	mc_make_sec_cfg(ISPWA, NON_SECURE, NO_OVERRIDE, ENABLE),
	mc_make_sec_cfg(ISPWB, NON_SECURE, NO_OVERRIDE, ENABLE),
	mc_make_sec_cfg(XUSB_HOSTR, NON_SECURE, NO_OVERRIDE, ENABLE),
	mc_make_sec_cfg(XUSB_HOSTW, NON_SECURE, NO_OVERRIDE, ENABLE),
	mc_make_sec_cfg(XUSB_DEVR, NON_SECURE, NO_OVERRIDE, ENABLE),
	mc_make_sec_cfg(XUSB_DEVW, NON_SECURE, NO_OVERRIDE, ENABLE),
	mc_make_sec_cfg(TSECSRD, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(TSECSWR, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(SDMMCRA, NON_SECURE, OVERRIDE, DISABLE),
	mc_make_sec_cfg(SDMMCR, NON_SECURE, OVERRIDE, DISABLE),
	mc_make_sec_cfg(SDMMCRAB, NON_SECURE, OVERRIDE, DISABLE),
	mc_make_sec_cfg(SDMMCWA, NON_SECURE, OVERRIDE, DISABLE),
	mc_make_sec_cfg(SDMMCW, NON_SECURE, OVERRIDE, DISABLE),
	mc_make_sec_cfg(SDMMCWAB, NON_SECURE, OVERRIDE, DISABLE),
	mc_make_sec_cfg(VICSRD, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(VICSWR, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(VIW, NON_SECURE, NO_OVERRIDE, ENABLE),
	mc_make_sec_cfg(NVDECSRD, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(NVDECSWR, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(APER, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(APEW, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(NVJPGSRD, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(NVJPGSWR, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(SESRD, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(SESWR, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(AXIAPR, NON_SECURE, OVERRIDE, DISABLE),
	mc_make_sec_cfg(AXIAPW, NON_SECURE, OVERRIDE, DISABLE),
	mc_make_sec_cfg(ETRR, NON_SECURE, OVERRIDE, DISABLE),
	mc_make_sec_cfg(ETRW, NON_SECURE, OVERRIDE, DISABLE),
	mc_make_sec_cfg(TSECSRDB, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(TSECSWRB, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(AXISR, SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(AXISW, SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(EQOSR, NON_SECURE, OVERRIDE, DISABLE),
	mc_make_sec_cfg(EQOSW, NON_SECURE, OVERRIDE, DISABLE),
	mc_make_sec_cfg(UFSHCR, NON_SECURE, OVERRIDE, DISABLE),
	mc_make_sec_cfg(UFSHCW, NON_SECURE, OVERRIDE, DISABLE),
	mc_make_sec_cfg(NVDISPLAYR, NON_SECURE, OVERRIDE, DISABLE),
	mc_make_sec_cfg(BPMPR, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(BPMPW, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(BPMPDMAR, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(BPMPDMAW, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(AONR, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(AONW, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(AONDMAR, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(AONDMAW, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(SCER, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(SCEW, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(SCEDMAR, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(SCEDMAW, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(APEDMAR, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(APEDMAW, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(NVDISPLAYR1, NON_SECURE, OVERRIDE, DISABLE),
	mc_make_sec_cfg(VICSRD1, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(NVDECSRD1, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(VIFALR, NON_SECURE, NO_OVERRIDE, ENABLE),
	mc_make_sec_cfg(VIFALW, NON_SECURE, NO_OVERRIDE, ENABLE),
	mc_make_sec_cfg(DLA0RDA, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(DLA0FALRDB, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(DLA0WRA, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(DLA0FALWRB, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(DLA1RDA, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(DLA1FALRDB, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(DLA1WRA, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(DLA1FALWRB, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(PVA0RDA, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(PVA0RDB, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(PVA0RDC, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(PVA0WRA, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(PVA0WRB, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(PVA0WRC, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(PVA1RDA, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(PVA1RDB, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(PVA1RDC, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(PVA1WRA, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(PVA1WRB, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(PVA1WRC, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(RCER, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(RCEW, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(RCEDMAR, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(RCEDMAW, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(NVENC1SRD, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(NVENC1SWR, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(PCIE0R, NON_SECURE, OVERRIDE, DISABLE),
	mc_make_sec_cfg(PCIE0W, NON_SECURE, OVERRIDE, DISABLE),
	mc_make_sec_cfg(PCIE1R, NON_SECURE, OVERRIDE, DISABLE),
	mc_make_sec_cfg(PCIE1W, NON_SECURE, OVERRIDE, DISABLE),
	mc_make_sec_cfg(PCIE2AR, NON_SECURE, OVERRIDE, DISABLE),
	mc_make_sec_cfg(PCIE2AW, NON_SECURE, OVERRIDE, DISABLE),
	mc_make_sec_cfg(PCIE3R, NON_SECURE, OVERRIDE, DISABLE),
	mc_make_sec_cfg(PCIE3W, NON_SECURE, OVERRIDE, DISABLE),
	mc_make_sec_cfg(PCIE4R, NON_SECURE, OVERRIDE, DISABLE),
	mc_make_sec_cfg(PCIE4W, NON_SECURE, OVERRIDE, DISABLE),
	mc_make_sec_cfg(PCIE5R, NON_SECURE, OVERRIDE, DISABLE),
	mc_make_sec_cfg(PCIE5W, NON_SECURE, OVERRIDE, DISABLE),
	mc_make_sec_cfg(ISPFALW, NON_SECURE, NO_OVERRIDE, ENABLE),
	mc_make_sec_cfg(DLA0RDA1, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(DLA1RDA1, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(PVA0RDA1, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(PVA0RDB1, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(PVA1RDA1, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(PVA1RDB1, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(PCIE5R1, NON_SECURE, OVERRIDE, DISABLE),
	mc_make_sec_cfg(NVENCSRD1, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(NVENC1SRD1, NON_SECURE, NO_OVERRIDE, DISABLE),
	mc_make_sec_cfg(ISPRA1, NON_SECURE, NO_OVERRIDE, ENABLE),
	mc_make_sec_cfg(PCIE0R1, NON_SECURE, OVERRIDE, DISABLE),
	mc_make_sec_cfg(MIU0R, NON_SECURE, OVERRIDE, DISABLE),
	mc_make_sec_cfg(MIU0W, NON_SECURE, OVERRIDE, DISABLE),
	mc_make_sec_cfg(MIU1R, NON_SECURE, OVERRIDE, DISABLE),
	mc_make_sec_cfg(MIU1W, NON_SECURE, OVERRIDE, DISABLE),
	mc_make_sec_cfg(MIU2R, NON_SECURE, OVERRIDE, DISABLE),
	mc_make_sec_cfg(MIU2W, NON_SECURE, OVERRIDE, DISABLE),
	mc_make_sec_cfg(MIU3R, NON_SECURE, OVERRIDE, DISABLE),
	mc_make_sec_cfg(MIU3W, NON_SECURE, OVERRIDE, DISABLE),
	mc_make_sec_cfg(MIU4R, NON_SECURE, OVERRIDE, DISABLE),
	mc_make_sec_cfg(MIU4W, NON_SECURE, OVERRIDE, DISABLE),
	mc_make_sec_cfg(MIU5R, NON_SECURE, OVERRIDE, DISABLE),
	mc_make_sec_cfg(MIU5W, NON_SECURE, OVERRIDE, DISABLE)
};

/*******************************************************************************
 * Struct to hold the memory controller settings
 ******************************************************************************/
static tegra_mc_settings_t tegra194_mc_settings = {
	.streamid_override_cfg = tegra194_streamid_override_regs,
	.num_streamid_override_cfgs = (uint32_t)ARRAY_SIZE(tegra194_streamid_override_regs),
	.streamid_security_cfg = tegra194_streamid_sec_cfgs,
	.num_streamid_security_cfgs = (uint32_t)ARRAY_SIZE(tegra194_streamid_sec_cfgs)
};

/*******************************************************************************
 * Handler to return the pointer to the memory controller's settings struct
 ******************************************************************************/
tegra_mc_settings_t *tegra_get_mc_settings(void)
{
	return &tegra194_mc_settings;
}

/*******************************************************************************
 * Handler to program the scratch registers with TZDRAM settings for the
 * resume firmware
 ******************************************************************************/
void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes)
{
	uint32_t sec_reg_ctrl = tegra_mc_read_32(MC_SECURITY_CFG_REG_CTRL_0);

	/*
	 * Check TZDRAM carveout register access status. Setup TZDRAM fence
	 * only if access is enabled.
	 */
	if ((sec_reg_ctrl & SECURITY_CFG_WRITE_ACCESS_BIT) ==
	     SECURITY_CFG_WRITE_ACCESS_ENABLE) {

		/*
		 * Setup the Memory controller to allow only secure accesses to
		 * the TZDRAM carveout
		 */
		INFO("Configuring TrustZone DRAM Memory Carveout\n");

		tegra_mc_write_32(MC_SECURITY_CFG0_0, (uint32_t)phys_base);
		tegra_mc_write_32(MC_SECURITY_CFG3_0, (uint32_t)(phys_base >> 32));
		tegra_mc_write_32(MC_SECURITY_CFG1_0, (uint32_t)(size_in_bytes >> 20));

		/*
		 * MCE propagates the security configuration values across the
		 * CCPLEX.
		 */
		(void)mce_update_gsc_tzdram();
	}
}