1719fdb6eSVarun Wadekar /* 2719fdb6eSVarun Wadekar * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. 3719fdb6eSVarun Wadekar * 4719fdb6eSVarun Wadekar * SPDX-License-Identifier: BSD-3-Clause 5719fdb6eSVarun Wadekar */ 6719fdb6eSVarun Wadekar 7f32e8525SVarun Wadekar #include <assert.h> 8f32e8525SVarun Wadekar #include <common/bl_common.h> 9f32e8525SVarun Wadekar #include <mce.h> 10719fdb6eSVarun Wadekar #include <memctrl_v2.h> 11f32e8525SVarun Wadekar #include <tegra_mc_def.h> 12f32e8525SVarun Wadekar #include <tegra_platform.h> 13719fdb6eSVarun Wadekar 14719fdb6eSVarun Wadekar /******************************************************************************* 15719fdb6eSVarun Wadekar * Array to hold stream_id override config register offsets 16719fdb6eSVarun Wadekar ******************************************************************************/ 17719fdb6eSVarun Wadekar const static uint32_t tegra194_streamid_override_regs[] = { 18719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_HDAR, 19719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR, 20719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_NVENCSRD, 21719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_SATAR, 22719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_NVENCSWR, 23719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_HDAW, 24719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_SATAW, 25719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_ISPRA, 26719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_ISPFALR, 27719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_ISPWA, 28719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_ISPWB, 29719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR, 30719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW, 31719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR, 32719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW, 33719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_TSECSRD, 34719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_TSECSWR, 35719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_SDMMCRA, 36719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_SDMMCR, 37719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_SDMMCRAB, 38719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_SDMMCWA, 39719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_SDMMCW, 40719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_SDMMCWAB, 41719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_VICSRD, 42719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_VICSWR, 43719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_VIW, 44719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_NVDECSRD, 45719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_NVDECSWR, 46719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_APER, 47719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_APEW, 48719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_NVJPGSRD, 49719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_NVJPGSWR, 50719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_SESRD, 51719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_SESWR, 52719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_AXIAPR, 53719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_AXIAPW, 54719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_ETRR, 55719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_ETRW, 56719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_TSECSRDB, 57719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_TSECSWRB, 58719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_AXISR, 59719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_AXISW, 60719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_EQOSR, 61719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_EQOSW, 62719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_UFSHCR, 63719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_UFSHCW, 64719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR, 65719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_BPMPR, 66719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_BPMPW, 67719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_BPMPDMAR, 68719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_BPMPDMAW, 69719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_AONR, 70719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_AONW, 71719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_AONDMAR, 72719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_AONDMAW, 73719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_SCER, 74719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_SCEW, 75719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_SCEDMAR, 76719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_SCEDMAW, 77719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_APEDMAR, 78719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_APEDMAW, 79719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1, 80719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_VICSRD1, 81719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_NVDECSRD1, 82719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_VIFALR, 83719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_VIFALW, 84719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_DLA0RDA, 85719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_DLA0FALRDB, 86719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_DLA0WRA, 87719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_DLA0FALWRB, 88719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_DLA1RDA, 89719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_DLA1FALRDB, 90719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_DLA1WRA, 91719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_DLA1FALWRB, 92719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PVA0RDA, 93719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PVA0RDB, 94719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PVA0RDC, 95719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PVA0WRA, 96719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PVA0WRB, 97719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PVA0WRC, 98719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PVA1RDA, 99719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PVA1RDB, 100719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PVA1RDC, 101719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PVA1WRA, 102719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PVA1WRB, 103719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PVA1WRC, 104719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_RCER, 105719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_RCEW, 106719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_RCEDMAR, 107719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_RCEDMAW, 108719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_NVENC1SRD, 109719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_NVENC1SWR, 110719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PCIE0R, 111719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PCIE0W, 112719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PCIE1R, 113719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PCIE1W, 114719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PCIE2AR, 115719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PCIE2AW, 116719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PCIE3R, 117719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PCIE3W, 118719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PCIE4R, 119719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PCIE4W, 120719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PCIE5R, 121719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PCIE5W, 122719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_ISPFALW, 123719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_DLA0RDA1, 124719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_DLA1RDA1, 125719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PVA0RDA1, 126719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PVA0RDB1, 127719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PVA1RDA1, 128719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PVA1RDB1, 129719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PCIE5R1, 130719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_NVENCSRD1, 131719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_NVENC1SRD1, 132719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_ISPRA1, 133719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_MIU0R, 134719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_MIU0W, 135719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_MIU1R, 136719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_MIU1W, 137719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_MIU2R, 138719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_MIU2W, 139719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_MIU3R, 140719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_MIU3W 141719fdb6eSVarun Wadekar }; 142719fdb6eSVarun Wadekar 143719fdb6eSVarun Wadekar /******************************************************************************* 144719fdb6eSVarun Wadekar * Array to hold the security configs for stream IDs 145719fdb6eSVarun Wadekar ******************************************************************************/ 146719fdb6eSVarun Wadekar const static mc_streamid_security_cfg_t tegra194_streamid_sec_cfgs[] = { 147719fdb6eSVarun Wadekar mc_make_sec_cfg(HDAR, NON_SECURE, OVERRIDE, ENABLE), 148719fdb6eSVarun Wadekar mc_make_sec_cfg(HOST1XDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), 149719fdb6eSVarun Wadekar mc_make_sec_cfg(NVENCSRD, NON_SECURE, NO_OVERRIDE, ENABLE), 150719fdb6eSVarun Wadekar mc_make_sec_cfg(SATAR, NON_SECURE, OVERRIDE, ENABLE), 151719fdb6eSVarun Wadekar mc_make_sec_cfg(NVENCSWR, NON_SECURE, NO_OVERRIDE, ENABLE), 152719fdb6eSVarun Wadekar mc_make_sec_cfg(HDAW, NON_SECURE, OVERRIDE, ENABLE), 153719fdb6eSVarun Wadekar mc_make_sec_cfg(SATAW, NON_SECURE, OVERRIDE, ENABLE), 154719fdb6eSVarun Wadekar mc_make_sec_cfg(ISPRA, NON_SECURE, NO_OVERRIDE, ENABLE), 155719fdb6eSVarun Wadekar mc_make_sec_cfg(ISPFALR, NON_SECURE, NO_OVERRIDE, ENABLE), 156719fdb6eSVarun Wadekar mc_make_sec_cfg(ISPWA, NON_SECURE, NO_OVERRIDE, ENABLE), 157719fdb6eSVarun Wadekar mc_make_sec_cfg(ISPWB, NON_SECURE, NO_OVERRIDE, ENABLE), 158bc019041SAjay Gupta mc_make_sec_cfg(XUSB_HOSTR, NON_SECURE, NO_OVERRIDE, ENABLE), 159bc019041SAjay Gupta mc_make_sec_cfg(XUSB_HOSTW, NON_SECURE, NO_OVERRIDE, ENABLE), 160bc019041SAjay Gupta mc_make_sec_cfg(XUSB_DEVR, NON_SECURE, NO_OVERRIDE, ENABLE), 161bc019041SAjay Gupta mc_make_sec_cfg(XUSB_DEVW, NON_SECURE, NO_OVERRIDE, ENABLE), 162719fdb6eSVarun Wadekar mc_make_sec_cfg(TSECSRD, NON_SECURE, NO_OVERRIDE, ENABLE), 163719fdb6eSVarun Wadekar mc_make_sec_cfg(TSECSWR, NON_SECURE, NO_OVERRIDE, ENABLE), 164719fdb6eSVarun Wadekar mc_make_sec_cfg(SDMMCRA, NON_SECURE, OVERRIDE, ENABLE), 165719fdb6eSVarun Wadekar mc_make_sec_cfg(SDMMCR, NON_SECURE, OVERRIDE, ENABLE), 166719fdb6eSVarun Wadekar mc_make_sec_cfg(SDMMCRAB, NON_SECURE, OVERRIDE, ENABLE), 167719fdb6eSVarun Wadekar mc_make_sec_cfg(SDMMCWA, NON_SECURE, OVERRIDE, ENABLE), 168719fdb6eSVarun Wadekar mc_make_sec_cfg(SDMMCW, NON_SECURE, OVERRIDE, ENABLE), 169719fdb6eSVarun Wadekar mc_make_sec_cfg(SDMMCWAB, NON_SECURE, OVERRIDE, ENABLE), 170719fdb6eSVarun Wadekar mc_make_sec_cfg(VICSRD, NON_SECURE, NO_OVERRIDE, ENABLE), 171719fdb6eSVarun Wadekar mc_make_sec_cfg(VICSWR, NON_SECURE, NO_OVERRIDE, ENABLE), 172719fdb6eSVarun Wadekar mc_make_sec_cfg(VIW, NON_SECURE, NO_OVERRIDE, ENABLE), 173719fdb6eSVarun Wadekar mc_make_sec_cfg(NVDECSRD, NON_SECURE, NO_OVERRIDE, ENABLE), 174719fdb6eSVarun Wadekar mc_make_sec_cfg(NVDECSWR, NON_SECURE, NO_OVERRIDE, ENABLE), 175719fdb6eSVarun Wadekar mc_make_sec_cfg(APER, NON_SECURE, NO_OVERRIDE, ENABLE), 176719fdb6eSVarun Wadekar mc_make_sec_cfg(APEW, NON_SECURE, NO_OVERRIDE, ENABLE), 177719fdb6eSVarun Wadekar mc_make_sec_cfg(NVJPGSRD, NON_SECURE, NO_OVERRIDE, ENABLE), 178719fdb6eSVarun Wadekar mc_make_sec_cfg(NVJPGSWR, NON_SECURE, NO_OVERRIDE, ENABLE), 179719fdb6eSVarun Wadekar mc_make_sec_cfg(SESRD, NON_SECURE, NO_OVERRIDE, ENABLE), 180719fdb6eSVarun Wadekar mc_make_sec_cfg(SESWR, NON_SECURE, NO_OVERRIDE, ENABLE), 181719fdb6eSVarun Wadekar mc_make_sec_cfg(AXIAPR, NON_SECURE, OVERRIDE, ENABLE), 182719fdb6eSVarun Wadekar mc_make_sec_cfg(AXIAPW, NON_SECURE, OVERRIDE, ENABLE), 183719fdb6eSVarun Wadekar mc_make_sec_cfg(ETRR, NON_SECURE, OVERRIDE, ENABLE), 184719fdb6eSVarun Wadekar mc_make_sec_cfg(ETRW, NON_SECURE, OVERRIDE, ENABLE), 185719fdb6eSVarun Wadekar mc_make_sec_cfg(TSECSRDB, NON_SECURE, NO_OVERRIDE, ENABLE), 186719fdb6eSVarun Wadekar mc_make_sec_cfg(TSECSWRB, NON_SECURE, NO_OVERRIDE, ENABLE), 187719fdb6eSVarun Wadekar mc_make_sec_cfg(AXISR, SECURE, NO_OVERRIDE, DISABLE), 188719fdb6eSVarun Wadekar mc_make_sec_cfg(AXISW, SECURE, NO_OVERRIDE, DISABLE), 189719fdb6eSVarun Wadekar mc_make_sec_cfg(EQOSR, NON_SECURE, OVERRIDE, ENABLE), 190719fdb6eSVarun Wadekar mc_make_sec_cfg(EQOSW, NON_SECURE, OVERRIDE, ENABLE), 191719fdb6eSVarun Wadekar mc_make_sec_cfg(UFSHCR, NON_SECURE, OVERRIDE, ENABLE), 192719fdb6eSVarun Wadekar mc_make_sec_cfg(UFSHCW, NON_SECURE, OVERRIDE, ENABLE), 193719fdb6eSVarun Wadekar mc_make_sec_cfg(NVDISPLAYR, NON_SECURE, OVERRIDE, ENABLE), 194719fdb6eSVarun Wadekar mc_make_sec_cfg(BPMPR, NON_SECURE, NO_OVERRIDE, ENABLE), 195719fdb6eSVarun Wadekar mc_make_sec_cfg(BPMPW, NON_SECURE, NO_OVERRIDE, ENABLE), 196719fdb6eSVarun Wadekar mc_make_sec_cfg(BPMPDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), 197719fdb6eSVarun Wadekar mc_make_sec_cfg(BPMPDMAW, NON_SECURE, NO_OVERRIDE, ENABLE), 198719fdb6eSVarun Wadekar mc_make_sec_cfg(AONR, NON_SECURE, NO_OVERRIDE, ENABLE), 199719fdb6eSVarun Wadekar mc_make_sec_cfg(AONW, NON_SECURE, NO_OVERRIDE, ENABLE), 200719fdb6eSVarun Wadekar mc_make_sec_cfg(AONDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), 201719fdb6eSVarun Wadekar mc_make_sec_cfg(AONDMAW, NON_SECURE, NO_OVERRIDE, ENABLE), 202719fdb6eSVarun Wadekar mc_make_sec_cfg(SCER, NON_SECURE, NO_OVERRIDE, ENABLE), 203719fdb6eSVarun Wadekar mc_make_sec_cfg(SCEW, NON_SECURE, NO_OVERRIDE, ENABLE), 204719fdb6eSVarun Wadekar mc_make_sec_cfg(SCEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), 205719fdb6eSVarun Wadekar mc_make_sec_cfg(SCEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE), 206719fdb6eSVarun Wadekar mc_make_sec_cfg(APEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), 207719fdb6eSVarun Wadekar mc_make_sec_cfg(APEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE), 208719fdb6eSVarun Wadekar mc_make_sec_cfg(NVDISPLAYR1, NON_SECURE, OVERRIDE, ENABLE), 209719fdb6eSVarun Wadekar mc_make_sec_cfg(VICSRD1, NON_SECURE, NO_OVERRIDE, ENABLE), 210719fdb6eSVarun Wadekar mc_make_sec_cfg(NVDECSRD1, NON_SECURE, NO_OVERRIDE, ENABLE), 211719fdb6eSVarun Wadekar mc_make_sec_cfg(VIFALR, NON_SECURE, NO_OVERRIDE, ENABLE), 212719fdb6eSVarun Wadekar mc_make_sec_cfg(VIFALW, NON_SECURE, NO_OVERRIDE, ENABLE), 213719fdb6eSVarun Wadekar mc_make_sec_cfg(DLA0RDA, NON_SECURE, NO_OVERRIDE, ENABLE), 214719fdb6eSVarun Wadekar mc_make_sec_cfg(DLA0FALRDB, NON_SECURE, NO_OVERRIDE, ENABLE), 215719fdb6eSVarun Wadekar mc_make_sec_cfg(DLA0WRA, NON_SECURE, NO_OVERRIDE, ENABLE), 216719fdb6eSVarun Wadekar mc_make_sec_cfg(DLA0FALWRB, NON_SECURE, NO_OVERRIDE, ENABLE), 217719fdb6eSVarun Wadekar mc_make_sec_cfg(DLA1RDA, NON_SECURE, NO_OVERRIDE, ENABLE), 218719fdb6eSVarun Wadekar mc_make_sec_cfg(DLA1FALRDB, NON_SECURE, NO_OVERRIDE, ENABLE), 219719fdb6eSVarun Wadekar mc_make_sec_cfg(DLA1WRA, NON_SECURE, NO_OVERRIDE, ENABLE), 220719fdb6eSVarun Wadekar mc_make_sec_cfg(DLA1FALWRB, NON_SECURE, NO_OVERRIDE, ENABLE), 221719fdb6eSVarun Wadekar mc_make_sec_cfg(PVA0RDA, NON_SECURE, NO_OVERRIDE, ENABLE), 222719fdb6eSVarun Wadekar mc_make_sec_cfg(PVA0RDB, NON_SECURE, NO_OVERRIDE, ENABLE), 223719fdb6eSVarun Wadekar mc_make_sec_cfg(PVA0RDC, NON_SECURE, NO_OVERRIDE, ENABLE), 224719fdb6eSVarun Wadekar mc_make_sec_cfg(PVA0WRA, NON_SECURE, NO_OVERRIDE, ENABLE), 225719fdb6eSVarun Wadekar mc_make_sec_cfg(PVA0WRB, NON_SECURE, NO_OVERRIDE, ENABLE), 226719fdb6eSVarun Wadekar mc_make_sec_cfg(PVA0WRC, NON_SECURE, NO_OVERRIDE, ENABLE), 227719fdb6eSVarun Wadekar mc_make_sec_cfg(PVA1RDA, NON_SECURE, NO_OVERRIDE, ENABLE), 228719fdb6eSVarun Wadekar mc_make_sec_cfg(PVA1RDB, NON_SECURE, NO_OVERRIDE, ENABLE), 229719fdb6eSVarun Wadekar mc_make_sec_cfg(PVA1RDC, NON_SECURE, NO_OVERRIDE, ENABLE), 230719fdb6eSVarun Wadekar mc_make_sec_cfg(PVA1WRA, NON_SECURE, NO_OVERRIDE, ENABLE), 231719fdb6eSVarun Wadekar mc_make_sec_cfg(PVA1WRB, NON_SECURE, NO_OVERRIDE, ENABLE), 232719fdb6eSVarun Wadekar mc_make_sec_cfg(PVA1WRC, NON_SECURE, NO_OVERRIDE, ENABLE), 233719fdb6eSVarun Wadekar mc_make_sec_cfg(RCER, NON_SECURE, NO_OVERRIDE, ENABLE), 234719fdb6eSVarun Wadekar mc_make_sec_cfg(RCEW, NON_SECURE, NO_OVERRIDE, ENABLE), 235719fdb6eSVarun Wadekar mc_make_sec_cfg(RCEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), 236719fdb6eSVarun Wadekar mc_make_sec_cfg(RCEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE), 237719fdb6eSVarun Wadekar mc_make_sec_cfg(NVENC1SRD, NON_SECURE, NO_OVERRIDE, ENABLE), 238719fdb6eSVarun Wadekar mc_make_sec_cfg(NVENC1SWR, NON_SECURE, NO_OVERRIDE, ENABLE), 239719fdb6eSVarun Wadekar mc_make_sec_cfg(PCIE0R, NON_SECURE, OVERRIDE, ENABLE), 240719fdb6eSVarun Wadekar mc_make_sec_cfg(PCIE0W, NON_SECURE, OVERRIDE, ENABLE), 241719fdb6eSVarun Wadekar mc_make_sec_cfg(PCIE1R, NON_SECURE, OVERRIDE, ENABLE), 242719fdb6eSVarun Wadekar mc_make_sec_cfg(PCIE1W, NON_SECURE, OVERRIDE, ENABLE), 243719fdb6eSVarun Wadekar mc_make_sec_cfg(PCIE2AR, NON_SECURE, OVERRIDE, ENABLE), 244719fdb6eSVarun Wadekar mc_make_sec_cfg(PCIE2AW, NON_SECURE, OVERRIDE, ENABLE), 245719fdb6eSVarun Wadekar mc_make_sec_cfg(PCIE3R, NON_SECURE, OVERRIDE, ENABLE), 246719fdb6eSVarun Wadekar mc_make_sec_cfg(PCIE3W, NON_SECURE, OVERRIDE, ENABLE), 247719fdb6eSVarun Wadekar mc_make_sec_cfg(PCIE4R, NON_SECURE, OVERRIDE, ENABLE), 248719fdb6eSVarun Wadekar mc_make_sec_cfg(PCIE4W, NON_SECURE, OVERRIDE, ENABLE), 249719fdb6eSVarun Wadekar mc_make_sec_cfg(PCIE5R, NON_SECURE, OVERRIDE, ENABLE), 250719fdb6eSVarun Wadekar mc_make_sec_cfg(PCIE5W, NON_SECURE, OVERRIDE, ENABLE), 251719fdb6eSVarun Wadekar mc_make_sec_cfg(ISPFALW, NON_SECURE, NO_OVERRIDE, ENABLE), 252719fdb6eSVarun Wadekar mc_make_sec_cfg(DLA0RDA1, NON_SECURE, NO_OVERRIDE, ENABLE), 253719fdb6eSVarun Wadekar mc_make_sec_cfg(DLA1RDA1, NON_SECURE, NO_OVERRIDE, ENABLE), 254719fdb6eSVarun Wadekar mc_make_sec_cfg(PVA0RDA1, NON_SECURE, NO_OVERRIDE, ENABLE), 255719fdb6eSVarun Wadekar mc_make_sec_cfg(PVA0RDB1, NON_SECURE, NO_OVERRIDE, ENABLE), 256719fdb6eSVarun Wadekar mc_make_sec_cfg(PVA1RDA1, NON_SECURE, NO_OVERRIDE, ENABLE), 257719fdb6eSVarun Wadekar mc_make_sec_cfg(PVA1RDB1, NON_SECURE, NO_OVERRIDE, ENABLE), 258719fdb6eSVarun Wadekar mc_make_sec_cfg(PCIE5R1, NON_SECURE, OVERRIDE, ENABLE), 259719fdb6eSVarun Wadekar mc_make_sec_cfg(NVENCSRD1, NON_SECURE, NO_OVERRIDE, ENABLE), 260719fdb6eSVarun Wadekar mc_make_sec_cfg(NVENC1SRD1, NON_SECURE, NO_OVERRIDE, ENABLE), 261719fdb6eSVarun Wadekar mc_make_sec_cfg(ISPRA1, NON_SECURE, NO_OVERRIDE, ENABLE), 262719fdb6eSVarun Wadekar mc_make_sec_cfg(MIU0R, NON_SECURE, OVERRIDE, ENABLE), 263719fdb6eSVarun Wadekar mc_make_sec_cfg(MIU0W, NON_SECURE, OVERRIDE, ENABLE), 264719fdb6eSVarun Wadekar mc_make_sec_cfg(MIU1R, NON_SECURE, OVERRIDE, ENABLE), 265719fdb6eSVarun Wadekar mc_make_sec_cfg(MIU1W, NON_SECURE, OVERRIDE, ENABLE), 266719fdb6eSVarun Wadekar mc_make_sec_cfg(MIU2R, NON_SECURE, OVERRIDE, ENABLE), 267719fdb6eSVarun Wadekar mc_make_sec_cfg(MIU2W, NON_SECURE, OVERRIDE, ENABLE), 268719fdb6eSVarun Wadekar mc_make_sec_cfg(MIU3R, NON_SECURE, OVERRIDE, ENABLE), 269719fdb6eSVarun Wadekar mc_make_sec_cfg(MIU3W, NON_SECURE, OVERRIDE, ENABLE), 270719fdb6eSVarun Wadekar }; 271719fdb6eSVarun Wadekar 272719fdb6eSVarun Wadekar /******************************************************************************* 273719fdb6eSVarun Wadekar * Array to hold the transaction override configs 274719fdb6eSVarun Wadekar ******************************************************************************/ 275719fdb6eSVarun Wadekar const static mc_txn_override_cfg_t tegra194_txn_override_cfgs[] = { 276719fdb6eSVarun Wadekar mc_make_txn_override_cfg(NVENCSWR, CGID_TAG_ADR), 277719fdb6eSVarun Wadekar mc_make_txn_override_cfg(HDAW, CGID_TAG_ADR), 278719fdb6eSVarun Wadekar mc_make_txn_override_cfg(SATAW, CGID_TAG_ADR), 279719fdb6eSVarun Wadekar mc_make_txn_override_cfg(ISPWB, CGID_TAG_ADR), 280719fdb6eSVarun Wadekar mc_make_txn_override_cfg(XUSB_HOSTW, CGID_TAG_ADR), 281719fdb6eSVarun Wadekar mc_make_txn_override_cfg(XUSB_DEVW, CGID_TAG_ADR), 282719fdb6eSVarun Wadekar mc_make_txn_override_cfg(TSECSWR, CGID_TAG_ADR), 283719fdb6eSVarun Wadekar mc_make_txn_override_cfg(SDMMCWA, CGID_TAG_ADR), 284719fdb6eSVarun Wadekar mc_make_txn_override_cfg(SDMMCW, CGID_TAG_ADR), 285719fdb6eSVarun Wadekar mc_make_txn_override_cfg(SDMMCWAB, CGID_TAG_ADR), 286719fdb6eSVarun Wadekar mc_make_txn_override_cfg(VICSWR, CGID_TAG_ADR), 287719fdb6eSVarun Wadekar mc_make_txn_override_cfg(NVDECSWR, CGID_TAG_ADR), 288719fdb6eSVarun Wadekar mc_make_txn_override_cfg(APEW, CGID_TAG_ADR), 289719fdb6eSVarun Wadekar mc_make_txn_override_cfg(NVJPGSWR, CGID_TAG_ADR), 290719fdb6eSVarun Wadekar mc_make_txn_override_cfg(SESWR, CGID_TAG_ADR), 291719fdb6eSVarun Wadekar mc_make_txn_override_cfg(ETRW, CGID_TAG_ADR), 292719fdb6eSVarun Wadekar mc_make_txn_override_cfg(TSECSWRB, CGID_TAG_ADR), 293719fdb6eSVarun Wadekar mc_make_txn_override_cfg(AXISW, CGID_TAG_ADR), 294719fdb6eSVarun Wadekar mc_make_txn_override_cfg(EQOSW, CGID_TAG_ADR), 295719fdb6eSVarun Wadekar mc_make_txn_override_cfg(UFSHCW, CGID_TAG_ADR), 296719fdb6eSVarun Wadekar mc_make_txn_override_cfg(BPMPW, CGID_TAG_ADR), 297719fdb6eSVarun Wadekar mc_make_txn_override_cfg(BPMPDMAW, CGID_TAG_ADR), 298719fdb6eSVarun Wadekar mc_make_txn_override_cfg(AONW, CGID_TAG_ADR), 299719fdb6eSVarun Wadekar mc_make_txn_override_cfg(AONDMAW, CGID_TAG_ADR), 300719fdb6eSVarun Wadekar mc_make_txn_override_cfg(SCEW, CGID_TAG_ADR), 301719fdb6eSVarun Wadekar mc_make_txn_override_cfg(SCEDMAW, CGID_TAG_ADR), 302719fdb6eSVarun Wadekar }; 303719fdb6eSVarun Wadekar 304f32e8525SVarun Wadekar /* To be called by common memctrl_v2.c */ 305f32e8525SVarun Wadekar static void tegra194_memctrl_reconfig_mss_clients(void) 306f32e8525SVarun Wadekar { 307f32e8525SVarun Wadekar uint32_t reg_val, wdata_0, wdata_1, wdata_2; 308f32e8525SVarun Wadekar 309f32e8525SVarun Wadekar wdata_0 = MC_CLIENT_HOTRESET_CTRL0_HC_FLUSH_ENB | 310f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL0_SATA_FLUSH_ENB | 311f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL0_VIC_FLUSH_ENB | 312f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL0_XUSB_HOST_FLUSH_ENB | 313f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL0_XUSB_DEV_FLUSH_ENB | 314f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL0_TSEC_FLUSH_ENB | 315f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL0_SDMMC3A_FLUSH_ENB; 316f32e8525SVarun Wadekar if (tegra_platform_is_silicon()) { 317f32e8525SVarun Wadekar wdata_0 |= MC_CLIENT_HOTRESET_CTRL0_SDMMC1A_FLUSH_ENB; 318f32e8525SVarun Wadekar } 319f32e8525SVarun Wadekar 320f32e8525SVarun Wadekar tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL0, wdata_0); 321f32e8525SVarun Wadekar 322f32e8525SVarun Wadekar /* Wait for HOTRESET STATUS to indicate FLUSH_DONE */ 323f32e8525SVarun Wadekar do { 324f32e8525SVarun Wadekar reg_val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS0); 325f32e8525SVarun Wadekar } while ((reg_val & wdata_0) != wdata_0); 326f32e8525SVarun Wadekar 327f32e8525SVarun Wadekar wdata_1 = MC_CLIENT_HOTRESET_CTRL1_SDMMC4A_FLUSH_ENB | 328f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL1_SE_FLUSH_ENB | 329f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL1_ETR_FLUSH_ENB | 330f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL1_TSECB_FLUSH_ENB| 331f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL1_AXIS_FLUSH_ENB | 332f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL1_UFSHC_FLUSH_ENB | 333f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL1_NVDISPLAY_FLUSH_ENB | 334f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL1_BPMP_FLUSH_ENB | 335f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL1_AON_FLUSH_ENB | 336f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL1_SCE_FLUSH_ENB | 337f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL1_VIFAL_FLUSH_ENB; 338f32e8525SVarun Wadekar if (tegra_platform_is_silicon()) { 339f32e8525SVarun Wadekar wdata_1 |= MC_CLIENT_HOTRESET_CTRL1_APE_FLUSH_ENB | 340f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL1_EQOS_FLUSH_ENB | 341f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL1_RCE_FLUSH_ENB; 342f32e8525SVarun Wadekar } 343f32e8525SVarun Wadekar tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL1, wdata_1); 344f32e8525SVarun Wadekar /* Wait for HOTRESET STATUS to indicate FLUSH_DONE */ 345f32e8525SVarun Wadekar do { 346f32e8525SVarun Wadekar reg_val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS1); 347f32e8525SVarun Wadekar } while ((reg_val & wdata_1) != wdata_1); 348f32e8525SVarun Wadekar 349f32e8525SVarun Wadekar wdata_2 = MC_CLIENT_HOTRESET_CTRL2_PCIE_FLUSH_ENB | 350f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL2_AONDMA_FLUSH_ENB | 351f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL2_BPMPDMA_FLUSH_ENB | 352f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL2_SCEDMA_FLUSH_ENB; 353f32e8525SVarun Wadekar if (tegra_platform_is_silicon()) { 354f32e8525SVarun Wadekar wdata_2 |= MC_CLIENT_HOTRESET_CTRL2_RCEDMA_FLUSH_ENB | 355f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL2_PCIE_FLUSH_ENB | 356f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL2_PCIE5A_FLUSH_ENB | 357f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL2_PCIE3A_FLUSH_ENB | 358f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL2_PCIE3_FLUSH_ENB | 359f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL2_PCIE0A_FLUSH_ENB | 360f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL2_PCIE0A2_FLUSH_ENB | 361f32e8525SVarun Wadekar MC_CLIENT_HOTRESET_CTRL2_PCIE4A_FLUSH_ENB; 362f32e8525SVarun Wadekar } 363f32e8525SVarun Wadekar tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL2, wdata_2); 364f32e8525SVarun Wadekar /* Wait for HOTRESET STATUS to indicate FLUSH_DONE */ 365f32e8525SVarun Wadekar do { 366f32e8525SVarun Wadekar reg_val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS2); 367f32e8525SVarun Wadekar } while ((reg_val & wdata_2) != wdata_2); 368f32e8525SVarun Wadekar 369f32e8525SVarun Wadekar /* 370f32e8525SVarun Wadekar * Change MEMTYPE_OVERRIDE from SO_DEV -> PASSTHRU for boot and 371f32e8525SVarun Wadekar * strongly ordered MSS clients. 372f32e8525SVarun Wadekar * 373f32e8525SVarun Wadekar * MC clients with default SO_DEV override still enabled at TSA: 374f32e8525SVarun Wadekar * EQOSW, SATAW, XUSB_DEVW, XUSB_HOSTW, PCIe0w, PCIe1w, PCIe2w, 375f32e8525SVarun Wadekar * PCIe3w, PCIe4w and PCIe5w. 376f32e8525SVarun Wadekar */ 377f32e8525SVarun Wadekar mc_set_tsa_w_passthrough(AONDMAW); 378f32e8525SVarun Wadekar mc_set_tsa_w_passthrough(AONW); 379f32e8525SVarun Wadekar mc_set_tsa_w_passthrough(APEDMAW); 380f32e8525SVarun Wadekar mc_set_tsa_w_passthrough(APEW); 381f32e8525SVarun Wadekar mc_set_tsa_w_passthrough(AXISW); 382f32e8525SVarun Wadekar mc_set_tsa_w_passthrough(BPMPDMAW); 383f32e8525SVarun Wadekar mc_set_tsa_w_passthrough(BPMPW); 384f32e8525SVarun Wadekar mc_set_tsa_w_passthrough(ETRW); 385f32e8525SVarun Wadekar mc_set_tsa_w_passthrough(SCEDMAW); 386f32e8525SVarun Wadekar mc_set_tsa_w_passthrough(RCEDMAW); 387f32e8525SVarun Wadekar mc_set_tsa_w_passthrough(RCEW); 388f32e8525SVarun Wadekar mc_set_tsa_w_passthrough(SDMMCW); 389f32e8525SVarun Wadekar mc_set_tsa_w_passthrough(SDMMCWA); 390f32e8525SVarun Wadekar mc_set_tsa_w_passthrough(SDMMCWAB); 391f32e8525SVarun Wadekar mc_set_tsa_w_passthrough(TSECSWR); 392f32e8525SVarun Wadekar mc_set_tsa_w_passthrough(TSECSWRB); 393f32e8525SVarun Wadekar mc_set_tsa_w_passthrough(UFSHCW); 394f32e8525SVarun Wadekar mc_set_tsa_w_passthrough(VICSWR); 395f32e8525SVarun Wadekar mc_set_tsa_w_passthrough(VIFALW); 396f32e8525SVarun Wadekar 397f32e8525SVarun Wadekar /* Ordered MC Clients on Xavier are EQOS, SATA, XUSB, PCIe1 and PCIe3 398f32e8525SVarun Wadekar * ISO clients(DISP, VI, EQOS) should never snoop caches and 399f32e8525SVarun Wadekar * don't need ROC/PCFIFO ordering. 400f32e8525SVarun Wadekar * ISO clients(EQOS) that need ordering should use PCFIFO ordering 401f32e8525SVarun Wadekar * and bypass ROC ordering by using FORCE_NON_COHERENT path. 402f32e8525SVarun Wadekar * FORCE_NON_COHERENT/FORCE_COHERENT config take precedence 403f32e8525SVarun Wadekar * over SMMU attributes. 404f32e8525SVarun Wadekar * Force all Normal memory transactions from ISO and non-ISO to be 405f32e8525SVarun Wadekar * non-coherent(bypass ROC, avoid cache snoop to avoid perf hit). 406f32e8525SVarun Wadekar * Force the SO_DEV transactions from ordered ISO clients(EQOS) to 407f32e8525SVarun Wadekar * non-coherent path and enable MC PCFIFO interlock for ordering. 408f32e8525SVarun Wadekar * Force the SO_DEV transactions from ordered non-ISO clients (PCIe, 409f32e8525SVarun Wadekar * XUSB, SATA) to coherent so that the transactions are 410f32e8525SVarun Wadekar * ordered by ROC. 411f32e8525SVarun Wadekar * PCFIFO ensure write ordering. 412f32e8525SVarun Wadekar * Read after Write ordering is maintained/enforced by MC clients. 413f32e8525SVarun Wadekar * Clients that need PCIe type write ordering must 414f32e8525SVarun Wadekar * go through ROC ordering. 415f32e8525SVarun Wadekar * Ordering enable for Read clients is not necessary. 416f32e8525SVarun Wadekar * R5's and A9 would get necessary ordering from AXI and 417f32e8525SVarun Wadekar * don't need ROC ordering enable: 418f32e8525SVarun Wadekar * - MMIO ordering is through dev mapping and MMIO 419f32e8525SVarun Wadekar * accesses bypass SMMU. 420f32e8525SVarun Wadekar * - Normal memory is accessed through SMMU and ordering is 421f32e8525SVarun Wadekar * ensured by client and AXI. 422f32e8525SVarun Wadekar * - Ack point for Normal memory is WCAM in MC. 423f32e8525SVarun Wadekar * - MMIO's can be early acked and AXI ensures dev memory ordering, 424f32e8525SVarun Wadekar * Client ensures read/write direction change ordering. 425f32e8525SVarun Wadekar * - See Bug 200312466 for more details. 426f32e8525SVarun Wadekar * 427f32e8525SVarun Wadekar * CGID_TAG_ADR is only present from T186 A02. As this code is common 428f32e8525SVarun Wadekar * between A01 and A02, tegra_memctrl_set_overrides() programs 429f32e8525SVarun Wadekar * CGID_TAG_ADR for the necessary clients on A02. 430f32e8525SVarun Wadekar */ 431f32e8525SVarun Wadekar mc_set_txn_override(AONDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 432f32e8525SVarun Wadekar mc_set_txn_override(AONDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 433f32e8525SVarun Wadekar mc_set_txn_override(AONR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 434f32e8525SVarun Wadekar mc_set_txn_override(AONW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 435f32e8525SVarun Wadekar mc_set_txn_override(APEDMAR, CGID_TAG_CLIENT_AXI_ID, SO_DEV_CLIENT_AXI_ID, NO_OVERRIDE, NO_OVERRIDE); 436f32e8525SVarun Wadekar mc_set_txn_override(APEDMAW, CGID_TAG_CLIENT_AXI_ID, SO_DEV_CLIENT_AXI_ID, NO_OVERRIDE, NO_OVERRIDE); 437f32e8525SVarun Wadekar mc_set_txn_override(APER, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 438f32e8525SVarun Wadekar mc_set_txn_override(APEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 439f32e8525SVarun Wadekar mc_set_txn_override(AXISR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 440f32e8525SVarun Wadekar mc_set_txn_override(AXISW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 441f32e8525SVarun Wadekar mc_set_txn_override(BPMPDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 442f32e8525SVarun Wadekar mc_set_txn_override(BPMPDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 443f32e8525SVarun Wadekar mc_set_txn_override(BPMPR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 444f32e8525SVarun Wadekar mc_set_txn_override(BPMPW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 445f32e8525SVarun Wadekar mc_set_txn_override(EQOSR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 446f32e8525SVarun Wadekar mc_set_txn_override(EQOSW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 447f32e8525SVarun Wadekar mc_set_txn_override(ETRR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 448f32e8525SVarun Wadekar mc_set_txn_override(ETRW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 449f32e8525SVarun Wadekar mc_set_txn_override(HOST1XDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 450f32e8525SVarun Wadekar mc_set_txn_override(MPCORER, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 451f32e8525SVarun Wadekar mc_set_txn_override(MPCOREW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 452f32e8525SVarun Wadekar mc_set_txn_override(NVDISPLAYR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 453f32e8525SVarun Wadekar mc_set_txn_override(PTCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 454f32e8525SVarun Wadekar mc_set_txn_override(SATAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 455f32e8525SVarun Wadekar mc_set_txn_override(SATAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_COHERENT_SNOOP); 456f32e8525SVarun Wadekar mc_set_txn_override(SCEDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 457f32e8525SVarun Wadekar mc_set_txn_override(SCEDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 458f32e8525SVarun Wadekar mc_set_txn_override(SCER, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 459f32e8525SVarun Wadekar mc_set_txn_override(SCEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 460f32e8525SVarun Wadekar mc_set_txn_override(RCEDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 461f32e8525SVarun Wadekar mc_set_txn_override(RCEDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 462f32e8525SVarun Wadekar mc_set_txn_override(RCER, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 463f32e8525SVarun Wadekar mc_set_txn_override(RCEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 464f32e8525SVarun Wadekar mc_set_txn_override(SDMMCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 465f32e8525SVarun Wadekar mc_set_txn_override(SDMMCRAB, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 466f32e8525SVarun Wadekar mc_set_txn_override(SDMMCRA, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 467f32e8525SVarun Wadekar mc_set_txn_override(SDMMCW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 468f32e8525SVarun Wadekar mc_set_txn_override(SDMMCWA, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 469f32e8525SVarun Wadekar mc_set_txn_override(SDMMCWAB, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 4705ad50d7dSPuneet Saxena mc_set_txn_override(SESRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, NO_OVERRIDE); 4715ad50d7dSPuneet Saxena mc_set_txn_override(SESWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, NO_OVERRIDE); 472f32e8525SVarun Wadekar mc_set_txn_override(TSECSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 473f32e8525SVarun Wadekar mc_set_txn_override(TSECSRDB, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 474f32e8525SVarun Wadekar mc_set_txn_override(TSECSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 475f32e8525SVarun Wadekar mc_set_txn_override(TSECSWRB, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 476f32e8525SVarun Wadekar mc_set_txn_override(UFSHCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 477f32e8525SVarun Wadekar mc_set_txn_override(UFSHCW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 478f32e8525SVarun Wadekar mc_set_txn_override(VICSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 479f32e8525SVarun Wadekar mc_set_txn_override(VICSRD1, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 480f32e8525SVarun Wadekar mc_set_txn_override(VICSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 481f32e8525SVarun Wadekar mc_set_txn_override(VIFALR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 482f32e8525SVarun Wadekar mc_set_txn_override(VIFALW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 483f32e8525SVarun Wadekar mc_set_txn_override(XUSB_DEVR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 484f32e8525SVarun Wadekar mc_set_txn_override(XUSB_DEVW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, 485f32e8525SVarun Wadekar FORCE_COHERENT_SNOOP); 486f32e8525SVarun Wadekar mc_set_txn_override(XUSB_HOSTR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 487f32e8525SVarun Wadekar mc_set_txn_override(XUSB_HOSTW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, 488f32e8525SVarun Wadekar FORCE_COHERENT_SNOOP); 489f32e8525SVarun Wadekar mc_set_txn_override(PCIE0R, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 490f32e8525SVarun Wadekar mc_set_txn_override(PCIE0R1, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 491f32e8525SVarun Wadekar mc_set_txn_override(PCIE0W, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, 492f32e8525SVarun Wadekar FORCE_COHERENT_SNOOP); 493f32e8525SVarun Wadekar mc_set_txn_override(PCIE1R, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 494f32e8525SVarun Wadekar mc_set_txn_override(PCIE1W, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, 495f32e8525SVarun Wadekar FORCE_COHERENT_SNOOP); 496f32e8525SVarun Wadekar if (tegra_platform_is_silicon()) { 497f32e8525SVarun Wadekar mc_set_txn_override(PCIE2AR, CGID_TAG_DEFAULT, SO_DEV_ZERO, 498f32e8525SVarun Wadekar NO_OVERRIDE, NO_OVERRIDE); 499f32e8525SVarun Wadekar mc_set_txn_override(PCIE2AW, CGID_TAG_DEFAULT, SO_DEV_ZERO, 500f32e8525SVarun Wadekar FORCE_NON_COHERENT, FORCE_COHERENT_SNOOP); 501f32e8525SVarun Wadekar mc_set_txn_override(PCIE3R, CGID_TAG_DEFAULT, SO_DEV_ZERO, 502f32e8525SVarun Wadekar NO_OVERRIDE, NO_OVERRIDE); 503f32e8525SVarun Wadekar mc_set_txn_override(PCIE3W, CGID_TAG_DEFAULT, SO_DEV_ZERO, 504f32e8525SVarun Wadekar FORCE_NON_COHERENT, FORCE_COHERENT_SNOOP); 505f32e8525SVarun Wadekar mc_set_txn_override(PCIE4R, CGID_TAG_DEFAULT, SO_DEV_ZERO, 506f32e8525SVarun Wadekar NO_OVERRIDE, NO_OVERRIDE); 507f32e8525SVarun Wadekar mc_set_txn_override(PCIE4W, CGID_TAG_DEFAULT, SO_DEV_ZERO, 508f32e8525SVarun Wadekar FORCE_NON_COHERENT, FORCE_COHERENT_SNOOP); 509f32e8525SVarun Wadekar mc_set_txn_override(PCIE5R, CGID_TAG_DEFAULT, SO_DEV_ZERO, 510f32e8525SVarun Wadekar NO_OVERRIDE, NO_OVERRIDE); 511f32e8525SVarun Wadekar mc_set_txn_override(PCIE5W, CGID_TAG_DEFAULT, SO_DEV_ZERO, 512f32e8525SVarun Wadekar FORCE_NON_COHERENT, FORCE_COHERENT_SNOOP); 513f32e8525SVarun Wadekar mc_set_txn_override(PCIE5R1, CGID_TAG_DEFAULT, SO_DEV_ZERO, 514f32e8525SVarun Wadekar NO_OVERRIDE, NO_OVERRIDE); 515f32e8525SVarun Wadekar } 516f32e8525SVarun Wadekar /* 517f32e8525SVarun Wadekar * At this point, ordering can occur at ROC. So, remove PCFIFO's 518f32e8525SVarun Wadekar * control over ordering requests. 519f32e8525SVarun Wadekar * 520f32e8525SVarun Wadekar * Change PCFIFO_*_ORDERED_CLIENT from ORDERED -> UNORDERED for 521f32e8525SVarun Wadekar * boot and strongly ordered MSS clients 522f32e8525SVarun Wadekar */ 523f32e8525SVarun Wadekar /* SATAW is ordered client */ 524f32e8525SVarun Wadekar reg_val = MC_PCFIFO_CLIENT_CONFIG1_RESET_VAL | 525f32e8525SVarun Wadekar mc_set_pcfifo_ordered_boot_so_mss(1, SATAW); 526f32e8525SVarun Wadekar tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG1, reg_val); 527f32e8525SVarun Wadekar 528f32e8525SVarun Wadekar reg_val = MC_PCFIFO_CLIENT_CONFIG2_RESET_VAL & 529f32e8525SVarun Wadekar mc_set_pcfifo_unordered_boot_so_mss(2, XUSB_HOSTW) & 530f32e8525SVarun Wadekar mc_set_pcfifo_unordered_boot_so_mss(2, TSECSWR); 531f32e8525SVarun Wadekar /* XUSB_DEVW has PCFIFO enabled. */ 532f32e8525SVarun Wadekar reg_val |= mc_set_pcfifo_ordered_boot_so_mss(2, XUSB_DEVW); 533f32e8525SVarun Wadekar tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG2, reg_val); 534f32e8525SVarun Wadekar 535f32e8525SVarun Wadekar reg_val = MC_PCFIFO_CLIENT_CONFIG3_RESET_VAL & 536f32e8525SVarun Wadekar mc_set_pcfifo_unordered_boot_so_mss(3, SDMMCWA) & 537f32e8525SVarun Wadekar mc_set_pcfifo_unordered_boot_so_mss(3, SDMMCW) & 538f32e8525SVarun Wadekar mc_set_pcfifo_unordered_boot_so_mss(3, SDMMCWAB) & 539f32e8525SVarun Wadekar mc_set_pcfifo_unordered_boot_so_mss(3, VICSWR) & 540f32e8525SVarun Wadekar mc_set_pcfifo_unordered_boot_so_mss(3, APEW); 541f32e8525SVarun Wadekar tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG3, reg_val); 542f32e8525SVarun Wadekar 543f32e8525SVarun Wadekar reg_val = MC_PCFIFO_CLIENT_CONFIG4_RESET_VAL & 544f32e8525SVarun Wadekar mc_set_pcfifo_unordered_boot_so_mss(4, SESWR) & 545f32e8525SVarun Wadekar mc_set_pcfifo_unordered_boot_so_mss(4, ETRW) & 546f32e8525SVarun Wadekar mc_set_pcfifo_unordered_boot_so_mss(4, TSECSWRB) & 547f32e8525SVarun Wadekar mc_set_pcfifo_unordered_boot_so_mss(4, AXISW) & 548f32e8525SVarun Wadekar mc_set_pcfifo_unordered_boot_so_mss(4, UFSHCW) & 549f32e8525SVarun Wadekar mc_set_pcfifo_unordered_boot_so_mss(4, BPMPW) & 550f32e8525SVarun Wadekar mc_set_pcfifo_unordered_boot_so_mss(4, BPMPDMAW) & 551f32e8525SVarun Wadekar mc_set_pcfifo_unordered_boot_so_mss(4, AONW) & 552f32e8525SVarun Wadekar mc_set_pcfifo_unordered_boot_so_mss(4, AONDMAW) & 553f32e8525SVarun Wadekar mc_set_pcfifo_unordered_boot_so_mss(4, SCEW) & 554f32e8525SVarun Wadekar mc_set_pcfifo_unordered_boot_so_mss(4, SCEDMAW); 555f32e8525SVarun Wadekar /* EQOSW has PCFIFO order enabled. */ 556f32e8525SVarun Wadekar reg_val |= mc_set_pcfifo_ordered_boot_so_mss(4, EQOSW); 557f32e8525SVarun Wadekar tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG4, reg_val); 558f32e8525SVarun Wadekar 559f32e8525SVarun Wadekar reg_val = MC_PCFIFO_CLIENT_CONFIG5_RESET_VAL & 560f32e8525SVarun Wadekar mc_set_pcfifo_unordered_boot_so_mss(5, APEDMAW) & 561f32e8525SVarun Wadekar mc_set_pcfifo_unordered_boot_so_mss(5, VIFALW); 562f32e8525SVarun Wadekar tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG5, reg_val); 563f32e8525SVarun Wadekar 564f32e8525SVarun Wadekar reg_val = MC_PCFIFO_CLIENT_CONFIG6_RESET_VAL & 565f32e8525SVarun Wadekar mc_set_pcfifo_unordered_boot_so_mss(6, RCEW) & 566f32e8525SVarun Wadekar mc_set_pcfifo_unordered_boot_so_mss(6, RCEDMAW) & 567f32e8525SVarun Wadekar mc_set_pcfifo_unordered_boot_so_mss(6, PCIE0W); 568f32e8525SVarun Wadekar /* PCIE1, PCIE2 and PCI3 has PCFIFO enabled. */ 569f32e8525SVarun Wadekar reg_val |= mc_set_pcfifo_ordered_boot_so_mss(6, PCIE1W) | 570f32e8525SVarun Wadekar mc_set_pcfifo_ordered_boot_so_mss(6, PCIE2W) | 571f32e8525SVarun Wadekar mc_set_pcfifo_ordered_boot_so_mss(6, PCIE3W); 572f32e8525SVarun Wadekar tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG6, reg_val); 573f32e8525SVarun Wadekar 574f32e8525SVarun Wadekar reg_val = MC_PCFIFO_CLIENT_CONFIG7_RESET_VAL & 575f32e8525SVarun Wadekar mc_set_pcfifo_unordered_boot_so_mss(7, PCIE4W) & 576f32e8525SVarun Wadekar mc_set_pcfifo_unordered_boot_so_mss(7, PCIE5W); 577f32e8525SVarun Wadekar tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG7, reg_val); 578f32e8525SVarun Wadekar 579f32e8525SVarun Wadekar /* Set Order Id only for the clients having non zero order id */ 580f32e8525SVarun Wadekar reg_val = MC_CLIENT_ORDER_ID_9_RESET_VAL & 581f32e8525SVarun Wadekar mc_client_order_id(9, XUSB_HOSTW); 582f32e8525SVarun Wadekar tegra_mc_write_32(MC_CLIENT_ORDER_ID_9, reg_val); 583f32e8525SVarun Wadekar 584f32e8525SVarun Wadekar reg_val = MC_CLIENT_ORDER_ID_27_RESET_VAL & 585f32e8525SVarun Wadekar mc_client_order_id(27, PCIE0W); 586f32e8525SVarun Wadekar tegra_mc_write_32(MC_CLIENT_ORDER_ID_27, reg_val); 587f32e8525SVarun Wadekar 588f32e8525SVarun Wadekar reg_val = MC_CLIENT_ORDER_ID_28_RESET_VAL & 589f32e8525SVarun Wadekar mc_client_order_id(28, PCIE4W) & 590f32e8525SVarun Wadekar mc_client_order_id(28, PCIE5W); 591f32e8525SVarun Wadekar tegra_mc_write_32(MC_CLIENT_ORDER_ID_28, reg_val); 592f32e8525SVarun Wadekar 593f32e8525SVarun Wadekar /* Set VC Id only for the clients having different reset values */ 594f32e8525SVarun Wadekar reg_val = MC_HUB_PC_VC_ID_0_RESET_VAL & 595f32e8525SVarun Wadekar /* 596f32e8525SVarun Wadekar * SDMMCRAB, SDMMCWAB, SESRD, SESWR, TSECSRD,TSECSRDB, 597f32e8525SVarun Wadekar * TSECSWR and TSECSWRB clients 598f32e8525SVarun Wadekar */ 599f32e8525SVarun Wadekar mc_hub_vc_id(0, APB); 600f32e8525SVarun Wadekar tegra_mc_write_32(MC_HUB_PC_VC_ID_0, reg_val); 601f32e8525SVarun Wadekar 602f32e8525SVarun Wadekar reg_val = MC_HUB_PC_VC_ID_2_RESET_VAL & 603f32e8525SVarun Wadekar /* SDMMCRAB and SDMMCWAB clients */ 604f32e8525SVarun Wadekar mc_hub_vc_id(2, SD); 605f32e8525SVarun Wadekar tegra_mc_write_32(MC_HUB_PC_VC_ID_2, reg_val); 606f32e8525SVarun Wadekar 607f32e8525SVarun Wadekar reg_val = MC_HUB_PC_VC_ID_4_RESET_VAL & 608f32e8525SVarun Wadekar /* AXIR and AXIW clients */ 609f32e8525SVarun Wadekar mc_hub_vc_id(4, NIC); 610f32e8525SVarun Wadekar tegra_mc_write_32(MC_HUB_PC_VC_ID_4, reg_val); 611f32e8525SVarun Wadekar 612f32e8525SVarun Wadekar wdata_0 = MC_CLIENT_HOTRESET_CTRL0_RESET_VAL; 613f32e8525SVarun Wadekar tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL0, wdata_0); 614f32e8525SVarun Wadekar 615f32e8525SVarun Wadekar wdata_1 = MC_CLIENT_HOTRESET_CTRL1_RESET_VAL; 616f32e8525SVarun Wadekar tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL1, wdata_1); 617f32e8525SVarun Wadekar 618f32e8525SVarun Wadekar wdata_2 = MC_CLIENT_HOTRESET_CTRL2_RESET_VAL; 619f32e8525SVarun Wadekar tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL2, wdata_2); 620f32e8525SVarun Wadekar } 621f32e8525SVarun Wadekar 622719fdb6eSVarun Wadekar /******************************************************************************* 623719fdb6eSVarun Wadekar * Struct to hold the memory controller settings 624719fdb6eSVarun Wadekar ******************************************************************************/ 625719fdb6eSVarun Wadekar static tegra_mc_settings_t tegra194_mc_settings = { 626719fdb6eSVarun Wadekar .streamid_override_cfg = tegra194_streamid_override_regs, 627b6533b56SAnthony Zhou .num_streamid_override_cfgs = (uint32_t)ARRAY_SIZE(tegra194_streamid_override_regs), 628719fdb6eSVarun Wadekar .streamid_security_cfg = tegra194_streamid_sec_cfgs, 629b6533b56SAnthony Zhou .num_streamid_security_cfgs = (uint32_t)ARRAY_SIZE(tegra194_streamid_sec_cfgs), 630719fdb6eSVarun Wadekar .txn_override_cfg = tegra194_txn_override_cfgs, 631b6533b56SAnthony Zhou .num_txn_override_cfgs = (uint32_t)ARRAY_SIZE(tegra194_txn_override_cfgs), 632f32e8525SVarun Wadekar .reconfig_mss_clients = tegra194_memctrl_reconfig_mss_clients 633719fdb6eSVarun Wadekar }; 634719fdb6eSVarun Wadekar 635719fdb6eSVarun Wadekar /******************************************************************************* 636719fdb6eSVarun Wadekar * Handler to return the pointer to the memory controller's settings struct 637719fdb6eSVarun Wadekar ******************************************************************************/ 638719fdb6eSVarun Wadekar tegra_mc_settings_t *tegra_get_mc_settings(void) 639719fdb6eSVarun Wadekar { 640719fdb6eSVarun Wadekar return &tegra194_mc_settings; 641719fdb6eSVarun Wadekar } 6424e697b77SSteven Kao 6434e697b77SSteven Kao /******************************************************************************* 6444e697b77SSteven Kao * Handler to program the scratch registers with TZDRAM settings for the 6454e697b77SSteven Kao * resume firmware 6464e697b77SSteven Kao ******************************************************************************/ 6474e697b77SSteven Kao void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes) 6484e697b77SSteven Kao { 649*95397d96SSteven Kao uint32_t sec_reg_ctrl = tegra_mc_read_32(MC_SECURITY_CFG_REG_CTRL_0); 650*95397d96SSteven Kao 6514e697b77SSteven Kao /* 652*95397d96SSteven Kao * Check TZDRAM carveout register access status. Setup TZDRAM fence 653*95397d96SSteven Kao * only if access is enabled. 6544e697b77SSteven Kao */ 655*95397d96SSteven Kao if ((sec_reg_ctrl & SECURITY_CFG_WRITE_ACCESS_BIT) == 656*95397d96SSteven Kao SECURITY_CFG_WRITE_ACCESS_ENABLE) { 6574e697b77SSteven Kao 6584e697b77SSteven Kao /* 6594e697b77SSteven Kao * Setup the Memory controller to allow only secure accesses to 6604e697b77SSteven Kao * the TZDRAM carveout 6614e697b77SSteven Kao */ 6624e697b77SSteven Kao INFO("Configuring TrustZone DRAM Memory Carveout\n"); 6634e697b77SSteven Kao 6644e697b77SSteven Kao tegra_mc_write_32(MC_SECURITY_CFG0_0, (uint32_t)phys_base); 6654e697b77SSteven Kao tegra_mc_write_32(MC_SECURITY_CFG3_0, (uint32_t)(phys_base >> 32)); 6664e697b77SSteven Kao tegra_mc_write_32(MC_SECURITY_CFG1_0, (uint32_t)(size_in_bytes >> 20)); 6674e697b77SSteven Kao 6684e697b77SSteven Kao /* 6694e697b77SSteven Kao * MCE propagates the security configuration values across the 6704e697b77SSteven Kao * CCPLEX. 6714e697b77SSteven Kao */ 6724e697b77SSteven Kao (void)mce_update_gsc_tzdram(); 6734e697b77SSteven Kao } 6744e697b77SSteven Kao } 675