1*719fdb6eSVarun Wadekar /* 2*719fdb6eSVarun Wadekar * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. 3*719fdb6eSVarun Wadekar * 4*719fdb6eSVarun Wadekar * SPDX-License-Identifier: BSD-3-Clause 5*719fdb6eSVarun Wadekar */ 6*719fdb6eSVarun Wadekar 7*719fdb6eSVarun Wadekar #include <bl_common.h> 8*719fdb6eSVarun Wadekar #include <memctrl_v2.h> 9*719fdb6eSVarun Wadekar 10*719fdb6eSVarun Wadekar /******************************************************************************* 11*719fdb6eSVarun Wadekar * Array to hold stream_id override config register offsets 12*719fdb6eSVarun Wadekar ******************************************************************************/ 13*719fdb6eSVarun Wadekar const static uint32_t tegra194_streamid_override_regs[] = { 14*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_HDAR, 15*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR, 16*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_NVENCSRD, 17*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_SATAR, 18*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_NVENCSWR, 19*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_HDAW, 20*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_SATAW, 21*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_ISPRA, 22*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_ISPFALR, 23*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_ISPWA, 24*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_ISPWB, 25*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR, 26*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW, 27*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR, 28*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW, 29*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_TSECSRD, 30*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_TSECSWR, 31*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_SDMMCRA, 32*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_SDMMCR, 33*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_SDMMCRAB, 34*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_SDMMCWA, 35*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_SDMMCW, 36*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_SDMMCWAB, 37*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_VICSRD, 38*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_VICSWR, 39*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_VIW, 40*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_NVDECSRD, 41*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_NVDECSWR, 42*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_APER, 43*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_APEW, 44*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_NVJPGSRD, 45*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_NVJPGSWR, 46*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_SESRD, 47*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_SESWR, 48*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_AXIAPR, 49*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_AXIAPW, 50*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_ETRR, 51*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_ETRW, 52*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_TSECSRDB, 53*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_TSECSWRB, 54*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_AXISR, 55*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_AXISW, 56*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_EQOSR, 57*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_EQOSW, 58*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_UFSHCR, 59*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_UFSHCW, 60*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR, 61*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_BPMPR, 62*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_BPMPW, 63*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_BPMPDMAR, 64*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_BPMPDMAW, 65*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_AONR, 66*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_AONW, 67*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_AONDMAR, 68*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_AONDMAW, 69*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_SCER, 70*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_SCEW, 71*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_SCEDMAR, 72*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_SCEDMAW, 73*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_APEDMAR, 74*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_APEDMAW, 75*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1, 76*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_VICSRD1, 77*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_NVDECSRD1, 78*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_VIFALR, 79*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_VIFALW, 80*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_DLA0RDA, 81*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_DLA0FALRDB, 82*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_DLA0WRA, 83*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_DLA0FALWRB, 84*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_DLA1RDA, 85*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_DLA1FALRDB, 86*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_DLA1WRA, 87*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_DLA1FALWRB, 88*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PVA0RDA, 89*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PVA0RDB, 90*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PVA0RDC, 91*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PVA0WRA, 92*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PVA0WRB, 93*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PVA0WRC, 94*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PVA1RDA, 95*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PVA1RDB, 96*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PVA1RDC, 97*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PVA1WRA, 98*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PVA1WRB, 99*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PVA1WRC, 100*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_RCER, 101*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_RCEW, 102*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_RCEDMAR, 103*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_RCEDMAW, 104*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_NVENC1SRD, 105*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_NVENC1SWR, 106*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PCIE0R, 107*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PCIE0W, 108*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PCIE1R, 109*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PCIE1W, 110*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PCIE2AR, 111*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PCIE2AW, 112*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PCIE3R, 113*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PCIE3W, 114*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PCIE4R, 115*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PCIE4W, 116*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PCIE5R, 117*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PCIE5W, 118*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_ISPFALW, 119*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_DLA0RDA1, 120*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_DLA1RDA1, 121*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PVA0RDA1, 122*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PVA0RDB1, 123*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PVA1RDA1, 124*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PVA1RDB1, 125*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_PCIE5R1, 126*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_NVENCSRD1, 127*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_NVENC1SRD1, 128*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_ISPRA1, 129*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_MIU0R, 130*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_MIU0W, 131*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_MIU1R, 132*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_MIU1W, 133*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_MIU2R, 134*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_MIU2W, 135*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_MIU3R, 136*719fdb6eSVarun Wadekar MC_STREAMID_OVERRIDE_CFG_MIU3W 137*719fdb6eSVarun Wadekar }; 138*719fdb6eSVarun Wadekar 139*719fdb6eSVarun Wadekar /******************************************************************************* 140*719fdb6eSVarun Wadekar * Array to hold the security configs for stream IDs 141*719fdb6eSVarun Wadekar ******************************************************************************/ 142*719fdb6eSVarun Wadekar const static mc_streamid_security_cfg_t tegra194_streamid_sec_cfgs[] = { 143*719fdb6eSVarun Wadekar mc_make_sec_cfg(HDAR, NON_SECURE, OVERRIDE, ENABLE), 144*719fdb6eSVarun Wadekar mc_make_sec_cfg(HOST1XDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), 145*719fdb6eSVarun Wadekar mc_make_sec_cfg(NVENCSRD, NON_SECURE, NO_OVERRIDE, ENABLE), 146*719fdb6eSVarun Wadekar mc_make_sec_cfg(SATAR, NON_SECURE, OVERRIDE, ENABLE), 147*719fdb6eSVarun Wadekar mc_make_sec_cfg(NVENCSWR, NON_SECURE, NO_OVERRIDE, ENABLE), 148*719fdb6eSVarun Wadekar mc_make_sec_cfg(HDAW, NON_SECURE, OVERRIDE, ENABLE), 149*719fdb6eSVarun Wadekar mc_make_sec_cfg(SATAW, NON_SECURE, OVERRIDE, ENABLE), 150*719fdb6eSVarun Wadekar mc_make_sec_cfg(ISPRA, NON_SECURE, NO_OVERRIDE, ENABLE), 151*719fdb6eSVarun Wadekar mc_make_sec_cfg(ISPFALR, NON_SECURE, NO_OVERRIDE, ENABLE), 152*719fdb6eSVarun Wadekar mc_make_sec_cfg(ISPWA, NON_SECURE, NO_OVERRIDE, ENABLE), 153*719fdb6eSVarun Wadekar mc_make_sec_cfg(ISPWB, NON_SECURE, NO_OVERRIDE, ENABLE), 154*719fdb6eSVarun Wadekar mc_make_sec_cfg(XUSB_HOSTR, NON_SECURE, OVERRIDE, ENABLE), 155*719fdb6eSVarun Wadekar mc_make_sec_cfg(XUSB_HOSTW, NON_SECURE, OVERRIDE, ENABLE), 156*719fdb6eSVarun Wadekar mc_make_sec_cfg(XUSB_DEVR, NON_SECURE, OVERRIDE, ENABLE), 157*719fdb6eSVarun Wadekar mc_make_sec_cfg(XUSB_DEVW, NON_SECURE, OVERRIDE, ENABLE), 158*719fdb6eSVarun Wadekar mc_make_sec_cfg(TSECSRD, NON_SECURE, NO_OVERRIDE, ENABLE), 159*719fdb6eSVarun Wadekar mc_make_sec_cfg(TSECSWR, NON_SECURE, NO_OVERRIDE, ENABLE), 160*719fdb6eSVarun Wadekar mc_make_sec_cfg(SDMMCRA, NON_SECURE, OVERRIDE, ENABLE), 161*719fdb6eSVarun Wadekar mc_make_sec_cfg(SDMMCR, NON_SECURE, OVERRIDE, ENABLE), 162*719fdb6eSVarun Wadekar mc_make_sec_cfg(SDMMCRAB, NON_SECURE, OVERRIDE, ENABLE), 163*719fdb6eSVarun Wadekar mc_make_sec_cfg(SDMMCWA, NON_SECURE, OVERRIDE, ENABLE), 164*719fdb6eSVarun Wadekar mc_make_sec_cfg(SDMMCW, NON_SECURE, OVERRIDE, ENABLE), 165*719fdb6eSVarun Wadekar mc_make_sec_cfg(SDMMCWAB, NON_SECURE, OVERRIDE, ENABLE), 166*719fdb6eSVarun Wadekar mc_make_sec_cfg(VICSRD, NON_SECURE, NO_OVERRIDE, ENABLE), 167*719fdb6eSVarun Wadekar mc_make_sec_cfg(VICSWR, NON_SECURE, NO_OVERRIDE, ENABLE), 168*719fdb6eSVarun Wadekar mc_make_sec_cfg(VIW, NON_SECURE, NO_OVERRIDE, ENABLE), 169*719fdb6eSVarun Wadekar mc_make_sec_cfg(NVDECSRD, NON_SECURE, NO_OVERRIDE, ENABLE), 170*719fdb6eSVarun Wadekar mc_make_sec_cfg(NVDECSWR, NON_SECURE, NO_OVERRIDE, ENABLE), 171*719fdb6eSVarun Wadekar mc_make_sec_cfg(APER, NON_SECURE, NO_OVERRIDE, ENABLE), 172*719fdb6eSVarun Wadekar mc_make_sec_cfg(APEW, NON_SECURE, NO_OVERRIDE, ENABLE), 173*719fdb6eSVarun Wadekar mc_make_sec_cfg(NVJPGSRD, NON_SECURE, NO_OVERRIDE, ENABLE), 174*719fdb6eSVarun Wadekar mc_make_sec_cfg(NVJPGSWR, NON_SECURE, NO_OVERRIDE, ENABLE), 175*719fdb6eSVarun Wadekar mc_make_sec_cfg(SESRD, NON_SECURE, NO_OVERRIDE, ENABLE), 176*719fdb6eSVarun Wadekar mc_make_sec_cfg(SESWR, NON_SECURE, NO_OVERRIDE, ENABLE), 177*719fdb6eSVarun Wadekar mc_make_sec_cfg(AXIAPR, NON_SECURE, OVERRIDE, ENABLE), 178*719fdb6eSVarun Wadekar mc_make_sec_cfg(AXIAPW, NON_SECURE, OVERRIDE, ENABLE), 179*719fdb6eSVarun Wadekar mc_make_sec_cfg(ETRR, NON_SECURE, OVERRIDE, ENABLE), 180*719fdb6eSVarun Wadekar mc_make_sec_cfg(ETRW, NON_SECURE, OVERRIDE, ENABLE), 181*719fdb6eSVarun Wadekar mc_make_sec_cfg(TSECSRDB, NON_SECURE, NO_OVERRIDE, ENABLE), 182*719fdb6eSVarun Wadekar mc_make_sec_cfg(TSECSWRB, NON_SECURE, NO_OVERRIDE, ENABLE), 183*719fdb6eSVarun Wadekar mc_make_sec_cfg(AXISR, SECURE, NO_OVERRIDE, DISABLE), 184*719fdb6eSVarun Wadekar mc_make_sec_cfg(AXISW, SECURE, NO_OVERRIDE, DISABLE), 185*719fdb6eSVarun Wadekar mc_make_sec_cfg(EQOSR, NON_SECURE, OVERRIDE, ENABLE), 186*719fdb6eSVarun Wadekar mc_make_sec_cfg(EQOSW, NON_SECURE, OVERRIDE, ENABLE), 187*719fdb6eSVarun Wadekar mc_make_sec_cfg(UFSHCR, NON_SECURE, OVERRIDE, ENABLE), 188*719fdb6eSVarun Wadekar mc_make_sec_cfg(UFSHCW, NON_SECURE, OVERRIDE, ENABLE), 189*719fdb6eSVarun Wadekar mc_make_sec_cfg(NVDISPLAYR, NON_SECURE, OVERRIDE, ENABLE), 190*719fdb6eSVarun Wadekar mc_make_sec_cfg(BPMPR, NON_SECURE, NO_OVERRIDE, ENABLE), 191*719fdb6eSVarun Wadekar mc_make_sec_cfg(BPMPW, NON_SECURE, NO_OVERRIDE, ENABLE), 192*719fdb6eSVarun Wadekar mc_make_sec_cfg(BPMPDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), 193*719fdb6eSVarun Wadekar mc_make_sec_cfg(BPMPDMAW, NON_SECURE, NO_OVERRIDE, ENABLE), 194*719fdb6eSVarun Wadekar mc_make_sec_cfg(AONR, NON_SECURE, NO_OVERRIDE, ENABLE), 195*719fdb6eSVarun Wadekar mc_make_sec_cfg(AONW, NON_SECURE, NO_OVERRIDE, ENABLE), 196*719fdb6eSVarun Wadekar mc_make_sec_cfg(AONDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), 197*719fdb6eSVarun Wadekar mc_make_sec_cfg(AONDMAW, NON_SECURE, NO_OVERRIDE, ENABLE), 198*719fdb6eSVarun Wadekar mc_make_sec_cfg(SCER, NON_SECURE, NO_OVERRIDE, ENABLE), 199*719fdb6eSVarun Wadekar mc_make_sec_cfg(SCEW, NON_SECURE, NO_OVERRIDE, ENABLE), 200*719fdb6eSVarun Wadekar mc_make_sec_cfg(SCEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), 201*719fdb6eSVarun Wadekar mc_make_sec_cfg(SCEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE), 202*719fdb6eSVarun Wadekar mc_make_sec_cfg(APEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), 203*719fdb6eSVarun Wadekar mc_make_sec_cfg(APEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE), 204*719fdb6eSVarun Wadekar mc_make_sec_cfg(NVDISPLAYR1, NON_SECURE, OVERRIDE, ENABLE), 205*719fdb6eSVarun Wadekar mc_make_sec_cfg(VICSRD1, NON_SECURE, NO_OVERRIDE, ENABLE), 206*719fdb6eSVarun Wadekar mc_make_sec_cfg(NVDECSRD1, NON_SECURE, NO_OVERRIDE, ENABLE), 207*719fdb6eSVarun Wadekar mc_make_sec_cfg(VIFALR, NON_SECURE, NO_OVERRIDE, ENABLE), 208*719fdb6eSVarun Wadekar mc_make_sec_cfg(VIFALW, NON_SECURE, NO_OVERRIDE, ENABLE), 209*719fdb6eSVarun Wadekar mc_make_sec_cfg(DLA0RDA, NON_SECURE, NO_OVERRIDE, ENABLE), 210*719fdb6eSVarun Wadekar mc_make_sec_cfg(DLA0FALRDB, NON_SECURE, NO_OVERRIDE, ENABLE), 211*719fdb6eSVarun Wadekar mc_make_sec_cfg(DLA0WRA, NON_SECURE, NO_OVERRIDE, ENABLE), 212*719fdb6eSVarun Wadekar mc_make_sec_cfg(DLA0FALWRB, NON_SECURE, NO_OVERRIDE, ENABLE), 213*719fdb6eSVarun Wadekar mc_make_sec_cfg(DLA1RDA, NON_SECURE, NO_OVERRIDE, ENABLE), 214*719fdb6eSVarun Wadekar mc_make_sec_cfg(DLA1FALRDB, NON_SECURE, NO_OVERRIDE, ENABLE), 215*719fdb6eSVarun Wadekar mc_make_sec_cfg(DLA1WRA, NON_SECURE, NO_OVERRIDE, ENABLE), 216*719fdb6eSVarun Wadekar mc_make_sec_cfg(DLA1FALWRB, NON_SECURE, NO_OVERRIDE, ENABLE), 217*719fdb6eSVarun Wadekar mc_make_sec_cfg(PVA0RDA, NON_SECURE, NO_OVERRIDE, ENABLE), 218*719fdb6eSVarun Wadekar mc_make_sec_cfg(PVA0RDB, NON_SECURE, NO_OVERRIDE, ENABLE), 219*719fdb6eSVarun Wadekar mc_make_sec_cfg(PVA0RDC, NON_SECURE, NO_OVERRIDE, ENABLE), 220*719fdb6eSVarun Wadekar mc_make_sec_cfg(PVA0WRA, NON_SECURE, NO_OVERRIDE, ENABLE), 221*719fdb6eSVarun Wadekar mc_make_sec_cfg(PVA0WRB, NON_SECURE, NO_OVERRIDE, ENABLE), 222*719fdb6eSVarun Wadekar mc_make_sec_cfg(PVA0WRC, NON_SECURE, NO_OVERRIDE, ENABLE), 223*719fdb6eSVarun Wadekar mc_make_sec_cfg(PVA1RDA, NON_SECURE, NO_OVERRIDE, ENABLE), 224*719fdb6eSVarun Wadekar mc_make_sec_cfg(PVA1RDB, NON_SECURE, NO_OVERRIDE, ENABLE), 225*719fdb6eSVarun Wadekar mc_make_sec_cfg(PVA1RDC, NON_SECURE, NO_OVERRIDE, ENABLE), 226*719fdb6eSVarun Wadekar mc_make_sec_cfg(PVA1WRA, NON_SECURE, NO_OVERRIDE, ENABLE), 227*719fdb6eSVarun Wadekar mc_make_sec_cfg(PVA1WRB, NON_SECURE, NO_OVERRIDE, ENABLE), 228*719fdb6eSVarun Wadekar mc_make_sec_cfg(PVA1WRC, NON_SECURE, NO_OVERRIDE, ENABLE), 229*719fdb6eSVarun Wadekar mc_make_sec_cfg(RCER, NON_SECURE, NO_OVERRIDE, ENABLE), 230*719fdb6eSVarun Wadekar mc_make_sec_cfg(RCEW, NON_SECURE, NO_OVERRIDE, ENABLE), 231*719fdb6eSVarun Wadekar mc_make_sec_cfg(RCEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), 232*719fdb6eSVarun Wadekar mc_make_sec_cfg(RCEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE), 233*719fdb6eSVarun Wadekar mc_make_sec_cfg(NVENC1SRD, NON_SECURE, NO_OVERRIDE, ENABLE), 234*719fdb6eSVarun Wadekar mc_make_sec_cfg(NVENC1SWR, NON_SECURE, NO_OVERRIDE, ENABLE), 235*719fdb6eSVarun Wadekar mc_make_sec_cfg(PCIE0R, NON_SECURE, OVERRIDE, ENABLE), 236*719fdb6eSVarun Wadekar mc_make_sec_cfg(PCIE0W, NON_SECURE, OVERRIDE, ENABLE), 237*719fdb6eSVarun Wadekar mc_make_sec_cfg(PCIE1R, NON_SECURE, OVERRIDE, ENABLE), 238*719fdb6eSVarun Wadekar mc_make_sec_cfg(PCIE1W, NON_SECURE, OVERRIDE, ENABLE), 239*719fdb6eSVarun Wadekar mc_make_sec_cfg(PCIE2AR, NON_SECURE, OVERRIDE, ENABLE), 240*719fdb6eSVarun Wadekar mc_make_sec_cfg(PCIE2AW, NON_SECURE, OVERRIDE, ENABLE), 241*719fdb6eSVarun Wadekar mc_make_sec_cfg(PCIE3R, NON_SECURE, OVERRIDE, ENABLE), 242*719fdb6eSVarun Wadekar mc_make_sec_cfg(PCIE3W, NON_SECURE, OVERRIDE, ENABLE), 243*719fdb6eSVarun Wadekar mc_make_sec_cfg(PCIE4R, NON_SECURE, OVERRIDE, ENABLE), 244*719fdb6eSVarun Wadekar mc_make_sec_cfg(PCIE4W, NON_SECURE, OVERRIDE, ENABLE), 245*719fdb6eSVarun Wadekar mc_make_sec_cfg(PCIE5R, NON_SECURE, OVERRIDE, ENABLE), 246*719fdb6eSVarun Wadekar mc_make_sec_cfg(PCIE5W, NON_SECURE, OVERRIDE, ENABLE), 247*719fdb6eSVarun Wadekar mc_make_sec_cfg(ISPFALW, NON_SECURE, NO_OVERRIDE, ENABLE), 248*719fdb6eSVarun Wadekar mc_make_sec_cfg(DLA0RDA1, NON_SECURE, NO_OVERRIDE, ENABLE), 249*719fdb6eSVarun Wadekar mc_make_sec_cfg(DLA1RDA1, NON_SECURE, NO_OVERRIDE, ENABLE), 250*719fdb6eSVarun Wadekar mc_make_sec_cfg(PVA0RDA1, NON_SECURE, NO_OVERRIDE, ENABLE), 251*719fdb6eSVarun Wadekar mc_make_sec_cfg(PVA0RDB1, NON_SECURE, NO_OVERRIDE, ENABLE), 252*719fdb6eSVarun Wadekar mc_make_sec_cfg(PVA1RDA1, NON_SECURE, NO_OVERRIDE, ENABLE), 253*719fdb6eSVarun Wadekar mc_make_sec_cfg(PVA1RDB1, NON_SECURE, NO_OVERRIDE, ENABLE), 254*719fdb6eSVarun Wadekar mc_make_sec_cfg(PCIE5R1, NON_SECURE, OVERRIDE, ENABLE), 255*719fdb6eSVarun Wadekar mc_make_sec_cfg(NVENCSRD1, NON_SECURE, NO_OVERRIDE, ENABLE), 256*719fdb6eSVarun Wadekar mc_make_sec_cfg(NVENC1SRD1, NON_SECURE, NO_OVERRIDE, ENABLE), 257*719fdb6eSVarun Wadekar mc_make_sec_cfg(ISPRA1, NON_SECURE, NO_OVERRIDE, ENABLE), 258*719fdb6eSVarun Wadekar mc_make_sec_cfg(MIU0R, NON_SECURE, OVERRIDE, ENABLE), 259*719fdb6eSVarun Wadekar mc_make_sec_cfg(MIU0W, NON_SECURE, OVERRIDE, ENABLE), 260*719fdb6eSVarun Wadekar mc_make_sec_cfg(MIU1R, NON_SECURE, OVERRIDE, ENABLE), 261*719fdb6eSVarun Wadekar mc_make_sec_cfg(MIU1W, NON_SECURE, OVERRIDE, ENABLE), 262*719fdb6eSVarun Wadekar mc_make_sec_cfg(MIU2R, NON_SECURE, OVERRIDE, ENABLE), 263*719fdb6eSVarun Wadekar mc_make_sec_cfg(MIU2W, NON_SECURE, OVERRIDE, ENABLE), 264*719fdb6eSVarun Wadekar mc_make_sec_cfg(MIU3R, NON_SECURE, OVERRIDE, ENABLE), 265*719fdb6eSVarun Wadekar mc_make_sec_cfg(MIU3W, NON_SECURE, OVERRIDE, ENABLE), 266*719fdb6eSVarun Wadekar }; 267*719fdb6eSVarun Wadekar 268*719fdb6eSVarun Wadekar /******************************************************************************* 269*719fdb6eSVarun Wadekar * Array to hold the transaction override configs 270*719fdb6eSVarun Wadekar ******************************************************************************/ 271*719fdb6eSVarun Wadekar const static mc_txn_override_cfg_t tegra194_txn_override_cfgs[] = { 272*719fdb6eSVarun Wadekar mc_make_txn_override_cfg(NVENCSWR, CGID_TAG_ADR), 273*719fdb6eSVarun Wadekar mc_make_txn_override_cfg(HDAW, CGID_TAG_ADR), 274*719fdb6eSVarun Wadekar mc_make_txn_override_cfg(SATAW, CGID_TAG_ADR), 275*719fdb6eSVarun Wadekar mc_make_txn_override_cfg(ISPWB, CGID_TAG_ADR), 276*719fdb6eSVarun Wadekar mc_make_txn_override_cfg(XUSB_HOSTW, CGID_TAG_ADR), 277*719fdb6eSVarun Wadekar mc_make_txn_override_cfg(XUSB_DEVW, CGID_TAG_ADR), 278*719fdb6eSVarun Wadekar mc_make_txn_override_cfg(TSECSWR, CGID_TAG_ADR), 279*719fdb6eSVarun Wadekar mc_make_txn_override_cfg(SDMMCWA, CGID_TAG_ADR), 280*719fdb6eSVarun Wadekar mc_make_txn_override_cfg(SDMMCW, CGID_TAG_ADR), 281*719fdb6eSVarun Wadekar mc_make_txn_override_cfg(SDMMCWAB, CGID_TAG_ADR), 282*719fdb6eSVarun Wadekar mc_make_txn_override_cfg(VICSWR, CGID_TAG_ADR), 283*719fdb6eSVarun Wadekar mc_make_txn_override_cfg(NVDECSWR, CGID_TAG_ADR), 284*719fdb6eSVarun Wadekar mc_make_txn_override_cfg(APEW, CGID_TAG_ADR), 285*719fdb6eSVarun Wadekar mc_make_txn_override_cfg(NVJPGSWR, CGID_TAG_ADR), 286*719fdb6eSVarun Wadekar mc_make_txn_override_cfg(SESWR, CGID_TAG_ADR), 287*719fdb6eSVarun Wadekar mc_make_txn_override_cfg(ETRW, CGID_TAG_ADR), 288*719fdb6eSVarun Wadekar mc_make_txn_override_cfg(TSECSWRB, CGID_TAG_ADR), 289*719fdb6eSVarun Wadekar mc_make_txn_override_cfg(AXISW, CGID_TAG_ADR), 290*719fdb6eSVarun Wadekar mc_make_txn_override_cfg(EQOSW, CGID_TAG_ADR), 291*719fdb6eSVarun Wadekar mc_make_txn_override_cfg(UFSHCW, CGID_TAG_ADR), 292*719fdb6eSVarun Wadekar mc_make_txn_override_cfg(BPMPW, CGID_TAG_ADR), 293*719fdb6eSVarun Wadekar mc_make_txn_override_cfg(BPMPDMAW, CGID_TAG_ADR), 294*719fdb6eSVarun Wadekar mc_make_txn_override_cfg(AONW, CGID_TAG_ADR), 295*719fdb6eSVarun Wadekar mc_make_txn_override_cfg(AONDMAW, CGID_TAG_ADR), 296*719fdb6eSVarun Wadekar mc_make_txn_override_cfg(SCEW, CGID_TAG_ADR), 297*719fdb6eSVarun Wadekar mc_make_txn_override_cfg(SCEDMAW, CGID_TAG_ADR), 298*719fdb6eSVarun Wadekar }; 299*719fdb6eSVarun Wadekar 300*719fdb6eSVarun Wadekar /******************************************************************************* 301*719fdb6eSVarun Wadekar * Struct to hold the memory controller settings 302*719fdb6eSVarun Wadekar ******************************************************************************/ 303*719fdb6eSVarun Wadekar static tegra_mc_settings_t tegra194_mc_settings = { 304*719fdb6eSVarun Wadekar .streamid_override_cfg = tegra194_streamid_override_regs, 305*719fdb6eSVarun Wadekar .num_streamid_override_cfgs = ARRAY_SIZE(tegra194_streamid_override_regs), 306*719fdb6eSVarun Wadekar .streamid_security_cfg = tegra194_streamid_sec_cfgs, 307*719fdb6eSVarun Wadekar .num_streamid_security_cfgs = ARRAY_SIZE(tegra194_streamid_sec_cfgs), 308*719fdb6eSVarun Wadekar .txn_override_cfg = tegra194_txn_override_cfgs, 309*719fdb6eSVarun Wadekar .num_txn_override_cfgs = ARRAY_SIZE(tegra194_txn_override_cfgs) 310*719fdb6eSVarun Wadekar }; 311*719fdb6eSVarun Wadekar 312*719fdb6eSVarun Wadekar /******************************************************************************* 313*719fdb6eSVarun Wadekar * Handler to return the pointer to the memory controller's settings struct 314*719fdb6eSVarun Wadekar ******************************************************************************/ 315*719fdb6eSVarun Wadekar tegra_mc_settings_t *tegra_get_mc_settings(void) 316*719fdb6eSVarun Wadekar { 317*719fdb6eSVarun Wadekar return &tegra194_mc_settings; 318*719fdb6eSVarun Wadekar } 319