1 /* 2 * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __SE_PRIVATE_H__ 8 #define __SE_PRIVATE_H__ 9 10 #include <lib/utils_def.h> 11 12 /* SE0_INT_ENABLE_0 */ 13 #define SE0_INT_ENABLE U(0x88) 14 #define SE0_DISABLE_ALL_INT U(0x0) 15 16 /* SE0_INT_STATUS_0 */ 17 #define SE0_INT_STATUS U(0x8C) 18 #define SE0_CLEAR_ALL_INT_STATUS U(0x3F) 19 20 /* SE0_SHA_INT_STATUS_0 */ 21 #define SHA_INT_STATUS U(0x184) 22 #define SHA_SE_OP_DONE (U(1) << 4) 23 24 /* SE0_SHA_ERR_STATUS_0 */ 25 #define SHA_ERR_STATUS U(0x18C) 26 27 /* SE0_AES0_INT_STATUS_0 */ 28 #define AES0_INT_STATUS U(0x2F0) 29 #define AES0_SE_OP_DONE (U(1) << 4) 30 31 /* SE0_AES0_ERR_STATUS_0 */ 32 #define AES0_ERR_STATUS U(0x2F8) 33 34 /* SE0_AES1_INT_STATUS_0 */ 35 #define AES1_INT_STATUS U(0x4F0) 36 37 /* SE0_AES1_ERR_STATUS_0 */ 38 #define AES1_ERR_STATUS U(0x4F8) 39 40 /* SE0_RSA_INT_STATUS_0 */ 41 #define RSA_INT_STATUS U(0x758) 42 43 /* SE0_RSA_ERR_STATUS_0 */ 44 #define RSA_ERR_STATUS U(0x760) 45 46 /* SE0_AES0_OPERATION_0 */ 47 #define AES0_OPERATION U(0x238) 48 #define OP_MASK_BITS U(0x7) 49 #define SE_OP_CTX_SAVE U(0x3) 50 51 /* SE0_AES0_CTX_SAVE_CONFIG_0 */ 52 #define CTX_SAVE_CONFIG U(0x2D4) 53 54 /* SE0_AES0_CTX_SAVE_AUTO_STATUS_0 */ 55 #define CTX_SAVE_AUTO_STATUS U(0x300) 56 #define CTX_SAVE_AUTO_SE_READY U(0xFF) 57 #define CTX_SAVE_AUTO_SE_BUSY (U(0x1) << 31) 58 59 /* SE0_AES0_CTX_SAVE_AUTO_CTRL_0 */ 60 #define CTX_SAVE_AUTO_CTRL U(0x304) 61 #define SE_CTX_SAVE_AUTO_EN (U(0x1) << 0) 62 #define SE_CTX_SAVE_AUTO_LOCK_EN (U(0x1) << 1) 63 64 /* SE0_AES0_CTX_SAVE_AUTO_START_ADDR_0 */ 65 #define CTX_SAVE_AUTO_START_ADDR U(0x308) 66 67 /* SE0_AES0_CTX_SAVE_AUTO_START_ADDR_HI_0 */ 68 #define CTX_SAVE_AUTO_START_ADDR_HI U(0x30C) 69 70 /******************************************************************************* 71 * Inline functions definition 72 ******************************************************************************/ 73 74 static inline uint32_t tegra_se_read_32(uint32_t offset) 75 { 76 return mmio_read_32(TEGRA_SE0_BASE + offset); 77 } 78 79 static inline void tegra_se_write_32(uint32_t offset, uint32_t val) 80 { 81 mmio_write_32(TEGRA_SE0_BASE + offset, val); 82 } 83 84 #endif /* __SE_PRIVATE_H__ */ 85