1 /* 2 * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <errno.h> 10 #include <stdbool.h> 11 12 #include <arch_helpers.h> 13 #include <bpmp_ipc.h> 14 #include <common/debug.h> 15 #include <drivers/delay_timer.h> 16 #include <lib/mmio.h> 17 #include <lib/psci/psci.h> 18 #include <se.h> 19 #include <tegra_platform.h> 20 21 #include "se_private.h" 22 23 /******************************************************************************* 24 * Constants and Macros 25 ******************************************************************************/ 26 #define ERR_STATUS_SW_CLEAR U(0xFFFFFFFF) 27 #define INT_STATUS_SW_CLEAR U(0xFFFFFFFF) 28 #define MAX_TIMEOUT_MS U(100) /* Timeout in 100ms */ 29 #define NUM_SE_REGS_TO_SAVE U(4) 30 31 /******************************************************************************* 32 * Data structure and global variables 33 ******************************************************************************/ 34 static uint32_t se_regs[NUM_SE_REGS_TO_SAVE]; 35 36 /* 37 * Check that SE operation has completed after kickoff. 38 * 39 * This function is invoked after an SE operation has been started, 40 * and it checks the following conditions: 41 * 42 * 1. SE_STATUS = IDLE 43 * 2. AHB bus data transfer is complete. 44 * 3. SE_ERR_STATUS is clean. 45 */ 46 static bool tegra_se_is_operation_complete(void) 47 { 48 uint32_t val = 0, timeout = 0, sha_status, aes_status; 49 int32_t ret = 0; 50 bool se_is_busy, txn_has_errors, txn_successful; 51 52 /* 53 * Poll the status register to check if the operation 54 * completed. 55 */ 56 do { 57 val = tegra_se_read_32(CTX_SAVE_AUTO_STATUS); 58 se_is_busy = ((val & CTX_SAVE_AUTO_SE_BUSY) != 0U); 59 60 /* sleep until SE finishes */ 61 if (se_is_busy) { 62 mdelay(1); 63 timeout++; 64 } 65 66 } while (se_is_busy && (timeout < MAX_TIMEOUT_MS)); 67 68 /* any transaction errors? */ 69 txn_has_errors = (tegra_se_read_32(SHA_ERR_STATUS) != 0U) || 70 (tegra_se_read_32(AES0_ERR_STATUS) != 0U); 71 72 /* transaction successful? */ 73 sha_status = tegra_se_read_32(SHA_INT_STATUS) & SHA_SE_OP_DONE; 74 aes_status = tegra_se_read_32(AES0_INT_STATUS) & AES0_SE_OP_DONE; 75 txn_successful = (sha_status == SHA_SE_OP_DONE) && 76 (aes_status == AES0_SE_OP_DONE); 77 78 if ((timeout == MAX_TIMEOUT_MS) || txn_has_errors || !txn_successful) { 79 ERROR("%s: Atomic context save operation failed!\n", 80 __func__); 81 ret = -ECANCELED; 82 } 83 84 return (ret == 0); 85 } 86 87 /* 88 * Wait for SE engine to be idle and clear any pending interrupts, before 89 * starting the next SE operation. 90 */ 91 static bool tegra_se_is_ready(void) 92 { 93 int32_t ret = 0; 94 uint32_t val = 0, timeout = 0; 95 bool se_is_ready; 96 97 /* Wait for previous operation to finish */ 98 do { 99 val = tegra_se_read_32(CTX_SAVE_AUTO_STATUS); 100 se_is_ready = (val == CTX_SAVE_AUTO_SE_READY); 101 102 /* sleep until SE is ready */ 103 if (!se_is_ready) { 104 mdelay(1); 105 timeout++; 106 } 107 108 } while (!se_is_ready && (timeout < MAX_TIMEOUT_MS)); 109 110 if (timeout == MAX_TIMEOUT_MS) { 111 ERROR("%s: SE is not ready!\n", __func__); 112 ret = -ETIMEDOUT; 113 } 114 115 /* Clear any pending interrupts from previous operation */ 116 tegra_se_write_32(AES0_INT_STATUS, INT_STATUS_SW_CLEAR); 117 tegra_se_write_32(AES1_INT_STATUS, INT_STATUS_SW_CLEAR); 118 tegra_se_write_32(RSA_INT_STATUS, INT_STATUS_SW_CLEAR); 119 tegra_se_write_32(SHA_INT_STATUS, INT_STATUS_SW_CLEAR); 120 121 /* Clear error status for each engine seen from current port */ 122 tegra_se_write_32(AES0_ERR_STATUS, ERR_STATUS_SW_CLEAR); 123 tegra_se_write_32(AES1_ERR_STATUS, ERR_STATUS_SW_CLEAR); 124 tegra_se_write_32(RSA_ERR_STATUS, ERR_STATUS_SW_CLEAR); 125 tegra_se_write_32(SHA_ERR_STATUS, ERR_STATUS_SW_CLEAR); 126 127 return (ret == 0); 128 } 129 130 /* 131 * During System Suspend, this handler triggers the hardware context 132 * save operation. 133 */ 134 static int32_t tegra_se_save_context(void) 135 { 136 int32_t ret = -ECANCELED; 137 138 /* 139 * 1. Ensure all SE Driver including RNG1/PKA1 are shut down. 140 * TSEC/R5s are powergated/idle. All tasks on SE1~SE4, RNG1, 141 * PKA1 are wrapped up. SE0 is ready for use. 142 * 2. Clear interrupt/error in SE0 status register. 143 * 3. Scrub SE0 register to avoid false failure for illegal 144 * configuration. Probably not needed, dependent on HW 145 * implementation. 146 * 4. Check SE is ready for HW CTX_SAVE by polling 147 * SE_CTX_SAVE_AUTO_STATUS.SE_READY. 148 * 149 * Steps 1-4 are executed by tegra_se_is_ready(). 150 * 151 * 5. Issue context save command. 152 * 6. Check SE is busy with CTX_SAVE, the command in step5 was not 153 * dropped for ongoing traffic in any of SE port/engine. 154 * 7. Poll SE register or wait for SE APB interrupt for task completion 155 * a. Polling: Read SE_CTX_SAVE_AUTO_STATUS.BUSY till it reports IDLE 156 * b. Interrupt: After receiving interrupt from SE APB, read 157 * SE_CTX_SAVE_AUTO_STATUS.BUSY till it reports IDLE. 158 * 8. Check AES0 and SHA ERR_STATUS to ensure no error case. 159 * 9. Check AES0 and SHA INT_STATUS to ensure operation has successfully 160 * completed. 161 * 162 * Steps 6-9 are executed by tegra_se_is_operation_complete(). 163 */ 164 if (tegra_se_is_ready()) { 165 166 /* Issue context save command */ 167 tegra_se_write_32(AES0_OPERATION, SE_OP_CTX_SAVE); 168 169 /* Wait for operation to finish */ 170 if (tegra_se_is_operation_complete()) { 171 ret = 0; 172 } 173 } 174 175 return ret; 176 } 177 178 /* 179 * Handler to power down the SE hardware blocks - SE, RNG1 and PKA1. This 180 * needs to be called only during System Suspend. 181 */ 182 int32_t tegra_se_suspend(void) 183 { 184 int32_t ret = 0; 185 186 /* initialise communication channel with BPMP */ 187 assert(tegra_bpmp_ipc_init() == 0); 188 189 /* Enable SE clock before SE context save */ 190 ret = tegra_bpmp_ipc_enable_clock(TEGRA_CLK_SE); 191 assert(ret == 0); 192 193 /* save SE registers */ 194 se_regs[0] = mmio_read_32(TEGRA_SE0_BASE + SE0_MUTEX_WATCHDOG_NS_LIMIT); 195 se_regs[1] = mmio_read_32(TEGRA_SE0_BASE + SE0_AES0_ENTROPY_SRC_AGE_CTRL); 196 se_regs[2] = mmio_read_32(TEGRA_RNG1_BASE + RNG1_MUTEX_WATCHDOG_NS_LIMIT); 197 se_regs[3] = mmio_read_32(TEGRA_PKA1_BASE + PKA1_MUTEX_WATCHDOG_NS_LIMIT); 198 199 /* Save SE context. The BootROM restores it during System Resume */ 200 ret = tegra_se_save_context(); 201 if (ret != 0) { 202 ERROR("%s: context save failed (%d)\n", __func__, ret); 203 } 204 205 /* Disable SE clock after SE context save */ 206 ret = tegra_bpmp_ipc_disable_clock(TEGRA_CLK_SE); 207 assert(ret == 0); 208 209 return ret; 210 } 211 212 /* 213 * Handler to power up the SE hardware block(s) during System Resume. 214 */ 215 void tegra_se_resume(void) 216 { 217 int32_t ret = 0; 218 219 /* initialise communication channel with BPMP */ 220 assert(tegra_bpmp_ipc_init() == 0); 221 222 /* Enable SE clock before SE context restore */ 223 ret = tegra_bpmp_ipc_enable_clock(TEGRA_CLK_SE); 224 assert(ret == 0); 225 226 /* 227 * When TZ takes over after System Resume, TZ should first reconfigure 228 * SE_MUTEX_WATCHDOG_NS_LIMIT, PKA1_MUTEX_WATCHDOG_NS_LIMIT, 229 * RNG1_MUTEX_WATCHDOG_NS_LIMIT and SE_ENTROPY_SRC_AGE_CTRL before 230 * other operations. 231 */ 232 mmio_write_32(TEGRA_SE0_BASE + SE0_MUTEX_WATCHDOG_NS_LIMIT, se_regs[0]); 233 mmio_write_32(TEGRA_SE0_BASE + SE0_AES0_ENTROPY_SRC_AGE_CTRL, se_regs[1]); 234 mmio_write_32(TEGRA_RNG1_BASE + RNG1_MUTEX_WATCHDOG_NS_LIMIT, se_regs[2]); 235 mmio_write_32(TEGRA_PKA1_BASE + PKA1_MUTEX_WATCHDOG_NS_LIMIT, se_regs[3]); 236 237 /* Disable SE clock after SE context restore */ 238 ret = tegra_bpmp_ipc_disable_clock(TEGRA_CLK_SE); 239 assert(ret == 0); 240 } 241