1 /* 2 * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <common/debug.h> 10 #include <denver.h> 11 #include <errno.h> 12 #include <lib/mmio.h> 13 #include <mce_private.h> 14 #include <platform_def.h> 15 #include <t194_nvg.h> 16 #include <tegra_private.h> 17 18 #define ID_AFR0_EL1_CACHE_OPS_SHIFT 12 19 #define ID_AFR0_EL1_CACHE_OPS_MASK 0xFU 20 /* 21 * Reports the major and minor version of this interface. 22 * 23 * NVGDATA[0:31]: SW(R) Minor Version 24 * NVGDATA[32:63]: SW(R) Major Version 25 */ 26 uint64_t nvg_get_version(void) 27 { 28 nvg_set_request((uint64_t)TEGRA_NVG_CHANNEL_VERSION); 29 30 return (uint64_t)nvg_get_result(); 31 } 32 33 /* 34 * Enable the perf per watt mode. 35 * 36 * NVGDATA[0]: SW(RW), 1 = enable perf per watt mode 37 */ 38 int32_t nvg_enable_power_perf_mode(void) 39 { 40 nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_POWER_PERF, 1U); 41 42 return 0; 43 } 44 45 /* 46 * Disable the perf per watt mode. 47 * 48 * NVGDATA[0]: SW(RW), 0 = disable perf per watt mode 49 */ 50 int32_t nvg_disable_power_perf_mode(void) 51 { 52 nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_POWER_PERF, 0U); 53 54 return 0; 55 } 56 57 /* 58 * Enable the battery saver mode. 59 * 60 * NVGDATA[2]: SW(RW), 1 = enable battery saver mode 61 */ 62 int32_t nvg_enable_power_saver_modes(void) 63 { 64 nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_POWER_MODES, 1U); 65 66 return 0; 67 } 68 69 /* 70 * Disable the battery saver mode. 71 * 72 * NVGDATA[2]: SW(RW), 0 = disable battery saver mode 73 */ 74 int32_t nvg_disable_power_saver_modes(void) 75 { 76 nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_POWER_MODES, 0U); 77 78 return 0; 79 } 80 81 /* 82 * Set the expected wake time in TSC ticks for the next low-power state the 83 * core enters. 84 * 85 * NVGDATA[0:31]: SW(RW), WAKE_TIME 86 */ 87 void nvg_set_wake_time(uint32_t wake_time) 88 { 89 /* time (TSC ticks) until the core is expected to get a wake event */ 90 nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_WAKE_TIME, (uint64_t)wake_time); 91 } 92 93 /* 94 * This request allows updating of CLUSTER_CSTATE, CCPLEX_CSTATE and 95 * SYSTEM_CSTATE values. 96 * 97 * NVGDATA[0:2]: SW(RW), CLUSTER_CSTATE 98 * NVGDATA[7]: SW(W), update cluster flag 99 * NVGDATA[8:10]: SW(RW), CG_CSTATE 100 * NVGDATA[15]: SW(W), update ccplex flag 101 * NVGDATA[16:19]: SW(RW), SYSTEM_CSTATE 102 * NVGDATA[23]: SW(W), update system flag 103 * NVGDATA[31]: SW(W), update wake mask flag 104 * NVGDATA[32:63]: SW(RW), WAKE_MASK 105 */ 106 void nvg_update_cstate_info(uint32_t cluster, uint32_t ccplex, 107 uint32_t system, uint32_t wake_mask, uint8_t update_wake_mask) 108 { 109 uint64_t val = 0; 110 111 /* update CLUSTER_CSTATE? */ 112 if (cluster != 0U) { 113 val |= ((uint64_t)cluster & CLUSTER_CSTATE_MASK) | 114 CLUSTER_CSTATE_UPDATE_BIT; 115 } 116 117 /* update CCPLEX_CSTATE? */ 118 if (ccplex != 0U) { 119 val |= (((uint64_t)ccplex & CCPLEX_CSTATE_MASK) << CCPLEX_CSTATE_SHIFT) | 120 CCPLEX_CSTATE_UPDATE_BIT; 121 } 122 123 /* update SYSTEM_CSTATE? */ 124 if (system != 0U) { 125 val |= (((uint64_t)system & SYSTEM_CSTATE_MASK) << SYSTEM_CSTATE_SHIFT) | 126 SYSTEM_CSTATE_UPDATE_BIT; 127 } 128 129 /* update wake mask value? */ 130 if (update_wake_mask != 0U) { 131 val |= CSTATE_WAKE_MASK_UPDATE_BIT; 132 } 133 134 /* set the wake mask */ 135 val |= ((uint64_t)wake_mask & CSTATE_WAKE_MASK_CLEAR) << CSTATE_WAKE_MASK_SHIFT; 136 137 /* set the updated cstate info */ 138 nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_CSTATE_INFO, val); 139 } 140 141 /* 142 * Return a non-zero value if the CCPLEX is able to enter SC7 143 * 144 * NVGDATA[0]: SW(R), Is allowed result 145 */ 146 int32_t nvg_is_sc7_allowed(void) 147 { 148 /* issue command to check if SC7 is allowed */ 149 nvg_set_request((uint64_t)TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED); 150 151 /* 1 = SC7 allowed, 0 = SC7 not allowed */ 152 return (int32_t)nvg_get_result(); 153 } 154 155 /* 156 * Wake an offlined logical core. Note that a core is offlined by entering 157 * a C-state where the WAKE_MASK is all 0. 158 * 159 * NVGDATA[0:3]: SW(W) logical core to online 160 */ 161 int32_t nvg_online_core(uint32_t core) 162 { 163 int32_t ret = 0; 164 165 /* sanity check the core ID value */ 166 if (core > (uint32_t)PLATFORM_CORE_COUNT) { 167 ERROR("%s: unknown core id (%d)\n", __func__, core); 168 ret = EINVAL; 169 } else { 170 /* get a core online */ 171 nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_ONLINE_CORE, 172 (uint64_t)core & MCE_CORE_ID_MASK); 173 } 174 175 return ret; 176 } 177 178 /* 179 * MC GSC (General Security Carveout) register values are expected to be 180 * changed by TrustZone ARM code after boot. 181 * 182 * NVGDATA[0:15] SW(R) GSC enun 183 */ 184 int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx) 185 { 186 int32_t ret; 187 188 /* sanity check GSC ID */ 189 if (gsc_idx > (uint32_t)TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR) { 190 ERROR("%s: unknown gsc_idx (%u)\n", __func__, gsc_idx); 191 ret = EINVAL; 192 } else { 193 nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC, 194 (uint64_t)gsc_idx); 195 } 196 197 return ret; 198 } 199 200 /* 201 * Cache clean operation for all CCPLEX caches. 202 */ 203 int32_t nvg_roc_clean_cache(void) 204 { 205 int32_t ret = 0; 206 207 /* check if cache flush through mts is supported */ 208 if (((read_id_afr0_el1() >> ID_AFR0_EL1_CACHE_OPS_SHIFT) & 209 ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) { 210 if (nvg_cache_clean() == 0U) { 211 ERROR("%s: failed\n", __func__); 212 ret = EINVAL; 213 } 214 } else { 215 ret = EINVAL; 216 } 217 return ret; 218 } 219 220 /* 221 * Cache clean and invalidate operation for all CCPLEX caches. 222 */ 223 int32_t nvg_roc_flush_cache(void) 224 { 225 int32_t ret = 0; 226 227 /* check if cache flush through mts is supported */ 228 if (((read_id_afr0_el1() >> ID_AFR0_EL1_CACHE_OPS_SHIFT) & 229 ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) { 230 if (nvg_cache_clean_inval() == 0U) { 231 ERROR("%s: failed\n", __func__); 232 ret = EINVAL; 233 } 234 } else { 235 ret = EINVAL; 236 } 237 return ret; 238 } 239 240 /* 241 * Cache clean and invalidate, clear TR-bit operation for all CCPLEX caches. 242 */ 243 int32_t nvg_roc_clean_cache_trbits(void) 244 { 245 int32_t ret = 0; 246 247 /* check if cache flush through mts is supported */ 248 if (((read_id_afr0_el1() >> ID_AFR0_EL1_CACHE_OPS_SHIFT) & 249 ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) { 250 if (nvg_cache_inval_all() == 0U) { 251 ERROR("%s: failed\n", __func__); 252 ret = EINVAL; 253 } 254 } else { 255 ret = EINVAL; 256 } 257 return ret; 258 } 259 260 /* 261 * Set the power state for a core 262 */ 263 int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time) 264 { 265 int32_t ret = 0; 266 uint64_t val = 0ULL; 267 268 /* check for allowed power state */ 269 if ((state != (uint32_t)TEGRA_NVG_CORE_C0) && 270 (state != (uint32_t)TEGRA_NVG_CORE_C1) && 271 (state != (uint32_t)TEGRA_NVG_CORE_C6) && 272 (state != (uint32_t)TEGRA_NVG_CORE_C7)) 273 { 274 ERROR("%s: unknown cstate (%d)\n", __func__, state); 275 ret = EINVAL; 276 } else { 277 /* time (TSC ticks) until the core is expected to get a wake event */ 278 nvg_set_wake_time(wake_time); 279 280 /* set the core cstate */ 281 val = read_actlr_el1() & ~ACTLR_EL1_PMSTATE_MASK; 282 write_actlr_el1(val | (uint64_t)state); 283 } 284 285 return ret; 286 } 287 288 /* 289 * Enable strict checking mode 290 * 291 * NVGDATA[3] strict_check ON + lock 292 */ 293 void nvg_enable_strict_checking_mode(void) 294 { 295 uint64_t params = (uint64_t)(STRICT_CHECKING_ENABLED_SET | 296 STRICT_CHECKING_LOCKED_SET); 297 298 nvg_set_request_data(TEGRA_NVG_CHANNEL_SECURITY_CONFIG, params); 299 } 300