1 /* 2 * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <common/debug.h> 10 #include <denver.h> 11 #include <errno.h> 12 #include <lib/mmio.h> 13 #include <mce_private.h> 14 #include <platform_def.h> 15 #include <t194_nvg.h> 16 17 extern void nvg_set_request_data(uint64_t req, uint64_t data); 18 extern void nvg_set_request(uint64_t req); 19 extern uint64_t nvg_get_result(void); 20 21 /* 22 * Reports the major and minor version of this interface. 23 * 24 * NVGDATA[0:31]: SW(R) Minor Version 25 * NVGDATA[32:63]: SW(R) Major Version 26 */ 27 uint64_t nvg_get_version(void) 28 { 29 nvg_set_request(TEGRA_NVG_CHANNEL_VERSION); 30 31 return (uint64_t)nvg_get_result(); 32 } 33 34 /* 35 * Enable the perf per watt mode. 36 * 37 * NVGDATA[0]: SW(RW), 1 = enable perf per watt mode 38 */ 39 int32_t nvg_enable_power_perf_mode(void) 40 { 41 nvg_set_request_data(TEGRA_NVG_CHANNEL_POWER_PERF, 1U); 42 43 return 0; 44 } 45 46 /* 47 * Disable the perf per watt mode. 48 * 49 * NVGDATA[0]: SW(RW), 0 = disable perf per watt mode 50 */ 51 int32_t nvg_disable_power_perf_mode(void) 52 { 53 nvg_set_request_data(TEGRA_NVG_CHANNEL_POWER_PERF, 0U); 54 55 return 0; 56 } 57 58 /* 59 * Enable the battery saver mode. 60 * 61 * NVGDATA[2]: SW(RW), 1 = enable battery saver mode 62 */ 63 int32_t nvg_enable_power_saver_modes(void) 64 { 65 nvg_set_request_data(TEGRA_NVG_CHANNEL_POWER_MODES, 1U); 66 67 return 0; 68 } 69 70 /* 71 * Disable the battery saver mode. 72 * 73 * NVGDATA[2]: SW(RW), 0 = disable battery saver mode 74 */ 75 int32_t nvg_disable_power_saver_modes(void) 76 { 77 nvg_set_request_data(TEGRA_NVG_CHANNEL_POWER_MODES, 0U); 78 79 return 0; 80 } 81 82 /* 83 * Set the expected wake time in TSC ticks for the next low-power state the 84 * core enters. 85 * 86 * NVGDATA[0:31]: SW(RW), WAKE_TIME 87 */ 88 void nvg_set_wake_time(uint32_t wake_time) 89 { 90 /* time (TSC ticks) until the core is expected to get a wake event */ 91 nvg_set_request_data(TEGRA_NVG_CHANNEL_WAKE_TIME, (uint64_t)wake_time); 92 } 93 94 /* 95 * This request allows updating of CLUSTER_CSTATE, CCPLEX_CSTATE and 96 * SYSTEM_CSTATE values. 97 * 98 * NVGDATA[0:2]: SW(RW), CLUSTER_CSTATE 99 * NVGDATA[7]: SW(W), update cluster flag 100 * NVGDATA[8:9]: SW(RW), CG_CSTATE 101 * NVGDATA[15]: SW(W), update ccplex flag 102 * NVGDATA[16:19]: SW(RW), SYSTEM_CSTATE 103 * NVGDATA[23]: SW(W), update system flag 104 * NVGDATA[31]: SW(W), update wake mask flag 105 * NVGDATA[32:63]: SW(RW), WAKE_MASK 106 */ 107 void nvg_update_cstate_info(uint32_t cluster, uint32_t ccplex, 108 uint32_t system, uint32_t wake_mask, uint8_t update_wake_mask) 109 { 110 uint64_t val = 0; 111 112 /* update CLUSTER_CSTATE? */ 113 if (cluster != 0U) { 114 val |= ((uint64_t)cluster & CLUSTER_CSTATE_MASK) | 115 CLUSTER_CSTATE_UPDATE_BIT; 116 } 117 118 /* update CCPLEX_CSTATE? */ 119 if (ccplex != 0U) { 120 val |= (((uint64_t)ccplex & CCPLEX_CSTATE_MASK) << CCPLEX_CSTATE_SHIFT) | 121 CCPLEX_CSTATE_UPDATE_BIT; 122 } 123 124 /* update SYSTEM_CSTATE? */ 125 if (system != 0U) { 126 val |= (((uint64_t)system & SYSTEM_CSTATE_MASK) << SYSTEM_CSTATE_SHIFT) | 127 SYSTEM_CSTATE_UPDATE_BIT; 128 } 129 130 /* update wake mask value? */ 131 if (update_wake_mask != 0U) { 132 val |= CSTATE_WAKE_MASK_UPDATE_BIT; 133 } 134 135 /* set the wake mask */ 136 val |= ((uint64_t)wake_mask & CSTATE_WAKE_MASK_CLEAR) << CSTATE_WAKE_MASK_SHIFT; 137 138 /* set the updated cstate info */ 139 nvg_set_request_data(TEGRA_NVG_CHANNEL_CSTATE_INFO, val); 140 } 141 142 /* 143 * Indices gives MTS the crossover point in TSC ticks for when it becomes 144 * no longer viable to enter the named state 145 * 146 * Type 0 : NVGDATA[0:31]: C6 Lower bound 147 * Type 1 : NVGDATA[0:31]: CC6 Lower bound 148 * Type 2 : NVGDATA[0:31]: CG7 Lower bound 149 */ 150 int32_t nvg_update_crossover_time(uint32_t type, uint32_t time) 151 { 152 int32_t ret = 0; 153 154 switch (type) { 155 case TEGRA_NVG_CROSSOVER_C6: 156 nvg_set_request_data(TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND, 157 (uint64_t)time); 158 break; 159 160 case TEGRA_NVG_CROSSOVER_CC6: 161 nvg_set_request_data(TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND, 162 (uint64_t)time); 163 break; 164 165 case TEGRA_NVG_CROSSOVER_CG7: 166 nvg_set_request_data(TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND, 167 (uint64_t)time); 168 break; 169 170 default: 171 ERROR("%s: unknown crossover type (%d)\n", __func__, type); 172 ret = EINVAL; 173 break; 174 } 175 176 return ret; 177 } 178 179 /* 180 * These NVG calls allow ARM SW to access CSTATE statistical information 181 * 182 * NVGDATA[0:3]: SW(RW) Core/cluster/cg id 183 * NVGDATA[16:31]: SW(RW) Stat id 184 */ 185 int32_t nvg_set_cstate_stat_query_value(uint64_t data) 186 { 187 int32_t ret = 0; 188 189 /* sanity check stat id */ 190 if (data > (uint64_t)NVG_STAT_QUERY_C7_RESIDENCY_SUM) { 191 ERROR("%s: unknown stat id (%d)\n", __func__, (uint32_t)data); 192 ret = EINVAL; 193 } else { 194 nvg_set_request_data(TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_REQUEST, data); 195 } 196 197 return ret; 198 } 199 200 /* 201 * The read-only value associated with the CSTATE_STAT_QUERY_REQUEST 202 * 203 * NVGDATA[0:63]: SW(R) Stat count 204 */ 205 uint64_t nvg_get_cstate_stat_query_value(void) 206 { 207 nvg_set_request(TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_VALUE); 208 209 return (uint64_t)nvg_get_result(); 210 } 211 212 /* 213 * Return a non-zero value if the CCPLEX is able to enter SC7 214 * 215 * NVGDATA[0]: SW(R), Is allowed result 216 */ 217 int32_t nvg_is_sc7_allowed(void) 218 { 219 /* issue command to check if SC7 is allowed */ 220 nvg_set_request(TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED); 221 222 /* 1 = SC7 allowed, 0 = SC7 not allowed */ 223 return (int32_t)nvg_get_result(); 224 } 225 226 /* 227 * Wake an offlined logical core. Note that a core is offlined by entering 228 * a C-state where the WAKE_MASK is all 0. 229 * 230 * NVGDATA[0:3]: SW(W) logical core to online 231 */ 232 int32_t nvg_online_core(uint32_t core) 233 { 234 int32_t ret = 0; 235 236 /* sanity check the core ID value */ 237 if (core > (uint32_t)PLATFORM_CORE_COUNT) { 238 ERROR("%s: unknown core id (%d)\n", __func__, core); 239 ret = EINVAL; 240 } else { 241 /* get a core online */ 242 nvg_set_request_data(TEGRA_NVG_CHANNEL_ONLINE_CORE, 243 (uint64_t)core & MCE_CORE_ID_MASK); 244 } 245 246 return ret; 247 } 248 249 /* 250 * Enables and controls the voltage/frequency hint for CC3. CC3 is disabled 251 * by default. 252 * 253 * NVGDATA[7:0] SW(RW) frequency request 254 * NVGDATA[31:31] SW(RW) enable bit 255 */ 256 int32_t nvg_cc3_ctrl(uint32_t freq, uint8_t enable) 257 { 258 uint64_t val = 0; 259 260 /* 261 * If the enable bit is cleared, Auto-CC3 will be disabled by setting 262 * the SW visible frequency request registers for all non 263 * floorswept cores valid independent of StandbyWFI and disabling 264 * the IDLE frequency request register. If set, Auto-CC3 265 * will be enabled by setting the ARM SW visible frequency 266 * request registers for all non floorswept cores to be enabled by 267 * StandbyWFI or the equivalent signal, and always keeping the IDLE 268 * frequency request register enabled. 269 */ 270 if (enable != 0U) { 271 val = ((uint64_t)freq & MCE_AUTO_CC3_FREQ_MASK) | MCE_AUTO_CC3_ENABLE_BIT; 272 } 273 nvg_set_request_data(TEGRA_NVG_CHANNEL_CC3_CTRL, val); 274 275 return 0; 276 } 277 278 /* 279 * MC GSC (General Security Carveout) register values are expected to be 280 * changed by TrustZone ARM code after boot. 281 * 282 * NVGDATA[0:15] SW(R) GSC enun 283 */ 284 int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx) 285 { 286 int32_t ret = 0; 287 288 /* sanity check GSC ID */ 289 if (gsc_idx > (uint32_t)TEGRA_NVG_GSC_VPR_IDX) { 290 ERROR("%s: unknown gsc_idx (%d)\n", __func__, gsc_idx); 291 ret = EINVAL; 292 } else { 293 nvg_set_request_data(TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC, 294 (uint64_t)gsc_idx); 295 } 296 297 return ret; 298 } 299 300 /* 301 * Cache clean operation for all CCPLEX caches. 302 * 303 * NVGDATA[0] cache_clean 304 */ 305 int32_t nvg_roc_clean_cache(void) 306 { 307 nvg_set_request_data(TEGRA_NVG_CHANNEL_CCPLEX_CACHE_INVAL, 308 (uint64_t)CACHE_CLEAN_SET); 309 310 return 0; 311 } 312 313 /* 314 * Cache clean and invalidate operation for all CCPLEX caches. 315 * 316 * NVGDATA[1] cache_clean_inval 317 */ 318 int32_t nvg_roc_flush_cache(void) 319 { 320 nvg_set_request_data(TEGRA_NVG_CHANNEL_CCPLEX_CACHE_INVAL, 321 (uint64_t)CACHE_CLEAN_INVAL_SET); 322 323 return 0; 324 } 325 326 /* 327 * Cache clean and invalidate, clear TR-bit operation for all CCPLEX caches. 328 * 329 * NVGDATA[2] cache_clean_inval_tr 330 */ 331 int32_t nvg_roc_clean_cache_trbits(void) 332 { 333 nvg_set_request_data(TEGRA_NVG_CHANNEL_CCPLEX_CACHE_INVAL, 334 (uint64_t)CACHE_CLEAN_INVAL_TR_SET); 335 336 return 0; 337 } 338 339 /* 340 * Set the power state for a core 341 */ 342 int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time) 343 { 344 int32_t ret = 0; 345 346 /* check for allowed power state */ 347 if ((state != (uint32_t)TEGRA_NVG_CORE_C0) && 348 (state != (uint32_t)TEGRA_NVG_CORE_C1) && 349 (state != (uint32_t)TEGRA_NVG_CORE_C6) && 350 (state != (uint32_t)TEGRA_NVG_CORE_C7)) 351 { 352 ERROR("%s: unknown cstate (%d)\n", __func__, state); 353 ret = EINVAL; 354 } else { 355 /* time (TSC ticks) until the core is expected to get a wake event */ 356 nvg_set_wake_time(wake_time); 357 358 /* set the core cstate */ 359 write_actlr_el1(state); 360 } 361 362 return ret; 363 } 364