1 /* 2 * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <common/debug.h> 10 #include <denver.h> 11 #include <errno.h> 12 #include <lib/mmio.h> 13 #include <mce_private.h> 14 #include <platform_def.h> 15 #include <t194_nvg.h> 16 #include <tegra_private.h> 17 18 #define ID_AFR0_EL1_CACHE_OPS_SHIFT U(12) 19 #define ID_AFR0_EL1_CACHE_OPS_MASK U(0xF) 20 /* 21 * Reports the major and minor version of this interface. 22 * 23 * NVGDATA[0:31]: SW(R) Minor Version 24 * NVGDATA[32:63]: SW(R) Major Version 25 */ 26 uint64_t nvg_get_version(void) 27 { 28 nvg_set_request((uint64_t)TEGRA_NVG_CHANNEL_VERSION); 29 30 return (uint64_t)nvg_get_result(); 31 } 32 33 /* 34 * Set the expected wake time in TSC ticks for the next low-power state the 35 * core enters. 36 * 37 * NVGDATA[0:31]: SW(RW), WAKE_TIME 38 */ 39 void nvg_set_wake_time(uint32_t wake_time) 40 { 41 /* time (TSC ticks) until the core is expected to get a wake event */ 42 nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_WAKE_TIME, (uint64_t)wake_time); 43 } 44 45 /* 46 * This request allows updating of CLUSTER_CSTATE, CCPLEX_CSTATE and 47 * SYSTEM_CSTATE values. 48 * 49 * NVGDATA[0:2]: SW(RW), CLUSTER_CSTATE 50 * NVGDATA[7]: SW(W), update cluster flag 51 * NVGDATA[8:10]: SW(RW), CG_CSTATE 52 * NVGDATA[15]: SW(W), update ccplex flag 53 * NVGDATA[16:19]: SW(RW), SYSTEM_CSTATE 54 * NVGDATA[23]: SW(W), update system flag 55 * NVGDATA[31]: SW(W), update wake mask flag 56 * NVGDATA[32:63]: SW(RW), WAKE_MASK 57 */ 58 void nvg_update_cstate_info(uint32_t cluster, uint32_t ccplex, 59 uint32_t system, uint32_t wake_mask, uint8_t update_wake_mask) 60 { 61 uint64_t val = 0; 62 63 /* update CLUSTER_CSTATE? */ 64 if (cluster != 0U) { 65 val |= ((uint64_t)cluster & CLUSTER_CSTATE_MASK) | 66 CLUSTER_CSTATE_UPDATE_BIT; 67 } 68 69 /* update CCPLEX_CSTATE? */ 70 if (ccplex != 0U) { 71 val |= (((uint64_t)ccplex & CCPLEX_CSTATE_MASK) << CCPLEX_CSTATE_SHIFT) | 72 CCPLEX_CSTATE_UPDATE_BIT; 73 } 74 75 /* update SYSTEM_CSTATE? */ 76 if (system != 0U) { 77 val |= (((uint64_t)system & SYSTEM_CSTATE_MASK) << SYSTEM_CSTATE_SHIFT) | 78 SYSTEM_CSTATE_UPDATE_BIT; 79 } 80 81 /* update wake mask value? */ 82 if (update_wake_mask != 0U) { 83 val |= CSTATE_WAKE_MASK_UPDATE_BIT; 84 } 85 86 /* set the wake mask */ 87 val |= ((uint64_t)wake_mask & CSTATE_WAKE_MASK_CLEAR) << CSTATE_WAKE_MASK_SHIFT; 88 89 /* set the updated cstate info */ 90 nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_CSTATE_INFO, val); 91 } 92 93 /* 94 * Return a non-zero value if the CCPLEX is able to enter SC7 95 * 96 * NVGDATA[0]: SW(R), Is allowed result 97 */ 98 int32_t nvg_is_sc7_allowed(void) 99 { 100 /* issue command to check if SC7 is allowed */ 101 nvg_set_request((uint64_t)TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED); 102 103 /* 1 = SC7 allowed, 0 = SC7 not allowed */ 104 return (int32_t)nvg_get_result(); 105 } 106 107 /* 108 * Wake an offlined logical core. Note that a core is offlined by entering 109 * a C-state where the WAKE_MASK is all 0. 110 * 111 * NVGDATA[0:3]: SW(W) logical core to online 112 */ 113 int32_t nvg_online_core(uint32_t core) 114 { 115 int32_t ret = 0; 116 117 /* sanity check the core ID value */ 118 if (core > (uint32_t)PLATFORM_CORE_COUNT) { 119 ERROR("%s: unknown core id (%d)\n", __func__, core); 120 ret = -EINVAL; 121 } else { 122 /* get a core online */ 123 nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_ONLINE_CORE, 124 (uint64_t)core & MCE_CORE_ID_MASK); 125 } 126 127 return ret; 128 } 129 130 /* 131 * MC GSC (General Security Carveout) register values are expected to be 132 * changed by TrustZone ARM code after boot. 133 * 134 * NVGDATA[0:15] SW(R) GSC enun 135 */ 136 int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx) 137 { 138 int32_t ret = 0; 139 140 /* sanity check GSC ID */ 141 if (gsc_idx > (uint32_t)TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR) { 142 ERROR("%s: unknown gsc_idx (%u)\n", __func__, gsc_idx); 143 ret = -EINVAL; 144 } else { 145 nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC, 146 (uint64_t)gsc_idx); 147 } 148 149 return ret; 150 } 151 152 /* 153 * Cache clean and invalidate, clear TR-bit operation for all CCPLEX caches. 154 */ 155 int32_t nvg_roc_clean_cache_trbits(void) 156 { 157 int32_t ret = 0; 158 159 /* check if cache flush through mts is supported */ 160 if (((read_id_afr0_el1() >> ID_AFR0_EL1_CACHE_OPS_SHIFT) & 161 ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) { 162 if (nvg_cache_inval_all() == 0U) { 163 ERROR("%s: failed\n", __func__); 164 ret = -ENODEV; 165 } 166 } else { 167 ret = -ENOTSUP; 168 } 169 170 return ret; 171 } 172 173 /* 174 * Set the power state for a core 175 */ 176 int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time) 177 { 178 int32_t ret = 0; 179 uint64_t val = 0ULL; 180 181 /* check for allowed power state */ 182 if ((state != (uint32_t)TEGRA_NVG_CORE_C0) && 183 (state != (uint32_t)TEGRA_NVG_CORE_C1) && 184 (state != (uint32_t)TEGRA_NVG_CORE_C6) && 185 (state != (uint32_t)TEGRA_NVG_CORE_C7)) 186 { 187 ERROR("%s: unknown cstate (%u)\n", __func__, state); 188 ret = -EINVAL; 189 } else { 190 /* time (TSC ticks) until the core is expected to get a wake event */ 191 nvg_set_wake_time(wake_time); 192 193 /* set the core cstate */ 194 val = read_actlr_el1() & ~ACTLR_EL1_PMSTATE_MASK; 195 write_actlr_el1(val | (uint64_t)state); 196 } 197 198 return ret; 199 } 200 201 #if ENABLE_STRICT_CHECKING_MODE 202 /* 203 * Enable strict checking mode 204 * 205 * NVGDATA[3] strict_check ON + lock 206 */ 207 void nvg_enable_strict_checking_mode(void) 208 { 209 uint64_t params = (uint64_t)(STRICT_CHECKING_ENABLED_SET | 210 STRICT_CHECKING_LOCKED_SET); 211 212 nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_SECURITY_CONFIG, params); 213 } 214 #endif 215 216 /* 217 * Request a reboot 218 * 219 * NVGDATA[0]: reboot command 220 */ 221 void nvg_system_reboot(void) 222 { 223 /* issue command for reboot */ 224 nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_SHUTDOWN, 225 (uint64_t)TEGRA_NVG_REBOOT); 226 } 227 228 /* 229 * Request a shutdown 230 * 231 * NVGDATA[0]: shutdown command 232 */ 233 void nvg_system_shutdown(void) 234 { 235 /* issue command for shutdown */ 236 nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_SHUTDOWN, 237 (uint64_t)TEGRA_NVG_SHUTDOWN); 238 } 239