1# 2# Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are met: 6# 7# Redistributions of source code must retain the above copyright notice, this 8# list of conditions and the following disclaimer. 9# 10# Redistributions in binary form must reproduce the above copyright notice, 11# this list of conditions and the following disclaimer in the documentation 12# and/or other materials provided with the distribution. 13# 14# Neither the name of ARM nor the names of its contributors may be used 15# to endorse or promote products derived from this software without specific 16# prior written permission. 17# 18# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28# POSSIBILITY OF SUCH DAMAGE. 29# 30 31# platform configs 32ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS := 1 33$(eval $(call add_define,ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS)) 34 35RELOCATE_TO_BL31_BASE := 1 36$(eval $(call add_define,RELOCATE_TO_BL31_BASE)) 37 38ENABLE_CHIP_VERIFICATION_HARNESS := 0 39$(eval $(call add_define,ENABLE_CHIP_VERIFICATION_HARNESS)) 40 41RESET_TO_BL31 := 1 42 43PROGRAMMABLE_RESET_ADDRESS := 1 44 45COLD_BOOT_SINGLE_CPU := 1 46 47# platform settings 48TZDRAM_BASE := 0x30000000 49$(eval $(call add_define,TZDRAM_BASE)) 50 51PLATFORM_CLUSTER_COUNT := 2 52$(eval $(call add_define,PLATFORM_CLUSTER_COUNT)) 53 54PLATFORM_MAX_CPUS_PER_CLUSTER := 4 55$(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER)) 56 57MAX_XLAT_TABLES := 20 58$(eval $(call add_define,MAX_XLAT_TABLES)) 59 60MAX_MMAP_REGIONS := 20 61$(eval $(call add_define,MAX_MMAP_REGIONS)) 62 63# platform files 64PLAT_INCLUDES += -I${SOC_DIR}/drivers/include 65 66BL31_SOURCES += lib/cpus/aarch64/denver.S \ 67 lib/cpus/aarch64/cortex_a57.S \ 68 ${COMMON_DIR}/drivers/memctrl/memctrl_v2.c \ 69 ${SOC_DIR}/drivers/mce/mce.c \ 70 ${SOC_DIR}/drivers/mce/ari.c \ 71 ${SOC_DIR}/drivers/mce/nvg.c \ 72 ${SOC_DIR}/drivers/mce/aarch64/nvg_helpers.S \ 73 ${SOC_DIR}/drivers/smmu/smmu.c \ 74 ${SOC_DIR}/plat_psci_handlers.c \ 75 ${SOC_DIR}/plat_setup.c \ 76 ${SOC_DIR}/plat_secondary.c \ 77 ${SOC_DIR}/plat_sip_calls.c \ 78 ${SOC_DIR}/plat_trampoline.S 79