1# 2# Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are met: 6# 7# Redistributions of source code must retain the above copyright notice, this 8# list of conditions and the following disclaimer. 9# 10# Redistributions in binary form must reproduce the above copyright notice, 11# this list of conditions and the following disclaimer in the documentation 12# and/or other materials provided with the distribution. 13# 14# Neither the name of ARM nor the names of its contributors may be used 15# to endorse or promote products derived from this software without specific 16# prior written permission. 17# 18# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28# POSSIBILITY OF SUCH DAMAGE. 29# 30 31# platform configs 32ENABLE_AFI_DEVICE := 1 33$(eval $(call add_define,ENABLE_AFI_DEVICE)) 34 35ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS := 1 36$(eval $(call add_define,ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS)) 37 38RELOCATE_TO_BL31_BASE := 1 39$(eval $(call add_define,RELOCATE_TO_BL31_BASE)) 40 41ENABLE_CHIP_VERIFICATION_HARNESS := 0 42$(eval $(call add_define,ENABLE_CHIP_VERIFICATION_HARNESS)) 43 44ENABLE_SMMU_DEVICE := 1 45$(eval $(call add_define,ENABLE_SMMU_DEVICE)) 46 47NUM_SMMU_DEVICES := 1 48$(eval $(call add_define,NUM_SMMU_DEVICES)) 49 50RESET_TO_BL31 := 1 51 52PROGRAMMABLE_RESET_ADDRESS := 1 53 54COLD_BOOT_SINGLE_CPU := 1 55 56# platform settings 57TZDRAM_BASE := 0x30000000 58$(eval $(call add_define,TZDRAM_BASE)) 59 60PLATFORM_CLUSTER_COUNT := 2 61$(eval $(call add_define,PLATFORM_CLUSTER_COUNT)) 62 63PLATFORM_MAX_CPUS_PER_CLUSTER := 4 64$(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER)) 65 66MAX_XLAT_TABLES := 24 67$(eval $(call add_define,MAX_XLAT_TABLES)) 68 69MAX_MMAP_REGIONS := 24 70$(eval $(call add_define,MAX_MMAP_REGIONS)) 71 72# platform files 73PLAT_INCLUDES += -I${SOC_DIR}/drivers/include 74 75BL31_SOURCES += lib/cpus/aarch64/denver.S \ 76 lib/cpus/aarch64/cortex_a57.S \ 77 ${COMMON_DIR}/drivers/memctrl/memctrl_v2.c \ 78 ${COMMON_DIR}/drivers/smmu/smmu.c \ 79 ${SOC_DIR}/drivers/mce/mce.c \ 80 ${SOC_DIR}/drivers/mce/ari.c \ 81 ${SOC_DIR}/drivers/mce/nvg.c \ 82 ${SOC_DIR}/drivers/mce/aarch64/nvg_helpers.S \ 83 ${SOC_DIR}/plat_memctrl.c \ 84 ${SOC_DIR}/plat_psci_handlers.c \ 85 ${SOC_DIR}/plat_setup.c \ 86 ${SOC_DIR}/plat_secondary.c \ 87 ${SOC_DIR}/plat_sip_calls.c \ 88 ${SOC_DIR}/plat_smmu.c \ 89 ${SOC_DIR}/plat_trampoline.S 90 91