1/* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <arch.h> 32#include <asm_macros.S> 33#include <memctrl_v2.h> 34#include <tegra_def.h> 35 36#define TEGRA186_SMMU_CTX_SIZE 0x420 37 38 .align 4 39 .globl tegra186_cpu_reset_handler 40 41/* CPU reset handler routine */ 42func tegra186_cpu_reset_handler 43 /* 44 * The Memory Controller loses state during System Suspend. We 45 * use this information to decide if the reset handler is running 46 * after a System Suspend. Resume from system suspend requires 47 * restoring the entire state from TZDRAM to TZRAM. 48 */ 49 mov x1, #TEGRA_MC_BASE 50 ldr w0, [x1, #MC_SECURITY_CFG3_0] 51 lsl x0, x0, #32 52 ldr w0, [x1, #MC_SECURITY_CFG0_0] 53 adr x1, tegra186_cpu_reset_handler 54 cmp x0, x1 55 beq boot_cpu 56 57 /* resume from system suspend */ 58 mov x0, #BL31_BASE 59 adr x1, __tegra186_cpu_reset_handler_end 60 adr x2, __tegra186_cpu_reset_handler_data 61 ldr x2, [x2, #8] 62 63 /* memcpy16 */ 64m_loop16: 65 cmp x2, #16 66 b.lt m_loop1 67 ldp x3, x4, [x1], #16 68 stp x3, x4, [x0], #16 69 sub x2, x2, #16 70 b m_loop16 71 /* copy byte per byte */ 72m_loop1: 73 cbz x2, boot_cpu 74 ldrb w3, [x1], #1 75 strb w3, [x0], #1 76 subs x2, x2, #1 77 b.ne m_loop1 78 79boot_cpu: 80 adr x0, __tegra186_cpu_reset_handler_data 81 ldr x0, [x0] 82 br x0 83endfunc tegra186_cpu_reset_handler 84 85 /* 86 * Tegra186 reset data (offset 0x0 - 0x430) 87 * 88 * 0x000: secure world's entrypoint 89 * 0x008: BL31 size (RO + RW) 90 * 0x00C: SMMU context start 91 * 0x42C: SMMU context end 92 */ 93 94 .align 4 95 .type __tegra186_cpu_reset_handler_data, %object 96 .globl __tegra186_cpu_reset_handler_data 97__tegra186_cpu_reset_handler_data: 98 .quad tegra_secure_entrypoint 99 .quad __BL31_END__ - BL31_BASE 100 .rept TEGRA186_SMMU_CTX_SIZE 101 .quad 0 102 .endr 103 .size __tegra186_cpu_reset_handler_data, \ 104 . - __tegra186_cpu_reset_handler_data 105 106 .align 4 107 .globl __tegra186_cpu_reset_handler_end 108__tegra186_cpu_reset_handler_end: 109