168c7de6fSVarun Wadekar/* 25e2fe3a3SVarun Wadekar * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. 3*a391d494SPritesh Raithatha * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 468c7de6fSVarun Wadekar * 582cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 668c7de6fSVarun Wadekar */ 768c7de6fSVarun Wadekar 868c7de6fSVarun Wadekar#include <arch.h> 968c7de6fSVarun Wadekar#include <asm_macros.S> 105e2fe3a3SVarun Wadekar#include <common/bl_common.h> 1168c7de6fSVarun Wadekar#include <memctrl_v2.h> 1209d40e0eSAntonio Nino Diaz#include <plat/common/common_def.h> 1368c7de6fSVarun Wadekar#include <tegra_def.h> 1468c7de6fSVarun Wadekar 15539c62d7SVarun Wadekar#define TEGRA186_STATE_SYSTEM_SUSPEND 0x5C7 16539c62d7SVarun Wadekar#define TEGRA186_STATE_SYSTEM_RESUME 0x600D 17*a391d494SPritesh Raithatha#define TEGRA186_MC_CTX_SIZE 0x93 1868c7de6fSVarun Wadekar 1968c7de6fSVarun Wadekar .globl tegra186_cpu_reset_handler 2068c7de6fSVarun Wadekar 2168c7de6fSVarun Wadekar/* CPU reset handler routine */ 2264726e6dSJulius Wernerfunc tegra186_cpu_reset_handler _align=4 23539c62d7SVarun Wadekar /* check if we are exiting system suspend state */ 24539c62d7SVarun Wadekar adr x0, __tegra186_system_suspend_state 25539c62d7SVarun Wadekar ldr x1, [x0] 26539c62d7SVarun Wadekar mov x2, #TEGRA186_STATE_SYSTEM_SUSPEND 27539c62d7SVarun Wadekar lsl x2, x2, #16 28539c62d7SVarun Wadekar add x2, x2, #TEGRA186_STATE_SYSTEM_SUSPEND 29539c62d7SVarun Wadekar cmp x1, x2 30539c62d7SVarun Wadekar bne boot_cpu 3168c7de6fSVarun Wadekar 32539c62d7SVarun Wadekar /* set system resume state */ 33539c62d7SVarun Wadekar mov x1, #TEGRA186_STATE_SYSTEM_RESUME 34539c62d7SVarun Wadekar lsl x1, x1, #16 35539c62d7SVarun Wadekar mov x2, #TEGRA186_STATE_SYSTEM_RESUME 36539c62d7SVarun Wadekar add x1, x1, x2 37539c62d7SVarun Wadekar str x1, [x0] 38539c62d7SVarun Wadekar dsb sy 39539c62d7SVarun Wadekar 40539c62d7SVarun Wadekar /* prepare to relocate to TZSRAM */ 4168c7de6fSVarun Wadekar mov x0, #BL31_BASE 4268c7de6fSVarun Wadekar adr x1, __tegra186_cpu_reset_handler_end 4368c7de6fSVarun Wadekar adr x2, __tegra186_cpu_reset_handler_data 4468c7de6fSVarun Wadekar ldr x2, [x2, #8] 4568c7de6fSVarun Wadekar 4668c7de6fSVarun Wadekar /* memcpy16 */ 4768c7de6fSVarun Wadekarm_loop16: 4868c7de6fSVarun Wadekar cmp x2, #16 4968c7de6fSVarun Wadekar b.lt m_loop1 5068c7de6fSVarun Wadekar ldp x3, x4, [x1], #16 5168c7de6fSVarun Wadekar stp x3, x4, [x0], #16 5268c7de6fSVarun Wadekar sub x2, x2, #16 5368c7de6fSVarun Wadekar b m_loop16 5468c7de6fSVarun Wadekar /* copy byte per byte */ 5568c7de6fSVarun Wadekarm_loop1: 5668c7de6fSVarun Wadekar cbz x2, boot_cpu 5768c7de6fSVarun Wadekar ldrb w3, [x1], #1 5868c7de6fSVarun Wadekar strb w3, [x0], #1 5968c7de6fSVarun Wadekar subs x2, x2, #1 6068c7de6fSVarun Wadekar b.ne m_loop1 6168c7de6fSVarun Wadekar 6268c7de6fSVarun Wadekarboot_cpu: 6368c7de6fSVarun Wadekar adr x0, __tegra186_cpu_reset_handler_data 6468c7de6fSVarun Wadekar ldr x0, [x0] 6568c7de6fSVarun Wadekar br x0 6668c7de6fSVarun Wadekarendfunc tegra186_cpu_reset_handler 6768c7de6fSVarun Wadekar 6868c7de6fSVarun Wadekar /* 6968c7de6fSVarun Wadekar * Tegra186 reset data (offset 0x0 - 0x430) 7068c7de6fSVarun Wadekar * 7168c7de6fSVarun Wadekar * 0x000: secure world's entrypoint 7268c7de6fSVarun Wadekar * 0x008: BL31 size (RO + RW) 73*a391d494SPritesh Raithatha * 0x00C: MC context start 74*a391d494SPritesh Raithatha * 0x42C: MC context end 7568c7de6fSVarun Wadekar */ 7668c7de6fSVarun Wadekar 7768c7de6fSVarun Wadekar .align 4 7868c7de6fSVarun Wadekar .type __tegra186_cpu_reset_handler_data, %object 7968c7de6fSVarun Wadekar .globl __tegra186_cpu_reset_handler_data 8068c7de6fSVarun Wadekar__tegra186_cpu_reset_handler_data: 8168c7de6fSVarun Wadekar .quad tegra_secure_entrypoint 8268c7de6fSVarun Wadekar .quad __BL31_END__ - BL31_BASE 83889c07c7SVarun Wadekar 84539c62d7SVarun Wadekar .globl __tegra186_system_suspend_state 85539c62d7SVarun Wadekar__tegra186_system_suspend_state: 86539c62d7SVarun Wadekar .quad 0 87539c62d7SVarun Wadekar 88889c07c7SVarun Wadekar .align 4 89*a391d494SPritesh Raithatha .globl __tegra186_mc_context 90*a391d494SPritesh Raithatha__tegra186_mc_context: 91*a391d494SPritesh Raithatha .rept TEGRA186_MC_CTX_SIZE 9268c7de6fSVarun Wadekar .quad 0 9368c7de6fSVarun Wadekar .endr 9468c7de6fSVarun Wadekar .size __tegra186_cpu_reset_handler_data, \ 9568c7de6fSVarun Wadekar . - __tegra186_cpu_reset_handler_data 9668c7de6fSVarun Wadekar 9768c7de6fSVarun Wadekar .align 4 9868c7de6fSVarun Wadekar .globl __tegra186_cpu_reset_handler_end 9968c7de6fSVarun Wadekar__tegra186_cpu_reset_handler_end: 1007191566cSVarun Wadekar 1017191566cSVarun Wadekar .globl tegra186_get_cpu_reset_handler_size 1027191566cSVarun Wadekar .globl tegra186_get_cpu_reset_handler_base 103*a391d494SPritesh Raithatha .globl tegra186_get_mc_ctx_offset 104539c62d7SVarun Wadekar .globl tegra186_set_system_suspend_entry 1057191566cSVarun Wadekar 1067191566cSVarun Wadekar/* return size of the CPU reset handler */ 1077191566cSVarun Wadekarfunc tegra186_get_cpu_reset_handler_size 1087191566cSVarun Wadekar adr x0, __tegra186_cpu_reset_handler_end 1097191566cSVarun Wadekar adr x1, tegra186_cpu_reset_handler 1107191566cSVarun Wadekar sub x0, x0, x1 1117191566cSVarun Wadekar ret 1127191566cSVarun Wadekarendfunc tegra186_get_cpu_reset_handler_size 1137191566cSVarun Wadekar 1147191566cSVarun Wadekar/* return the start address of the CPU reset handler */ 1157191566cSVarun Wadekarfunc tegra186_get_cpu_reset_handler_base 1167191566cSVarun Wadekar adr x0, tegra186_cpu_reset_handler 1177191566cSVarun Wadekar ret 1187191566cSVarun Wadekarendfunc tegra186_get_cpu_reset_handler_base 119889c07c7SVarun Wadekar 120*a391d494SPritesh Raithatha/* return the size of the MC context */ 121*a391d494SPritesh Raithathafunc tegra186_get_mc_ctx_offset 122*a391d494SPritesh Raithatha adr x0, __tegra186_mc_context 123889c07c7SVarun Wadekar adr x1, tegra186_cpu_reset_handler 124889c07c7SVarun Wadekar sub x0, x0, x1 125889c07c7SVarun Wadekar ret 126*a391d494SPritesh Raithathaendfunc tegra186_get_mc_ctx_offset 127539c62d7SVarun Wadekar 128539c62d7SVarun Wadekar/* set system suspend state before SC7 entry */ 129539c62d7SVarun Wadekarfunc tegra186_set_system_suspend_entry 130539c62d7SVarun Wadekar mov x0, #TEGRA_MC_BASE 131539c62d7SVarun Wadekar mov x3, #MC_SECURITY_CFG3_0 132539c62d7SVarun Wadekar ldr w1, [x0, x3] 133539c62d7SVarun Wadekar lsl x1, x1, #32 134539c62d7SVarun Wadekar mov x3, #MC_SECURITY_CFG0_0 135539c62d7SVarun Wadekar ldr w2, [x0, x3] 136539c62d7SVarun Wadekar orr x3, x1, x2 /* TZDRAM base */ 137539c62d7SVarun Wadekar adr x0, __tegra186_system_suspend_state 138539c62d7SVarun Wadekar adr x1, tegra186_cpu_reset_handler 139539c62d7SVarun Wadekar sub x2, x0, x1 /* offset in TZDRAM */ 140539c62d7SVarun Wadekar mov x0, #TEGRA186_STATE_SYSTEM_SUSPEND 141539c62d7SVarun Wadekar lsl x0, x0, #16 142539c62d7SVarun Wadekar add x0, x0, #TEGRA186_STATE_SYSTEM_SUSPEND 143539c62d7SVarun Wadekar str x0, [x3, x2] /* set value in TZDRAM */ 144539c62d7SVarun Wadekar dsb sy 145539c62d7SVarun Wadekar ret 146539c62d7SVarun Wadekarendfunc tegra186_set_system_suspend_entry 147