1*68c7de6fSVarun Wadekar/* 2*68c7de6fSVarun Wadekar * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3*68c7de6fSVarun Wadekar * 4*68c7de6fSVarun Wadekar * Redistribution and use in source and binary forms, with or without 5*68c7de6fSVarun Wadekar * modification, are permitted provided that the following conditions are met: 6*68c7de6fSVarun Wadekar * 7*68c7de6fSVarun Wadekar * Redistributions of source code must retain the above copyright notice, this 8*68c7de6fSVarun Wadekar * list of conditions and the following disclaimer. 9*68c7de6fSVarun Wadekar * 10*68c7de6fSVarun Wadekar * Redistributions in binary form must reproduce the above copyright notice, 11*68c7de6fSVarun Wadekar * this list of conditions and the following disclaimer in the documentation 12*68c7de6fSVarun Wadekar * and/or other materials provided with the distribution. 13*68c7de6fSVarun Wadekar * 14*68c7de6fSVarun Wadekar * Neither the name of ARM nor the names of its contributors may be used 15*68c7de6fSVarun Wadekar * to endorse or promote products derived from this software without specific 16*68c7de6fSVarun Wadekar * prior written permission. 17*68c7de6fSVarun Wadekar * 18*68c7de6fSVarun Wadekar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19*68c7de6fSVarun Wadekar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20*68c7de6fSVarun Wadekar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21*68c7de6fSVarun Wadekar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22*68c7de6fSVarun Wadekar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23*68c7de6fSVarun Wadekar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24*68c7de6fSVarun Wadekar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25*68c7de6fSVarun Wadekar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26*68c7de6fSVarun Wadekar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27*68c7de6fSVarun Wadekar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28*68c7de6fSVarun Wadekar * POSSIBILITY OF SUCH DAMAGE. 29*68c7de6fSVarun Wadekar */ 30*68c7de6fSVarun Wadekar 31*68c7de6fSVarun Wadekar#include <arch.h> 32*68c7de6fSVarun Wadekar#include <asm_macros.S> 33*68c7de6fSVarun Wadekar#include <memctrl_v2.h> 34*68c7de6fSVarun Wadekar#include <tegra_def.h> 35*68c7de6fSVarun Wadekar 36*68c7de6fSVarun Wadekar#define TEGRA186_SMMU_CTX_SIZE 0x420 37*68c7de6fSVarun Wadekar 38*68c7de6fSVarun Wadekar .align 4 39*68c7de6fSVarun Wadekar .globl tegra186_cpu_reset_handler 40*68c7de6fSVarun Wadekar 41*68c7de6fSVarun Wadekar/* CPU reset handler routine */ 42*68c7de6fSVarun Wadekarfunc tegra186_cpu_reset_handler 43*68c7de6fSVarun Wadekar /* 44*68c7de6fSVarun Wadekar * The Memory Controller loses state during System Suspend. We 45*68c7de6fSVarun Wadekar * use this information to decide if the reset handler is running 46*68c7de6fSVarun Wadekar * after a System Suspend. Resume from system suspend requires 47*68c7de6fSVarun Wadekar * restoring the entire state from TZDRAM to TZRAM. 48*68c7de6fSVarun Wadekar */ 49*68c7de6fSVarun Wadekar mov x1, #TEGRA_MC_BASE 50*68c7de6fSVarun Wadekar ldr w0, [x1, #MC_SECURITY_CFG3_0] 51*68c7de6fSVarun Wadekar lsl x0, x0, #32 52*68c7de6fSVarun Wadekar ldr w0, [x1, #MC_SECURITY_CFG0_0] 53*68c7de6fSVarun Wadekar adr x1, tegra186_cpu_reset_handler 54*68c7de6fSVarun Wadekar cmp x0, x1 55*68c7de6fSVarun Wadekar beq boot_cpu 56*68c7de6fSVarun Wadekar 57*68c7de6fSVarun Wadekar /* resume from system suspend */ 58*68c7de6fSVarun Wadekar mov x0, #BL31_BASE 59*68c7de6fSVarun Wadekar adr x1, __tegra186_cpu_reset_handler_end 60*68c7de6fSVarun Wadekar adr x2, __tegra186_cpu_reset_handler_data 61*68c7de6fSVarun Wadekar ldr x2, [x2, #8] 62*68c7de6fSVarun Wadekar 63*68c7de6fSVarun Wadekar /* memcpy16 */ 64*68c7de6fSVarun Wadekarm_loop16: 65*68c7de6fSVarun Wadekar cmp x2, #16 66*68c7de6fSVarun Wadekar b.lt m_loop1 67*68c7de6fSVarun Wadekar ldp x3, x4, [x1], #16 68*68c7de6fSVarun Wadekar stp x3, x4, [x0], #16 69*68c7de6fSVarun Wadekar sub x2, x2, #16 70*68c7de6fSVarun Wadekar b m_loop16 71*68c7de6fSVarun Wadekar /* copy byte per byte */ 72*68c7de6fSVarun Wadekarm_loop1: 73*68c7de6fSVarun Wadekar cbz x2, boot_cpu 74*68c7de6fSVarun Wadekar ldrb w3, [x1], #1 75*68c7de6fSVarun Wadekar strb w3, [x0], #1 76*68c7de6fSVarun Wadekar subs x2, x2, #1 77*68c7de6fSVarun Wadekar b.ne m_loop1 78*68c7de6fSVarun Wadekar 79*68c7de6fSVarun Wadekarboot_cpu: 80*68c7de6fSVarun Wadekar adr x0, __tegra186_cpu_reset_handler_data 81*68c7de6fSVarun Wadekar ldr x0, [x0] 82*68c7de6fSVarun Wadekar br x0 83*68c7de6fSVarun Wadekarendfunc tegra186_cpu_reset_handler 84*68c7de6fSVarun Wadekar 85*68c7de6fSVarun Wadekar /* 86*68c7de6fSVarun Wadekar * Tegra186 reset data (offset 0x0 - 0x430) 87*68c7de6fSVarun Wadekar * 88*68c7de6fSVarun Wadekar * 0x000: secure world's entrypoint 89*68c7de6fSVarun Wadekar * 0x008: BL31 size (RO + RW) 90*68c7de6fSVarun Wadekar * 0x00C: SMMU context start 91*68c7de6fSVarun Wadekar * 0x42C: SMMU context end 92*68c7de6fSVarun Wadekar */ 93*68c7de6fSVarun Wadekar 94*68c7de6fSVarun Wadekar .align 4 95*68c7de6fSVarun Wadekar .type __tegra186_cpu_reset_handler_data, %object 96*68c7de6fSVarun Wadekar .globl __tegra186_cpu_reset_handler_data 97*68c7de6fSVarun Wadekar__tegra186_cpu_reset_handler_data: 98*68c7de6fSVarun Wadekar .quad tegra_secure_entrypoint 99*68c7de6fSVarun Wadekar .quad __BL31_END__ - BL31_BASE 100*68c7de6fSVarun Wadekar .rept TEGRA186_SMMU_CTX_SIZE 101*68c7de6fSVarun Wadekar .quad 0 102*68c7de6fSVarun Wadekar .endr 103*68c7de6fSVarun Wadekar .size __tegra186_cpu_reset_handler_data, \ 104*68c7de6fSVarun Wadekar . - __tegra186_cpu_reset_handler_data 105*68c7de6fSVarun Wadekar 106*68c7de6fSVarun Wadekar .align 4 107*68c7de6fSVarun Wadekar .globl __tegra186_cpu_reset_handler_end 108*68c7de6fSVarun Wadekar__tegra186_cpu_reset_handler_end: 109