168c7de6fSVarun Wadekar/* 268c7de6fSVarun Wadekar * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 368c7de6fSVarun Wadekar * 468c7de6fSVarun Wadekar * Redistribution and use in source and binary forms, with or without 568c7de6fSVarun Wadekar * modification, are permitted provided that the following conditions are met: 668c7de6fSVarun Wadekar * 768c7de6fSVarun Wadekar * Redistributions of source code must retain the above copyright notice, this 868c7de6fSVarun Wadekar * list of conditions and the following disclaimer. 968c7de6fSVarun Wadekar * 1068c7de6fSVarun Wadekar * Redistributions in binary form must reproduce the above copyright notice, 1168c7de6fSVarun Wadekar * this list of conditions and the following disclaimer in the documentation 1268c7de6fSVarun Wadekar * and/or other materials provided with the distribution. 1368c7de6fSVarun Wadekar * 1468c7de6fSVarun Wadekar * Neither the name of ARM nor the names of its contributors may be used 1568c7de6fSVarun Wadekar * to endorse or promote products derived from this software without specific 1668c7de6fSVarun Wadekar * prior written permission. 1768c7de6fSVarun Wadekar * 1868c7de6fSVarun Wadekar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 1968c7de6fSVarun Wadekar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2068c7de6fSVarun Wadekar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2168c7de6fSVarun Wadekar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 2268c7de6fSVarun Wadekar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2368c7de6fSVarun Wadekar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2468c7de6fSVarun Wadekar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2568c7de6fSVarun Wadekar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2668c7de6fSVarun Wadekar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2768c7de6fSVarun Wadekar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 2868c7de6fSVarun Wadekar * POSSIBILITY OF SUCH DAMAGE. 2968c7de6fSVarun Wadekar */ 3068c7de6fSVarun Wadekar 3168c7de6fSVarun Wadekar#include <arch.h> 3268c7de6fSVarun Wadekar#include <asm_macros.S> 33*2079ddd6SVarun Wadekar#include <common_def.h> 3468c7de6fSVarun Wadekar#include <memctrl_v2.h> 3568c7de6fSVarun Wadekar#include <tegra_def.h> 3668c7de6fSVarun Wadekar 3768c7de6fSVarun Wadekar#define TEGRA186_SMMU_CTX_SIZE 0x420 3868c7de6fSVarun Wadekar 3968c7de6fSVarun Wadekar .align 4 4068c7de6fSVarun Wadekar .globl tegra186_cpu_reset_handler 4168c7de6fSVarun Wadekar 4268c7de6fSVarun Wadekar/* CPU reset handler routine */ 4368c7de6fSVarun Wadekarfunc tegra186_cpu_reset_handler 4468c7de6fSVarun Wadekar /* 4568c7de6fSVarun Wadekar * The Memory Controller loses state during System Suspend. We 4668c7de6fSVarun Wadekar * use this information to decide if the reset handler is running 4768c7de6fSVarun Wadekar * after a System Suspend. Resume from system suspend requires 4868c7de6fSVarun Wadekar * restoring the entire state from TZDRAM to TZRAM. 4968c7de6fSVarun Wadekar */ 5068c7de6fSVarun Wadekar mov x1, #TEGRA_MC_BASE 5168c7de6fSVarun Wadekar ldr w0, [x1, #MC_SECURITY_CFG3_0] 5268c7de6fSVarun Wadekar lsl x0, x0, #32 5368c7de6fSVarun Wadekar ldr w0, [x1, #MC_SECURITY_CFG0_0] 5468c7de6fSVarun Wadekar adr x1, tegra186_cpu_reset_handler 5568c7de6fSVarun Wadekar cmp x0, x1 5668c7de6fSVarun Wadekar beq boot_cpu 5768c7de6fSVarun Wadekar 5868c7de6fSVarun Wadekar /* resume from system suspend */ 5968c7de6fSVarun Wadekar mov x0, #BL31_BASE 6068c7de6fSVarun Wadekar adr x1, __tegra186_cpu_reset_handler_end 6168c7de6fSVarun Wadekar adr x2, __tegra186_cpu_reset_handler_data 6268c7de6fSVarun Wadekar ldr x2, [x2, #8] 6368c7de6fSVarun Wadekar 6468c7de6fSVarun Wadekar /* memcpy16 */ 6568c7de6fSVarun Wadekarm_loop16: 6668c7de6fSVarun Wadekar cmp x2, #16 6768c7de6fSVarun Wadekar b.lt m_loop1 6868c7de6fSVarun Wadekar ldp x3, x4, [x1], #16 6968c7de6fSVarun Wadekar stp x3, x4, [x0], #16 7068c7de6fSVarun Wadekar sub x2, x2, #16 7168c7de6fSVarun Wadekar b m_loop16 7268c7de6fSVarun Wadekar /* copy byte per byte */ 7368c7de6fSVarun Wadekarm_loop1: 7468c7de6fSVarun Wadekar cbz x2, boot_cpu 7568c7de6fSVarun Wadekar ldrb w3, [x1], #1 7668c7de6fSVarun Wadekar strb w3, [x0], #1 7768c7de6fSVarun Wadekar subs x2, x2, #1 7868c7de6fSVarun Wadekar b.ne m_loop1 7968c7de6fSVarun Wadekar 8068c7de6fSVarun Wadekarboot_cpu: 8168c7de6fSVarun Wadekar adr x0, __tegra186_cpu_reset_handler_data 8268c7de6fSVarun Wadekar ldr x0, [x0] 8368c7de6fSVarun Wadekar br x0 8468c7de6fSVarun Wadekarendfunc tegra186_cpu_reset_handler 8568c7de6fSVarun Wadekar 8668c7de6fSVarun Wadekar /* 8768c7de6fSVarun Wadekar * Tegra186 reset data (offset 0x0 - 0x430) 8868c7de6fSVarun Wadekar * 8968c7de6fSVarun Wadekar * 0x000: secure world's entrypoint 9068c7de6fSVarun Wadekar * 0x008: BL31 size (RO + RW) 9168c7de6fSVarun Wadekar * 0x00C: SMMU context start 9268c7de6fSVarun Wadekar * 0x42C: SMMU context end 9368c7de6fSVarun Wadekar */ 9468c7de6fSVarun Wadekar 9568c7de6fSVarun Wadekar .align 4 9668c7de6fSVarun Wadekar .type __tegra186_cpu_reset_handler_data, %object 9768c7de6fSVarun Wadekar .globl __tegra186_cpu_reset_handler_data 9868c7de6fSVarun Wadekar__tegra186_cpu_reset_handler_data: 9968c7de6fSVarun Wadekar .quad tegra_secure_entrypoint 10068c7de6fSVarun Wadekar .quad __BL31_END__ - BL31_BASE 10168c7de6fSVarun Wadekar .rept TEGRA186_SMMU_CTX_SIZE 10268c7de6fSVarun Wadekar .quad 0 10368c7de6fSVarun Wadekar .endr 10468c7de6fSVarun Wadekar .size __tegra186_cpu_reset_handler_data, \ 10568c7de6fSVarun Wadekar . - __tegra186_cpu_reset_handler_data 10668c7de6fSVarun Wadekar 10768c7de6fSVarun Wadekar .align 4 10868c7de6fSVarun Wadekar .globl __tegra186_cpu_reset_handler_end 10968c7de6fSVarun Wadekar__tegra186_cpu_reset_handler_end: 110