168c7de6fSVarun Wadekar/* 268c7de6fSVarun Wadekar * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 368c7de6fSVarun Wadekar * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 568c7de6fSVarun Wadekar */ 668c7de6fSVarun Wadekar 768c7de6fSVarun Wadekar#include <arch.h> 868c7de6fSVarun Wadekar#include <asm_macros.S> 968c7de6fSVarun Wadekar#include <memctrl_v2.h> 10*09d40e0eSAntonio Nino Diaz#include <plat/common/common_def.h> 1168c7de6fSVarun Wadekar#include <tegra_def.h> 1268c7de6fSVarun Wadekar 1368c7de6fSVarun Wadekar#define TEGRA186_SMMU_CTX_SIZE 0x420 1468c7de6fSVarun Wadekar 1568c7de6fSVarun Wadekar .globl tegra186_cpu_reset_handler 1668c7de6fSVarun Wadekar 1768c7de6fSVarun Wadekar/* CPU reset handler routine */ 1864726e6dSJulius Wernerfunc tegra186_cpu_reset_handler _align=4 1968c7de6fSVarun Wadekar /* 2025621454SVarun Wadekar * The TZRAM loses state during System Suspend. We use this 2125621454SVarun Wadekar * information to decide if the reset handler is running after a 2225621454SVarun Wadekar * System Suspend. Resume from system suspend requires restoring 2325621454SVarun Wadekar * the entire state from TZDRAM to TZRAM. 2468c7de6fSVarun Wadekar */ 2525621454SVarun Wadekar mov x0, #BL31_BASE 2625621454SVarun Wadekar ldr x0, [x0] 2725621454SVarun Wadekar cbnz x0, boot_cpu 2868c7de6fSVarun Wadekar 2968c7de6fSVarun Wadekar /* resume from system suspend */ 3068c7de6fSVarun Wadekar mov x0, #BL31_BASE 3168c7de6fSVarun Wadekar adr x1, __tegra186_cpu_reset_handler_end 3268c7de6fSVarun Wadekar adr x2, __tegra186_cpu_reset_handler_data 3368c7de6fSVarun Wadekar ldr x2, [x2, #8] 3468c7de6fSVarun Wadekar 3568c7de6fSVarun Wadekar /* memcpy16 */ 3668c7de6fSVarun Wadekarm_loop16: 3768c7de6fSVarun Wadekar cmp x2, #16 3868c7de6fSVarun Wadekar b.lt m_loop1 3968c7de6fSVarun Wadekar ldp x3, x4, [x1], #16 4068c7de6fSVarun Wadekar stp x3, x4, [x0], #16 4168c7de6fSVarun Wadekar sub x2, x2, #16 4268c7de6fSVarun Wadekar b m_loop16 4368c7de6fSVarun Wadekar /* copy byte per byte */ 4468c7de6fSVarun Wadekarm_loop1: 4568c7de6fSVarun Wadekar cbz x2, boot_cpu 4668c7de6fSVarun Wadekar ldrb w3, [x1], #1 4768c7de6fSVarun Wadekar strb w3, [x0], #1 4868c7de6fSVarun Wadekar subs x2, x2, #1 4968c7de6fSVarun Wadekar b.ne m_loop1 5068c7de6fSVarun Wadekar 5168c7de6fSVarun Wadekarboot_cpu: 5268c7de6fSVarun Wadekar adr x0, __tegra186_cpu_reset_handler_data 5368c7de6fSVarun Wadekar ldr x0, [x0] 5468c7de6fSVarun Wadekar br x0 5568c7de6fSVarun Wadekarendfunc tegra186_cpu_reset_handler 5668c7de6fSVarun Wadekar 5768c7de6fSVarun Wadekar /* 5868c7de6fSVarun Wadekar * Tegra186 reset data (offset 0x0 - 0x430) 5968c7de6fSVarun Wadekar * 6068c7de6fSVarun Wadekar * 0x000: secure world's entrypoint 6168c7de6fSVarun Wadekar * 0x008: BL31 size (RO + RW) 6268c7de6fSVarun Wadekar * 0x00C: SMMU context start 6368c7de6fSVarun Wadekar * 0x42C: SMMU context end 6468c7de6fSVarun Wadekar */ 6568c7de6fSVarun Wadekar 6668c7de6fSVarun Wadekar .align 4 6768c7de6fSVarun Wadekar .type __tegra186_cpu_reset_handler_data, %object 6868c7de6fSVarun Wadekar .globl __tegra186_cpu_reset_handler_data 6968c7de6fSVarun Wadekar__tegra186_cpu_reset_handler_data: 7068c7de6fSVarun Wadekar .quad tegra_secure_entrypoint 7168c7de6fSVarun Wadekar .quad __BL31_END__ - BL31_BASE 7263ac1a2aSVarun Wadekar .globl __tegra186_smmu_context 7363ac1a2aSVarun Wadekar__tegra186_smmu_context: 7468c7de6fSVarun Wadekar .rept TEGRA186_SMMU_CTX_SIZE 7568c7de6fSVarun Wadekar .quad 0 7668c7de6fSVarun Wadekar .endr 7768c7de6fSVarun Wadekar .size __tegra186_cpu_reset_handler_data, \ 7868c7de6fSVarun Wadekar . - __tegra186_cpu_reset_handler_data 7968c7de6fSVarun Wadekar 8068c7de6fSVarun Wadekar .align 4 8168c7de6fSVarun Wadekar .globl __tegra186_cpu_reset_handler_end 8268c7de6fSVarun Wadekar__tegra186_cpu_reset_handler_end: 83