1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <assert.h> 33 #include <bl_common.h> 34 #include <console.h> 35 #include <context.h> 36 #include <context_mgmt.h> 37 #include <debug.h> 38 #include <denver.h> 39 #include <interrupt_mgmt.h> 40 #include <mce.h> 41 #include <platform.h> 42 #include <tegra_def.h> 43 #include <tegra_private.h> 44 #include <xlat_tables.h> 45 46 /******************************************************************************* 47 * The Tegra power domain tree has a single system level power domain i.e. a 48 * single root node. The first entry in the power domain descriptor specifies 49 * the number of power domains at the highest power level. 50 ******************************************************************************* 51 */ 52 const unsigned char tegra_power_domain_tree_desc[] = { 53 /* No of root nodes */ 54 1, 55 /* No of clusters */ 56 PLATFORM_CLUSTER_COUNT, 57 /* No of CPU cores - cluster0 */ 58 PLATFORM_MAX_CPUS_PER_CLUSTER, 59 /* No of CPU cores - cluster1 */ 60 PLATFORM_MAX_CPUS_PER_CLUSTER 61 }; 62 63 /* 64 * Table of regions to map using the MMU. 65 */ 66 static const mmap_region_t tegra_mmap[] = { 67 MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000, /* 64KB */ 68 MT_DEVICE | MT_RW | MT_SECURE), 69 MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000, /* 128KB */ 70 MT_DEVICE | MT_RW | MT_SECURE), 71 MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000, /* 64KB */ 72 MT_DEVICE | MT_RW | MT_SECURE), 73 MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000, /* 64KB */ 74 MT_DEVICE | MT_RW | MT_SECURE), 75 MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000, /* 128KB */ 76 MT_DEVICE | MT_RW | MT_SECURE), 77 MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000, /* 128KB */ 78 MT_DEVICE | MT_RW | MT_SECURE), 79 MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000, /* 64KB */ 80 MT_DEVICE | MT_RW | MT_SECURE), 81 MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000, /* 64KB */ 82 MT_DEVICE | MT_RW | MT_SECURE), 83 MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000, /* 64KB */ 84 MT_DEVICE | MT_RW | MT_SECURE), 85 MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000, /* 64KB */ 86 MT_DEVICE | MT_RW | MT_SECURE), 87 MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000, /* 256KB */ 88 MT_DEVICE | MT_RW | MT_SECURE), 89 MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000, /* 64KB */ 90 MT_DEVICE | MT_RW | MT_SECURE), 91 MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000, /* 384KB */ 92 MT_DEVICE | MT_RW | MT_SECURE), 93 MAP_REGION_FLAT(TEGRA_SMMU_BASE, 0x1000000, /* 64KB */ 94 MT_DEVICE | MT_RW | MT_SECURE), 95 {0} 96 }; 97 98 /******************************************************************************* 99 * Set up the pagetables as per the platform memory map & initialize the MMU 100 ******************************************************************************/ 101 const mmap_region_t *plat_get_mmio_map(void) 102 { 103 /* MMIO space */ 104 return tegra_mmap; 105 } 106 107 /******************************************************************************* 108 * Handler to get the System Counter Frequency 109 ******************************************************************************/ 110 unsigned int plat_get_syscnt_freq2(void) 111 { 112 return 31250000; 113 } 114 115 /******************************************************************************* 116 * Maximum supported UART controllers 117 ******************************************************************************/ 118 #define TEGRA186_MAX_UART_PORTS 7 119 120 /******************************************************************************* 121 * This variable holds the UART port base addresses 122 ******************************************************************************/ 123 static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = { 124 0, /* undefined - treated as an error case */ 125 TEGRA_UARTA_BASE, 126 TEGRA_UARTB_BASE, 127 TEGRA_UARTC_BASE, 128 TEGRA_UARTD_BASE, 129 TEGRA_UARTE_BASE, 130 TEGRA_UARTF_BASE, 131 TEGRA_UARTG_BASE, 132 }; 133 134 /******************************************************************************* 135 * Retrieve the UART controller base to be used as the console 136 ******************************************************************************/ 137 uint32_t plat_get_console_from_id(int id) 138 { 139 if (id > TEGRA186_MAX_UART_PORTS) 140 return 0; 141 142 return tegra186_uart_addresses[id]; 143 } 144 145 /* Secure IRQs for Tegra186 */ 146 static const irq_sec_cfg_t tegra186_sec_irqs[] = { 147 { 148 TEGRA186_TOP_WDT_IRQ, 149 TEGRA186_SEC_IRQ_TARGET_MASK, 150 INTR_TYPE_EL3, 151 }, 152 { 153 TEGRA186_AON_WDT_IRQ, 154 TEGRA186_SEC_IRQ_TARGET_MASK, 155 INTR_TYPE_EL3, 156 }, 157 }; 158 159 /******************************************************************************* 160 * Initialize the GIC and SGIs 161 ******************************************************************************/ 162 void plat_gic_setup(void) 163 { 164 tegra_gic_setup(tegra186_sec_irqs, 165 sizeof(tegra186_sec_irqs) / sizeof(tegra186_sec_irqs[0])); 166 167 /* 168 * Initialize the FIQ handler only if the platform supports any 169 * FIQ interrupt sources. 170 */ 171 if (sizeof(tegra186_sec_irqs) > 0) 172 tegra_fiq_handler_setup(); 173 } 174 175 /******************************************************************************* 176 * Handler for early platform setup 177 ******************************************************************************/ 178 void plat_early_platform_setup(void) 179 { 180 mce_verify_firmware_version(); 181 } 182