1 /* 2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <assert.h> 33 #include <bl_common.h> 34 #include <console.h> 35 #include <context.h> 36 #include <context_mgmt.h> 37 #include <debug.h> 38 #include <denver.h> 39 #include <interrupt_mgmt.h> 40 #include <platform.h> 41 #include <tegra_def.h> 42 #include <tegra_private.h> 43 #include <xlat_tables.h> 44 45 /******************************************************************************* 46 * The Tegra power domain tree has a single system level power domain i.e. a 47 * single root node. The first entry in the power domain descriptor specifies 48 * the number of power domains at the highest power level. 49 ******************************************************************************* 50 */ 51 const unsigned char tegra_power_domain_tree_desc[] = { 52 /* No of root nodes */ 53 1, 54 /* No of clusters */ 55 PLATFORM_CLUSTER_COUNT, 56 /* No of CPU cores - cluster0 */ 57 PLATFORM_MAX_CPUS_PER_CLUSTER, 58 /* No of CPU cores - cluster1 */ 59 PLATFORM_MAX_CPUS_PER_CLUSTER 60 }; 61 62 /* 63 * Table of regions to map using the MMU. 64 */ 65 static const mmap_region_t tegra_mmap[] = { 66 MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000, /* 64KB */ 67 MT_DEVICE | MT_RW | MT_SECURE), 68 MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000, /* 64KB */ 69 MT_DEVICE | MT_RW | MT_SECURE), 70 MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000, /* 64KB */ 71 MT_DEVICE | MT_RW | MT_SECURE), 72 MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000, /* 128KB */ 73 MT_DEVICE | MT_RW | MT_SECURE), 74 MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000, /* 128KB */ 75 MT_DEVICE | MT_RW | MT_SECURE), 76 MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000, /* 64KB */ 77 MT_DEVICE | MT_RW | MT_SECURE), 78 MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000, /* 256KB */ 79 MT_DEVICE | MT_RW | MT_SECURE), 80 MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000, /* 384KB */ 81 MT_DEVICE | MT_RW | MT_SECURE), 82 MAP_REGION_FLAT(TEGRA_SMMU_BASE, 0x10000, /* 64KB */ 83 MT_DEVICE | MT_RW | MT_SECURE), 84 {0} 85 }; 86 87 /******************************************************************************* 88 * Set up the pagetables as per the platform memory map & initialize the MMU 89 ******************************************************************************/ 90 const mmap_region_t *plat_get_mmio_map(void) 91 { 92 /* MMIO space */ 93 return tegra_mmap; 94 } 95 96 /******************************************************************************* 97 * Handler to get the System Counter Frequency 98 ******************************************************************************/ 99 unsigned int plat_get_syscnt_freq2(void) 100 { 101 return 31250000; 102 } 103 104 /******************************************************************************* 105 * Maximum supported UART controllers 106 ******************************************************************************/ 107 #define TEGRA186_MAX_UART_PORTS 7 108 109 /******************************************************************************* 110 * This variable holds the UART port base addresses 111 ******************************************************************************/ 112 static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = { 113 0, /* undefined - treated as an error case */ 114 TEGRA_UARTA_BASE, 115 TEGRA_UARTB_BASE, 116 TEGRA_UARTC_BASE, 117 TEGRA_UARTD_BASE, 118 TEGRA_UARTE_BASE, 119 TEGRA_UARTF_BASE, 120 TEGRA_UARTG_BASE, 121 }; 122 123 /******************************************************************************* 124 * Retrieve the UART controller base to be used as the console 125 ******************************************************************************/ 126 uint32_t plat_get_console_from_id(int id) 127 { 128 if (id > TEGRA186_MAX_UART_PORTS) 129 return 0; 130 131 return tegra186_uart_addresses[id]; 132 } 133 134 /* Secure IRQs for Tegra186 */ 135 static const irq_sec_cfg_t tegra186_sec_irqs[] = { 136 { 137 TEGRA186_TOP_WDT_IRQ, 138 TEGRA186_SEC_IRQ_TARGET_MASK, 139 INTR_TYPE_EL3, 140 }, 141 { 142 TEGRA186_AON_WDT_IRQ, 143 TEGRA186_SEC_IRQ_TARGET_MASK, 144 INTR_TYPE_EL3, 145 }, 146 }; 147 148 /******************************************************************************* 149 * Initialize the GIC and SGIs 150 ******************************************************************************/ 151 void plat_gic_setup(void) 152 { 153 tegra_gic_setup(tegra186_sec_irqs, 154 sizeof(tegra186_sec_irqs) / sizeof(tegra186_sec_irqs[0])); 155 156 /* 157 * Initialize the FIQ handler only if the platform supports any 158 * FIQ interrupt sources. 159 */ 160 if (sizeof(tegra186_sec_irqs) > 0) 161 tegra_fiq_handler_setup(); 162 } 163