1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <arch_helpers.h> 10 #include <bl31/bl31.h> 11 #include <bl31/interrupt_mgmt.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <common/interrupt_props.h> 15 #include <context.h> 16 #include <cortex_a57.h> 17 #include <denver.h> 18 #include <drivers/arm/gic_common.h> 19 #include <drivers/arm/gicv2.h> 20 #include <drivers/console.h> 21 #include <lib/el3_runtime/context_mgmt.h> 22 #include <lib/xlat_tables/xlat_tables_v2.h> 23 #include <plat/common/platform.h> 24 25 #include <mce.h> 26 #include <tegra_def.h> 27 #include <tegra_platform.h> 28 #include <tegra_private.h> 29 30 /******************************************************************************* 31 * Tegra186 CPU numbers in cluster #0 32 ******************************************************************************* 33 */ 34 #define TEGRA186_CLUSTER0_CORE2 2U 35 #define TEGRA186_CLUSTER0_CORE3 3U 36 37 /******************************************************************************* 38 * The Tegra power domain tree has a single system level power domain i.e. a 39 * single root node. The first entry in the power domain descriptor specifies 40 * the number of power domains at the highest power level. 41 ******************************************************************************* 42 */ 43 const uint8_t tegra_power_domain_tree_desc[] = { 44 /* No of root nodes */ 45 1, 46 /* No of clusters */ 47 PLATFORM_CLUSTER_COUNT, 48 /* No of CPU cores - cluster0 */ 49 PLATFORM_MAX_CPUS_PER_CLUSTER, 50 /* No of CPU cores - cluster1 */ 51 PLATFORM_MAX_CPUS_PER_CLUSTER 52 }; 53 54 /******************************************************************************* 55 * This function returns the Tegra default topology tree information. 56 ******************************************************************************/ 57 const uint8_t *plat_get_power_domain_tree_desc(void) 58 { 59 return tegra_power_domain_tree_desc; 60 } 61 62 /* 63 * Table of regions to map using the MMU. 64 */ 65 static const mmap_region_t tegra_mmap[] = { 66 MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000U, /* 64KB */ 67 MT_DEVICE | MT_RW | MT_SECURE), 68 MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000U, /* 128KB */ 69 MT_DEVICE | MT_RW | MT_SECURE), 70 MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000U, /* 64KB */ 71 MT_DEVICE | MT_RW | MT_SECURE), 72 MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000U, /* 64KB */ 73 MT_DEVICE | MT_RW | MT_SECURE), 74 MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000U, /* 128KB - UART A, B*/ 75 MT_DEVICE | MT_RW | MT_SECURE), 76 MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000U, /* 128KB - UART C, G */ 77 MT_DEVICE | MT_RW | MT_SECURE), 78 MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000U, /* 192KB - UART D, E, F */ 79 MT_DEVICE | MT_RW | MT_SECURE), 80 MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000U, /* 64KB */ 81 MT_DEVICE | MT_RW | MT_SECURE), 82 MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000U, /* 128KB */ 83 MT_DEVICE | MT_RW | MT_SECURE), 84 MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000U, /* 64KB */ 85 MT_DEVICE | MT_RW | MT_SECURE), 86 MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000U, /* 64KB */ 87 MT_DEVICE | MT_RW | MT_SECURE), 88 MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000U, /* 64KB */ 89 MT_DEVICE | MT_RW | MT_SECURE), 90 MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000U, /* 64KB */ 91 MT_DEVICE | MT_RW | MT_SECURE), 92 MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000U, /* 256KB */ 93 MT_DEVICE | MT_RW | MT_SECURE), 94 MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000U, /* 64KB */ 95 MT_DEVICE | MT_RW | MT_SECURE), 96 MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000U, /* 384KB */ 97 MT_DEVICE | MT_RW | MT_SECURE), 98 MAP_REGION_FLAT(TEGRA_ARM_ACTMON_CTR_BASE, 0x20000U, /* 128KB - ARM/Denver */ 99 MT_DEVICE | MT_RW | MT_SECURE), 100 MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x1000000U, /* 64KB */ 101 MT_DEVICE | MT_RW | MT_SECURE), 102 {0} 103 }; 104 105 /******************************************************************************* 106 * Set up the pagetables as per the platform memory map & initialize the MMU 107 ******************************************************************************/ 108 const mmap_region_t *plat_get_mmio_map(void) 109 { 110 /* MMIO space */ 111 return tegra_mmap; 112 } 113 114 /******************************************************************************* 115 * Handler to get the System Counter Frequency 116 ******************************************************************************/ 117 uint32_t plat_get_syscnt_freq2(void) 118 { 119 return 31250000; 120 } 121 122 /******************************************************************************* 123 * Maximum supported UART controllers 124 ******************************************************************************/ 125 #define TEGRA186_MAX_UART_PORTS 7 126 127 /******************************************************************************* 128 * This variable holds the UART port base addresses 129 ******************************************************************************/ 130 static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = { 131 0, /* undefined - treated as an error case */ 132 TEGRA_UARTA_BASE, 133 TEGRA_UARTB_BASE, 134 TEGRA_UARTC_BASE, 135 TEGRA_UARTD_BASE, 136 TEGRA_UARTE_BASE, 137 TEGRA_UARTF_BASE, 138 TEGRA_UARTG_BASE, 139 }; 140 141 /******************************************************************************* 142 * Retrieve the UART controller base to be used as the console 143 ******************************************************************************/ 144 uint32_t plat_get_console_from_id(int32_t id) 145 { 146 uint32_t ret; 147 148 if (id > TEGRA186_MAX_UART_PORTS) { 149 ret = 0; 150 } else { 151 ret = tegra186_uart_addresses[id]; 152 } 153 154 return ret; 155 } 156 157 /******************************************************************************* 158 * Handler for early platform setup 159 ******************************************************************************/ 160 void plat_early_platform_setup(void) 161 { 162 uint64_t impl, val; 163 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); 164 165 /* sanity check MCE firmware compatibility */ 166 mce_verify_firmware_version(); 167 168 impl = (read_midr() >> MIDR_IMPL_SHIFT) & (uint64_t)MIDR_IMPL_MASK; 169 170 /* 171 * Enable ECC and Parity Protection for Cortex-A57 CPUs (Tegra186 172 * A02p and beyond). 173 */ 174 if ((plat_params->l2_ecc_parity_prot_dis != 1) && 175 (impl != (uint64_t)DENVER_IMPL)) { 176 177 val = read_l2ctlr_el1(); 178 val |= CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT; 179 write_l2ctlr_el1(val); 180 } 181 } 182 183 /* Secure IRQs for Tegra186 */ 184 static const interrupt_prop_t tegra186_interrupt_props[] = { 185 INTR_PROP_DESC(TEGRA186_TOP_WDT_IRQ, GIC_HIGHEST_SEC_PRIORITY, 186 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE), 187 INTR_PROP_DESC(TEGRA186_AON_WDT_IRQ, GIC_HIGHEST_SEC_PRIORITY, 188 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE) 189 }; 190 191 /******************************************************************************* 192 * Initialize the GIC and SGIs 193 ******************************************************************************/ 194 void plat_gic_setup(void) 195 { 196 tegra_gic_setup(tegra186_interrupt_props, ARRAY_SIZE(tegra186_interrupt_props)); 197 198 /* 199 * Initialize the FIQ handler only if the platform supports any 200 * FIQ interrupt sources. 201 */ 202 if (sizeof(tegra186_interrupt_props) > 0U) { 203 tegra_fiq_handler_setup(); 204 } 205 } 206 207 /******************************************************************************* 208 * Return pointer to the BL31 params from previous bootloader 209 ******************************************************************************/ 210 struct tegra_bl31_params *plat_get_bl31_params(void) 211 { 212 uint32_t val; 213 214 val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_LO); 215 216 return (struct tegra_bl31_params *)(uintptr_t)val; 217 } 218 219 /******************************************************************************* 220 * Return pointer to the BL31 platform params from previous bootloader 221 ******************************************************************************/ 222 plat_params_from_bl2_t *plat_get_bl31_plat_params(void) 223 { 224 uint32_t val; 225 226 val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_HI); 227 228 return (plat_params_from_bl2_t *)(uintptr_t)val; 229 } 230 231 /******************************************************************************* 232 * This function implements a part of the critical interface between the psci 233 * generic layer and the platform that allows the former to query the platform 234 * to convert an MPIDR to a unique linear index. An error code (-1) is returned 235 * in case the MPIDR is invalid. 236 ******************************************************************************/ 237 int32_t plat_core_pos_by_mpidr(u_register_t mpidr) 238 { 239 u_register_t cluster_id, cpu_id, pos; 240 int32_t ret; 241 242 cluster_id = (mpidr >> (u_register_t)MPIDR_AFF1_SHIFT) & (u_register_t)MPIDR_AFFLVL_MASK; 243 cpu_id = (mpidr >> (u_register_t)MPIDR_AFF0_SHIFT) & (u_register_t)MPIDR_AFFLVL_MASK; 244 245 /* 246 * Validate cluster_id by checking whether it represents 247 * one of the two clusters present on the platform. 248 * Validate cpu_id by checking whether it represents a CPU in 249 * one of the two clusters present on the platform. 250 */ 251 if ((cluster_id >= (u_register_t)PLATFORM_CLUSTER_COUNT) || 252 (cpu_id >= (u_register_t)PLATFORM_MAX_CPUS_PER_CLUSTER)) { 253 ret = PSCI_E_NOT_PRESENT; 254 } else { 255 /* calculate the core position */ 256 pos = cpu_id + (cluster_id << 2U); 257 258 /* check for non-existent CPUs */ 259 if ((pos == TEGRA186_CLUSTER0_CORE2) || (pos == TEGRA186_CLUSTER0_CORE3)) { 260 ret = PSCI_E_NOT_PRESENT; 261 } else { 262 ret = (int32_t)pos; 263 } 264 } 265 266 return ret; 267 } 268