1 /* 2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 10 #include <arch_helpers.h> 11 #include <bl31/bl31.h> 12 #include <bl31/interrupt_mgmt.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <common/ep_info.h> 16 #include <common/interrupt_props.h> 17 #include <context.h> 18 #include <cortex_a57.h> 19 #include <denver.h> 20 #include <drivers/arm/gic_common.h> 21 #include <drivers/arm/gicv2.h> 22 #include <drivers/console.h> 23 #include <lib/el3_runtime/context_mgmt.h> 24 #include <lib/utils.h> 25 #include <lib/xlat_tables/xlat_tables_v2.h> 26 #include <plat/common/platform.h> 27 28 #include <mce.h> 29 #include <memctrl.h> 30 #include <tegra_def.h> 31 #include <tegra_platform.h> 32 #include <tegra_private.h> 33 34 extern void memcpy16(void *dest, const void *src, unsigned int length); 35 36 /******************************************************************************* 37 * Tegra186 CPU numbers in cluster #0 38 ******************************************************************************* 39 */ 40 #define TEGRA186_CLUSTER0_CORE2 2U 41 #define TEGRA186_CLUSTER0_CORE3 3U 42 43 /******************************************************************************* 44 * The Tegra power domain tree has a single system level power domain i.e. a 45 * single root node. The first entry in the power domain descriptor specifies 46 * the number of power domains at the highest power level. 47 ******************************************************************************* 48 */ 49 static const uint8_t tegra_power_domain_tree_desc[] = { 50 /* No of root nodes */ 51 1, 52 /* No of clusters */ 53 PLATFORM_CLUSTER_COUNT, 54 /* No of CPU cores - cluster0 */ 55 PLATFORM_MAX_CPUS_PER_CLUSTER, 56 /* No of CPU cores - cluster1 */ 57 PLATFORM_MAX_CPUS_PER_CLUSTER 58 }; 59 60 /******************************************************************************* 61 * This function returns the Tegra default topology tree information. 62 ******************************************************************************/ 63 const uint8_t *plat_get_power_domain_tree_desc(void) 64 { 65 return tegra_power_domain_tree_desc; 66 } 67 68 /* 69 * Table of regions to map using the MMU. 70 */ 71 static const mmap_region_t tegra_mmap[] = { 72 MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000U, /* 64KB */ 73 MT_DEVICE | MT_RW | MT_SECURE), 74 MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000U, /* 128KB */ 75 MT_DEVICE | MT_RW | MT_SECURE), 76 MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000U, /* 64KB */ 77 MT_DEVICE | MT_RW | MT_SECURE), 78 MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000U, /* 64KB */ 79 MT_DEVICE | MT_RW | MT_SECURE), 80 MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000U, /* 128KB - UART A, B*/ 81 MT_DEVICE | MT_RW | MT_SECURE), 82 MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000U, /* 128KB - UART C, G */ 83 MT_DEVICE | MT_RW | MT_SECURE), 84 MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000U, /* 192KB - UART D, E, F */ 85 MT_DEVICE | MT_RW | MT_SECURE), 86 MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000U, /* 64KB */ 87 MT_DEVICE | MT_RW | MT_SECURE), 88 MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000U, /* 128KB */ 89 MT_DEVICE | MT_RW | MT_SECURE), 90 MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000U, /* 64KB */ 91 MT_DEVICE | MT_RW | MT_SECURE), 92 MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000U, /* 64KB */ 93 MT_DEVICE | MT_RW | MT_SECURE), 94 MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000U, /* 64KB */ 95 MT_DEVICE | MT_RW | MT_SECURE), 96 MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000U, /* 64KB */ 97 MT_DEVICE | MT_RW | MT_SECURE), 98 MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000U, /* 256KB */ 99 MT_DEVICE | MT_RW | MT_SECURE), 100 MAP_REGION_FLAT(TEGRA_TMRUS_BASE, 0x1000U, /* 4KB */ 101 MT_DEVICE | MT_RO | MT_SECURE), 102 MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000U, /* 64KB */ 103 MT_DEVICE | MT_RW | MT_SECURE), 104 MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000U, /* 384KB */ 105 MT_DEVICE | MT_RW | MT_SECURE), 106 MAP_REGION_FLAT(TEGRA_ARM_ACTMON_CTR_BASE, 0x20000U, /* 128KB - ARM/Denver */ 107 MT_DEVICE | MT_RW | MT_SECURE), 108 MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x1000000U, /* 64KB */ 109 MT_DEVICE | MT_RW | MT_SECURE), 110 MAP_REGION_FLAT(TEGRA_HSP_DBELL_BASE, 0x10000U, /* 64KB */ 111 MT_DEVICE | MT_RW | MT_SECURE), 112 MAP_REGION_FLAT(TEGRA_BPMP_IPC_TX_PHYS_BASE, TEGRA_BPMP_IPC_CH_MAP_SIZE, /* 4KB */ 113 MT_DEVICE | MT_RW | MT_SECURE), 114 MAP_REGION_FLAT(TEGRA_BPMP_IPC_RX_PHYS_BASE, TEGRA_BPMP_IPC_CH_MAP_SIZE, /* 4KB */ 115 MT_DEVICE | MT_RW | MT_SECURE), 116 {0} 117 }; 118 119 /******************************************************************************* 120 * Set up the pagetables as per the platform memory map & initialize the MMU 121 ******************************************************************************/ 122 const mmap_region_t *plat_get_mmio_map(void) 123 { 124 /* MMIO space */ 125 return tegra_mmap; 126 } 127 128 /******************************************************************************* 129 * Handler to get the System Counter Frequency 130 ******************************************************************************/ 131 uint32_t plat_get_syscnt_freq2(void) 132 { 133 return 31250000; 134 } 135 136 /******************************************************************************* 137 * Maximum supported UART controllers 138 ******************************************************************************/ 139 #define TEGRA186_MAX_UART_PORTS 7 140 141 /******************************************************************************* 142 * This variable holds the UART port base addresses 143 ******************************************************************************/ 144 static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = { 145 0, /* undefined - treated as an error case */ 146 TEGRA_UARTA_BASE, 147 TEGRA_UARTB_BASE, 148 TEGRA_UARTC_BASE, 149 TEGRA_UARTD_BASE, 150 TEGRA_UARTE_BASE, 151 TEGRA_UARTF_BASE, 152 TEGRA_UARTG_BASE, 153 }; 154 155 /******************************************************************************* 156 * Enable console corresponding to the console ID 157 ******************************************************************************/ 158 void plat_enable_console(int32_t id) 159 { 160 static console_t uart_console; 161 uint32_t console_clock; 162 163 if ((id > 0) && (id < TEGRA186_MAX_UART_PORTS)) { 164 /* 165 * Reference clock used by the FPGAs is a lot slower. 166 */ 167 if (tegra_platform_is_fpga()) { 168 console_clock = TEGRA_BOOT_UART_CLK_13_MHZ; 169 } else { 170 console_clock = TEGRA_BOOT_UART_CLK_408_MHZ; 171 } 172 173 (void)console_16550_register(tegra186_uart_addresses[id], 174 console_clock, 175 TEGRA_CONSOLE_BAUDRATE, 176 &uart_console); 177 console_set_scope(&uart_console, CONSOLE_FLAG_BOOT | 178 CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH); 179 } 180 } 181 182 /******************************************************************************* 183 * Handler for early platform setup 184 ******************************************************************************/ 185 void plat_early_platform_setup(void) 186 { 187 uint64_t impl, val; 188 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); 189 const struct tegra_bl31_params *arg_from_bl2 = plat_get_bl31_params(); 190 191 /* Verify chip id is t186 */ 192 assert(tegra_chipid_is_t186()); 193 194 /* sanity check MCE firmware compatibility */ 195 mce_verify_firmware_version(); 196 197 /* 198 * Do initial security configuration to allow DRAM/device access. 199 */ 200 tegra_memctrl_tzdram_setup(plat_params->tzdram_base, 201 (uint32_t)plat_params->tzdram_size); 202 203 impl = (read_midr() >> MIDR_IMPL_SHIFT) & (uint64_t)MIDR_IMPL_MASK; 204 205 /* 206 * Enable ECC and Parity Protection for Cortex-A57 CPUs (Tegra186 207 * A02p and beyond). 208 */ 209 if ((plat_params->l2_ecc_parity_prot_dis != 1) && 210 (impl != (uint64_t)DENVER_IMPL)) { 211 212 val = read_l2ctlr_el1(); 213 val |= CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT; 214 write_l2ctlr_el1(val); 215 } 216 217 /* 218 * The previous bootloader might not have placed the BL32 image 219 * inside the TZDRAM. Platform handler to allow relocation of BL32 220 * image to TZDRAM memory. This behavior might change per platform. 221 */ 222 plat_relocate_bl32_image(arg_from_bl2->bl32_image_info); 223 } 224 225 /******************************************************************************* 226 * Handler for late platform setup 227 ******************************************************************************/ 228 void plat_late_platform_setup(void) 229 { 230 ; /* do nothing */ 231 } 232 233 /* Secure IRQs for Tegra186 */ 234 static const interrupt_prop_t tegra186_interrupt_props[] = { 235 INTR_PROP_DESC(TEGRA_SDEI_SGI_PRIVATE, PLAT_SDEI_CRITICAL_PRI, 236 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE), 237 INTR_PROP_DESC(TEGRA186_TOP_WDT_IRQ, PLAT_TEGRA_WDT_PRIO, 238 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE), 239 INTR_PROP_DESC(TEGRA186_AON_WDT_IRQ, PLAT_TEGRA_WDT_PRIO, 240 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE) 241 }; 242 243 /******************************************************************************* 244 * Initialize the GIC and SGIs 245 ******************************************************************************/ 246 void plat_gic_setup(void) 247 { 248 tegra_gic_setup(tegra186_interrupt_props, ARRAY_SIZE(tegra186_interrupt_props)); 249 tegra_gic_init(); 250 251 /* 252 * Initialize the FIQ handler only if the platform supports any 253 * FIQ interrupt sources. 254 */ 255 tegra_fiq_handler_setup(); 256 } 257 258 /******************************************************************************* 259 * Return pointer to the BL31 params from previous bootloader 260 ******************************************************************************/ 261 struct tegra_bl31_params *plat_get_bl31_params(void) 262 { 263 uint32_t val; 264 265 val = mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PARAMS_ADDR); 266 267 return (struct tegra_bl31_params *)(uintptr_t)val; 268 } 269 270 /******************************************************************************* 271 * Return pointer to the BL31 platform params from previous bootloader 272 ******************************************************************************/ 273 plat_params_from_bl2_t *plat_get_bl31_plat_params(void) 274 { 275 uint32_t val; 276 277 val = mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PLAT_PARAMS_ADDR); 278 279 return (plat_params_from_bl2_t *)(uintptr_t)val; 280 } 281 282 /******************************************************************************* 283 * This function implements a part of the critical interface between the psci 284 * generic layer and the platform that allows the former to query the platform 285 * to convert an MPIDR to a unique linear index. An error code (-1) is returned 286 * in case the MPIDR is invalid. 287 ******************************************************************************/ 288 int32_t plat_core_pos_by_mpidr(u_register_t mpidr) 289 { 290 u_register_t cluster_id, cpu_id, pos; 291 int32_t ret; 292 293 cluster_id = (mpidr >> (u_register_t)MPIDR_AFF1_SHIFT) & (u_register_t)MPIDR_AFFLVL_MASK; 294 cpu_id = (mpidr >> (u_register_t)MPIDR_AFF0_SHIFT) & (u_register_t)MPIDR_AFFLVL_MASK; 295 296 /* 297 * Validate cluster_id by checking whether it represents 298 * one of the two clusters present on the platform. 299 * Validate cpu_id by checking whether it represents a CPU in 300 * one of the two clusters present on the platform. 301 */ 302 if ((cluster_id >= (u_register_t)PLATFORM_CLUSTER_COUNT) || 303 (cpu_id >= (u_register_t)PLATFORM_MAX_CPUS_PER_CLUSTER)) { 304 ret = PSCI_E_NOT_PRESENT; 305 } else { 306 /* calculate the core position */ 307 pos = cpu_id + (cluster_id << 2U); 308 309 /* check for non-existent CPUs */ 310 if ((pos == TEGRA186_CLUSTER0_CORE2) || (pos == TEGRA186_CLUSTER0_CORE3)) { 311 ret = PSCI_E_NOT_PRESENT; 312 } else { 313 ret = (int32_t)pos; 314 } 315 } 316 317 return ret; 318 } 319 320 /******************************************************************************* 321 * Handler to relocate BL32 image to TZDRAM 322 ******************************************************************************/ 323 void plat_relocate_bl32_image(const image_info_t *bl32_img_info) 324 { 325 const plat_params_from_bl2_t *plat_bl31_params = plat_get_bl31_plat_params(); 326 const entry_point_info_t *bl32_ep_info = bl31_plat_get_next_image_ep_info(SECURE); 327 uint64_t tzdram_start, tzdram_end, bl32_start, bl32_end; 328 329 if ((bl32_img_info != NULL) && (bl32_ep_info != NULL)) { 330 331 /* Relocate BL32 if it resides outside of the TZDRAM */ 332 tzdram_start = plat_bl31_params->tzdram_base; 333 tzdram_end = plat_bl31_params->tzdram_base + 334 plat_bl31_params->tzdram_size; 335 bl32_start = bl32_img_info->image_base; 336 bl32_end = bl32_img_info->image_base + bl32_img_info->image_size; 337 338 assert(tzdram_end > tzdram_start); 339 assert(bl32_end > bl32_start); 340 assert(bl32_ep_info->pc > tzdram_start); 341 assert(bl32_ep_info->pc < tzdram_end); 342 343 /* relocate BL32 */ 344 if ((bl32_start >= tzdram_end) || (bl32_end <= tzdram_start)) { 345 346 INFO("Relocate BL32 to TZDRAM\n"); 347 348 (void)memcpy16((void *)(uintptr_t)bl32_ep_info->pc, 349 (void *)(uintptr_t)bl32_start, 350 bl32_img_info->image_size); 351 352 /* clean up non-secure intermediate buffer */ 353 zeromem((void *)(uintptr_t)bl32_start, 354 bl32_img_info->image_size); 355 } 356 } 357 } 358 359 /******************************************************************************* 360 * Handler to indicate support for System Suspend 361 ******************************************************************************/ 362 bool plat_supports_system_suspend(void) 363 { 364 return true; 365 } 366