13cf3183fSVarun Wadekar /* 250402b17SVarun Wadekar * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 33cf3183fSVarun Wadekar * 43cf3183fSVarun Wadekar * Redistribution and use in source and binary forms, with or without 53cf3183fSVarun Wadekar * modification, are permitted provided that the following conditions are met: 63cf3183fSVarun Wadekar * 73cf3183fSVarun Wadekar * Redistributions of source code must retain the above copyright notice, this 83cf3183fSVarun Wadekar * list of conditions and the following disclaimer. 93cf3183fSVarun Wadekar * 103cf3183fSVarun Wadekar * Redistributions in binary form must reproduce the above copyright notice, 113cf3183fSVarun Wadekar * this list of conditions and the following disclaimer in the documentation 123cf3183fSVarun Wadekar * and/or other materials provided with the distribution. 133cf3183fSVarun Wadekar * 143cf3183fSVarun Wadekar * Neither the name of ARM nor the names of its contributors may be used 153cf3183fSVarun Wadekar * to endorse or promote products derived from this software without specific 163cf3183fSVarun Wadekar * prior written permission. 173cf3183fSVarun Wadekar * 183cf3183fSVarun Wadekar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 193cf3183fSVarun Wadekar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 203cf3183fSVarun Wadekar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 213cf3183fSVarun Wadekar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 223cf3183fSVarun Wadekar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 233cf3183fSVarun Wadekar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 243cf3183fSVarun Wadekar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 253cf3183fSVarun Wadekar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 263cf3183fSVarun Wadekar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 273cf3183fSVarun Wadekar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 283cf3183fSVarun Wadekar * POSSIBILITY OF SUCH DAMAGE. 293cf3183fSVarun Wadekar */ 303cf3183fSVarun Wadekar 3150cd8646SVarun Wadekar #include <arch_helpers.h> 3250cd8646SVarun Wadekar #include <assert.h> 3350cd8646SVarun Wadekar #include <bl_common.h> 343cf3183fSVarun Wadekar #include <console.h> 3550cd8646SVarun Wadekar #include <context.h> 3650cd8646SVarun Wadekar #include <context_mgmt.h> 3750cd8646SVarun Wadekar #include <debug.h> 3850cd8646SVarun Wadekar #include <denver.h> 3950cd8646SVarun Wadekar #include <interrupt_mgmt.h> 4050cd8646SVarun Wadekar #include <platform.h> 413cf3183fSVarun Wadekar #include <tegra_def.h> 4250cd8646SVarun Wadekar #include <tegra_private.h> 433cf3183fSVarun Wadekar #include <xlat_tables.h> 443cf3183fSVarun Wadekar 45b67a7c7cSVarun Wadekar /******************************************************************************* 46b67a7c7cSVarun Wadekar * The Tegra power domain tree has a single system level power domain i.e. a 47b67a7c7cSVarun Wadekar * single root node. The first entry in the power domain descriptor specifies 48b67a7c7cSVarun Wadekar * the number of power domains at the highest power level. 49b67a7c7cSVarun Wadekar ******************************************************************************* 50b67a7c7cSVarun Wadekar */ 51b67a7c7cSVarun Wadekar const unsigned char tegra_power_domain_tree_desc[] = { 52b67a7c7cSVarun Wadekar /* No of root nodes */ 53b67a7c7cSVarun Wadekar 1, 54b67a7c7cSVarun Wadekar /* No of clusters */ 55b67a7c7cSVarun Wadekar PLATFORM_CLUSTER_COUNT, 56b67a7c7cSVarun Wadekar /* No of CPU cores - cluster0 */ 57b67a7c7cSVarun Wadekar PLATFORM_MAX_CPUS_PER_CLUSTER, 58b67a7c7cSVarun Wadekar /* No of CPU cores - cluster1 */ 59b67a7c7cSVarun Wadekar PLATFORM_MAX_CPUS_PER_CLUSTER 60b67a7c7cSVarun Wadekar }; 61b67a7c7cSVarun Wadekar 623cf3183fSVarun Wadekar /* 633cf3183fSVarun Wadekar * Table of regions to map using the MMU. 643cf3183fSVarun Wadekar */ 653cf3183fSVarun Wadekar static const mmap_region_t tegra_mmap[] = { 663cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000, /* 64KB */ 673cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 68*e64ce3abSVarun Wadekar MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000, /* 128KB */ 69*e64ce3abSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 703cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000, /* 64KB */ 713cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 723cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000, /* 64KB */ 733cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 743cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000, /* 128KB */ 753cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 763cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000, /* 128KB */ 773cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 7850402b17SVarun Wadekar MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000, /* 64KB */ 7950402b17SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 8050402b17SVarun Wadekar MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000, /* 64KB */ 8150402b17SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 8250402b17SVarun Wadekar MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000, /* 64KB */ 8350402b17SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 8467bc721bSVarun Wadekar MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000, /* 64KB */ 8567bc721bSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 863cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000, /* 256KB */ 873cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 8850402b17SVarun Wadekar MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000, /* 64KB */ 8950402b17SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 903cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000, /* 384KB */ 913cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 9250402b17SVarun Wadekar MAP_REGION_FLAT(TEGRA_SMMU_BASE, 0x1000000, /* 64KB */ 933cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 943cf3183fSVarun Wadekar {0} 953cf3183fSVarun Wadekar }; 963cf3183fSVarun Wadekar 973cf3183fSVarun Wadekar /******************************************************************************* 983cf3183fSVarun Wadekar * Set up the pagetables as per the platform memory map & initialize the MMU 993cf3183fSVarun Wadekar ******************************************************************************/ 1003cf3183fSVarun Wadekar const mmap_region_t *plat_get_mmio_map(void) 1013cf3183fSVarun Wadekar { 1023cf3183fSVarun Wadekar /* MMIO space */ 1033cf3183fSVarun Wadekar return tegra_mmap; 1043cf3183fSVarun Wadekar } 1053cf3183fSVarun Wadekar 1063cf3183fSVarun Wadekar /******************************************************************************* 1073cf3183fSVarun Wadekar * Handler to get the System Counter Frequency 1083cf3183fSVarun Wadekar ******************************************************************************/ 1093cf3183fSVarun Wadekar unsigned int plat_get_syscnt_freq2(void) 1103cf3183fSVarun Wadekar { 1115d74d68eSVarun Wadekar return 31250000; 1123cf3183fSVarun Wadekar } 1133cf3183fSVarun Wadekar 1143cf3183fSVarun Wadekar /******************************************************************************* 1153cf3183fSVarun Wadekar * Maximum supported UART controllers 1163cf3183fSVarun Wadekar ******************************************************************************/ 1173cf3183fSVarun Wadekar #define TEGRA186_MAX_UART_PORTS 7 1183cf3183fSVarun Wadekar 1193cf3183fSVarun Wadekar /******************************************************************************* 1203cf3183fSVarun Wadekar * This variable holds the UART port base addresses 1213cf3183fSVarun Wadekar ******************************************************************************/ 1223cf3183fSVarun Wadekar static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = { 1233cf3183fSVarun Wadekar 0, /* undefined - treated as an error case */ 1243cf3183fSVarun Wadekar TEGRA_UARTA_BASE, 1253cf3183fSVarun Wadekar TEGRA_UARTB_BASE, 1263cf3183fSVarun Wadekar TEGRA_UARTC_BASE, 1273cf3183fSVarun Wadekar TEGRA_UARTD_BASE, 1283cf3183fSVarun Wadekar TEGRA_UARTE_BASE, 1293cf3183fSVarun Wadekar TEGRA_UARTF_BASE, 1303cf3183fSVarun Wadekar TEGRA_UARTG_BASE, 1313cf3183fSVarun Wadekar }; 1323cf3183fSVarun Wadekar 1333cf3183fSVarun Wadekar /******************************************************************************* 1343cf3183fSVarun Wadekar * Retrieve the UART controller base to be used as the console 1353cf3183fSVarun Wadekar ******************************************************************************/ 1363cf3183fSVarun Wadekar uint32_t plat_get_console_from_id(int id) 1373cf3183fSVarun Wadekar { 1383cf3183fSVarun Wadekar if (id > TEGRA186_MAX_UART_PORTS) 1393cf3183fSVarun Wadekar return 0; 1403cf3183fSVarun Wadekar 1413cf3183fSVarun Wadekar return tegra186_uart_addresses[id]; 1423cf3183fSVarun Wadekar } 14350cd8646SVarun Wadekar 14450cd8646SVarun Wadekar /* Secure IRQs for Tegra186 */ 14550cd8646SVarun Wadekar static const irq_sec_cfg_t tegra186_sec_irqs[] = { 14650cd8646SVarun Wadekar { 14750cd8646SVarun Wadekar TEGRA186_TOP_WDT_IRQ, 14850cd8646SVarun Wadekar TEGRA186_SEC_IRQ_TARGET_MASK, 14950cd8646SVarun Wadekar INTR_TYPE_EL3, 15050cd8646SVarun Wadekar }, 15150cd8646SVarun Wadekar { 15250cd8646SVarun Wadekar TEGRA186_AON_WDT_IRQ, 15350cd8646SVarun Wadekar TEGRA186_SEC_IRQ_TARGET_MASK, 15450cd8646SVarun Wadekar INTR_TYPE_EL3, 15550cd8646SVarun Wadekar }, 15650cd8646SVarun Wadekar }; 15750cd8646SVarun Wadekar 15850cd8646SVarun Wadekar /******************************************************************************* 15950cd8646SVarun Wadekar * Initialize the GIC and SGIs 16050cd8646SVarun Wadekar ******************************************************************************/ 16150cd8646SVarun Wadekar void plat_gic_setup(void) 16250cd8646SVarun Wadekar { 16350cd8646SVarun Wadekar tegra_gic_setup(tegra186_sec_irqs, 16450cd8646SVarun Wadekar sizeof(tegra186_sec_irqs) / sizeof(tegra186_sec_irqs[0])); 16550cd8646SVarun Wadekar 16650cd8646SVarun Wadekar /* 16750cd8646SVarun Wadekar * Initialize the FIQ handler only if the platform supports any 16850cd8646SVarun Wadekar * FIQ interrupt sources. 16950cd8646SVarun Wadekar */ 17050cd8646SVarun Wadekar if (sizeof(tegra186_sec_irqs) > 0) 17150cd8646SVarun Wadekar tegra_fiq_handler_setup(); 17250cd8646SVarun Wadekar } 173