13cf3183fSVarun Wadekar /* 280c50eeaSVarun Wadekar * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 33cf3183fSVarun Wadekar * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 53cf3183fSVarun Wadekar */ 63cf3183fSVarun Wadekar 750cd8646SVarun Wadekar #include <assert.h> 809d40e0eSAntonio Nino Diaz 909d40e0eSAntonio Nino Diaz #include <arch_helpers.h> 1009d40e0eSAntonio Nino Diaz #include <bl31/bl31.h> 1109d40e0eSAntonio Nino Diaz #include <bl31/interrupt_mgmt.h> 1209d40e0eSAntonio Nino Diaz #include <common/bl_common.h> 1309d40e0eSAntonio Nino Diaz #include <common/debug.h> 1409d40e0eSAntonio Nino Diaz #include <common/interrupt_props.h> 1550cd8646SVarun Wadekar #include <context.h> 161eed3838SVarun Wadekar #include <cortex_a57.h> 1750cd8646SVarun Wadekar #include <denver.h> 1809d40e0eSAntonio Nino Diaz #include <drivers/arm/gic_common.h> 1909d40e0eSAntonio Nino Diaz #include <drivers/arm/gicv2.h> 2009d40e0eSAntonio Nino Diaz #include <drivers/console.h> 2109d40e0eSAntonio Nino Diaz #include <lib/el3_runtime/context_mgmt.h> 2209d40e0eSAntonio Nino Diaz #include <lib/xlat_tables/xlat_tables_v2.h> 2309d40e0eSAntonio Nino Diaz #include <plat/common/platform.h> 2409d40e0eSAntonio Nino Diaz 255cb89c56SVarun Wadekar #include <mce.h> 263cf3183fSVarun Wadekar #include <tegra_def.h> 272b04f927SVarun Wadekar #include <tegra_platform.h> 2850cd8646SVarun Wadekar #include <tegra_private.h> 293cf3183fSVarun Wadekar 30b67a7c7cSVarun Wadekar /******************************************************************************* 31ae8ac2d2SVarun Wadekar * Tegra186 CPU numbers in cluster #0 32ae8ac2d2SVarun Wadekar ******************************************************************************* 33ae8ac2d2SVarun Wadekar */ 34ae8ac2d2SVarun Wadekar #define TEGRA186_CLUSTER0_CORE2 2 35ae8ac2d2SVarun Wadekar #define TEGRA186_CLUSTER0_CORE3 3 36ae8ac2d2SVarun Wadekar 37ae8ac2d2SVarun Wadekar /******************************************************************************* 38b67a7c7cSVarun Wadekar * The Tegra power domain tree has a single system level power domain i.e. a 39b67a7c7cSVarun Wadekar * single root node. The first entry in the power domain descriptor specifies 40b67a7c7cSVarun Wadekar * the number of power domains at the highest power level. 41b67a7c7cSVarun Wadekar ******************************************************************************* 42b67a7c7cSVarun Wadekar */ 43b67a7c7cSVarun Wadekar const unsigned char tegra_power_domain_tree_desc[] = { 44b67a7c7cSVarun Wadekar /* No of root nodes */ 45b67a7c7cSVarun Wadekar 1, 46b67a7c7cSVarun Wadekar /* No of clusters */ 47b67a7c7cSVarun Wadekar PLATFORM_CLUSTER_COUNT, 48b67a7c7cSVarun Wadekar /* No of CPU cores - cluster0 */ 49b67a7c7cSVarun Wadekar PLATFORM_MAX_CPUS_PER_CLUSTER, 50b67a7c7cSVarun Wadekar /* No of CPU cores - cluster1 */ 51b67a7c7cSVarun Wadekar PLATFORM_MAX_CPUS_PER_CLUSTER 52b67a7c7cSVarun Wadekar }; 53b67a7c7cSVarun Wadekar 547b3b41d6SVarun Wadekar /******************************************************************************* 557b3b41d6SVarun Wadekar * This function returns the Tegra default topology tree information. 567b3b41d6SVarun Wadekar ******************************************************************************/ 577b3b41d6SVarun Wadekar const unsigned char *plat_get_power_domain_tree_desc(void) 587b3b41d6SVarun Wadekar { 597b3b41d6SVarun Wadekar return tegra_power_domain_tree_desc; 607b3b41d6SVarun Wadekar } 617b3b41d6SVarun Wadekar 623cf3183fSVarun Wadekar /* 633cf3183fSVarun Wadekar * Table of regions to map using the MMU. 643cf3183fSVarun Wadekar */ 653cf3183fSVarun Wadekar static const mmap_region_t tegra_mmap[] = { 663cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000, /* 64KB */ 673cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 68e64ce3abSVarun Wadekar MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000, /* 128KB */ 69e64ce3abSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 703cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000, /* 64KB */ 713cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 723cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000, /* 64KB */ 733cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 7449cbbc4eSVarun Wadekar MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000, /* 128KB - UART A, B*/ 7549cbbc4eSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 7649cbbc4eSVarun Wadekar MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000, /* 128KB - UART C, G */ 7749cbbc4eSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 7849cbbc4eSVarun Wadekar MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000, /* 192KB - UART D, E, F */ 793cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 801eed3838SVarun Wadekar MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000, /* 64KB */ 811eed3838SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 823cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000, /* 128KB */ 833cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 8450402b17SVarun Wadekar MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000, /* 64KB */ 8550402b17SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 8650402b17SVarun Wadekar MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000, /* 64KB */ 8750402b17SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 8850402b17SVarun Wadekar MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000, /* 64KB */ 8950402b17SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 9067bc721bSVarun Wadekar MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000, /* 64KB */ 9167bc721bSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 923cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000, /* 256KB */ 933cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 9450402b17SVarun Wadekar MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000, /* 64KB */ 9550402b17SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 963cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000, /* 384KB */ 973cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 98691bc22dSVarun Wadekar MAP_REGION_FLAT(TEGRA_ARM_ACTMON_CTR_BASE, 0x20000, /* 128KB - ARM/Denver */ 99691bc22dSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 100c459206dSPritesh Raithatha MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x1000000, /* 64KB */ 1013cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 1023cf3183fSVarun Wadekar {0} 1033cf3183fSVarun Wadekar }; 1043cf3183fSVarun Wadekar 1053cf3183fSVarun Wadekar /******************************************************************************* 1063cf3183fSVarun Wadekar * Set up the pagetables as per the platform memory map & initialize the MMU 1073cf3183fSVarun Wadekar ******************************************************************************/ 1083cf3183fSVarun Wadekar const mmap_region_t *plat_get_mmio_map(void) 1093cf3183fSVarun Wadekar { 1103cf3183fSVarun Wadekar /* MMIO space */ 1113cf3183fSVarun Wadekar return tegra_mmap; 1123cf3183fSVarun Wadekar } 1133cf3183fSVarun Wadekar 1143cf3183fSVarun Wadekar /******************************************************************************* 1153cf3183fSVarun Wadekar * Handler to get the System Counter Frequency 1163cf3183fSVarun Wadekar ******************************************************************************/ 1179c2a3d8aSVarun Wadekar unsigned int plat_get_syscnt_freq2(void) 1183cf3183fSVarun Wadekar { 1195d74d68eSVarun Wadekar return 31250000; 1203cf3183fSVarun Wadekar } 1213cf3183fSVarun Wadekar 1223cf3183fSVarun Wadekar /******************************************************************************* 1233cf3183fSVarun Wadekar * Maximum supported UART controllers 1243cf3183fSVarun Wadekar ******************************************************************************/ 1253cf3183fSVarun Wadekar #define TEGRA186_MAX_UART_PORTS 7 1263cf3183fSVarun Wadekar 1273cf3183fSVarun Wadekar /******************************************************************************* 1283cf3183fSVarun Wadekar * This variable holds the UART port base addresses 1293cf3183fSVarun Wadekar ******************************************************************************/ 1303cf3183fSVarun Wadekar static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = { 1313cf3183fSVarun Wadekar 0, /* undefined - treated as an error case */ 1323cf3183fSVarun Wadekar TEGRA_UARTA_BASE, 1333cf3183fSVarun Wadekar TEGRA_UARTB_BASE, 1343cf3183fSVarun Wadekar TEGRA_UARTC_BASE, 1353cf3183fSVarun Wadekar TEGRA_UARTD_BASE, 1363cf3183fSVarun Wadekar TEGRA_UARTE_BASE, 1373cf3183fSVarun Wadekar TEGRA_UARTF_BASE, 1383cf3183fSVarun Wadekar TEGRA_UARTG_BASE, 1393cf3183fSVarun Wadekar }; 1403cf3183fSVarun Wadekar 1413cf3183fSVarun Wadekar /******************************************************************************* 1423cf3183fSVarun Wadekar * Retrieve the UART controller base to be used as the console 1433cf3183fSVarun Wadekar ******************************************************************************/ 1443cf3183fSVarun Wadekar uint32_t plat_get_console_from_id(int id) 1453cf3183fSVarun Wadekar { 1463cf3183fSVarun Wadekar if (id > TEGRA186_MAX_UART_PORTS) 1473cf3183fSVarun Wadekar return 0; 1483cf3183fSVarun Wadekar 1493cf3183fSVarun Wadekar return tegra186_uart_addresses[id]; 1503cf3183fSVarun Wadekar } 15150cd8646SVarun Wadekar 1521eed3838SVarun Wadekar /******************************************************************************* 1531eed3838SVarun Wadekar * Handler for early platform setup 1541eed3838SVarun Wadekar ******************************************************************************/ 1551eed3838SVarun Wadekar void plat_early_platform_setup(void) 1561eed3838SVarun Wadekar { 157*b495791bSHarvey Hsieh uint64_t impl, val; 158*b495791bSHarvey Hsieh const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); 1591eed3838SVarun Wadekar 1601eed3838SVarun Wadekar /* sanity check MCE firmware compatibility */ 1611eed3838SVarun Wadekar mce_verify_firmware_version(); 1621eed3838SVarun Wadekar 163*b495791bSHarvey Hsieh impl = (read_midr() >> MIDR_IMPL_SHIFT) & (uint64_t)MIDR_IMPL_MASK; 164*b495791bSHarvey Hsieh 1651eed3838SVarun Wadekar /* 166*b495791bSHarvey Hsieh * Enable ECC and Parity Protection for Cortex-A57 CPUs (Tegra186 167*b495791bSHarvey Hsieh * A02p and beyond). 1681eed3838SVarun Wadekar */ 169*b495791bSHarvey Hsieh if ((plat_params->l2_ecc_parity_prot_dis != 1) && 170*b495791bSHarvey Hsieh (impl != (uint64_t)DENVER_IMPL)) { 1711eed3838SVarun Wadekar 1721eed3838SVarun Wadekar val = read_l2ctlr_el1(); 173*b495791bSHarvey Hsieh val |= (uint64_t)CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT; 1741eed3838SVarun Wadekar write_l2ctlr_el1(val); 1751eed3838SVarun Wadekar } 1761eed3838SVarun Wadekar } 1771eed3838SVarun Wadekar 17850cd8646SVarun Wadekar /* Secure IRQs for Tegra186 */ 17980c50eeaSVarun Wadekar static const interrupt_prop_t tegra186_interrupt_props[] = { 18080c50eeaSVarun Wadekar INTR_PROP_DESC(TEGRA186_TOP_WDT_IRQ, GIC_HIGHEST_SEC_PRIORITY, 18180c50eeaSVarun Wadekar GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE), 18280c50eeaSVarun Wadekar INTR_PROP_DESC(TEGRA186_AON_WDT_IRQ, GIC_HIGHEST_SEC_PRIORITY, 18380c50eeaSVarun Wadekar GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE) 18450cd8646SVarun Wadekar }; 18550cd8646SVarun Wadekar 18650cd8646SVarun Wadekar /******************************************************************************* 18750cd8646SVarun Wadekar * Initialize the GIC and SGIs 18850cd8646SVarun Wadekar ******************************************************************************/ 18950cd8646SVarun Wadekar void plat_gic_setup(void) 19050cd8646SVarun Wadekar { 19180c50eeaSVarun Wadekar tegra_gic_setup(tegra186_interrupt_props, ARRAY_SIZE(tegra186_interrupt_props)); 19250cd8646SVarun Wadekar 19350cd8646SVarun Wadekar /* 19450cd8646SVarun Wadekar * Initialize the FIQ handler only if the platform supports any 19550cd8646SVarun Wadekar * FIQ interrupt sources. 19650cd8646SVarun Wadekar */ 19780c50eeaSVarun Wadekar if (sizeof(tegra186_interrupt_props) > 0) 19850cd8646SVarun Wadekar tegra_fiq_handler_setup(); 19950cd8646SVarun Wadekar } 20048afb167SVarun Wadekar 20148afb167SVarun Wadekar /******************************************************************************* 20248afb167SVarun Wadekar * Return pointer to the BL31 params from previous bootloader 20348afb167SVarun Wadekar ******************************************************************************/ 204fdcc1127SAntonio Nino Diaz struct tegra_bl31_params *plat_get_bl31_params(void) 20548afb167SVarun Wadekar { 20648afb167SVarun Wadekar uint32_t val; 20748afb167SVarun Wadekar 20848afb167SVarun Wadekar val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_LO); 20948afb167SVarun Wadekar 210fdcc1127SAntonio Nino Diaz return (struct tegra_bl31_params *)(uintptr_t)val; 21148afb167SVarun Wadekar } 21248afb167SVarun Wadekar 21348afb167SVarun Wadekar /******************************************************************************* 21448afb167SVarun Wadekar * Return pointer to the BL31 platform params from previous bootloader 21548afb167SVarun Wadekar ******************************************************************************/ 21648afb167SVarun Wadekar plat_params_from_bl2_t *plat_get_bl31_plat_params(void) 21748afb167SVarun Wadekar { 21848afb167SVarun Wadekar uint32_t val; 21948afb167SVarun Wadekar 22048afb167SVarun Wadekar val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_HI); 22148afb167SVarun Wadekar 22248afb167SVarun Wadekar return (plat_params_from_bl2_t *)(uintptr_t)val; 22348afb167SVarun Wadekar } 224ae8ac2d2SVarun Wadekar 225ae8ac2d2SVarun Wadekar /******************************************************************************* 226ae8ac2d2SVarun Wadekar * This function implements a part of the critical interface between the psci 227ae8ac2d2SVarun Wadekar * generic layer and the platform that allows the former to query the platform 228ae8ac2d2SVarun Wadekar * to convert an MPIDR to a unique linear index. An error code (-1) is returned 229ae8ac2d2SVarun Wadekar * in case the MPIDR is invalid. 230ae8ac2d2SVarun Wadekar ******************************************************************************/ 231ae8ac2d2SVarun Wadekar int plat_core_pos_by_mpidr(u_register_t mpidr) 232ae8ac2d2SVarun Wadekar { 233ae8ac2d2SVarun Wadekar unsigned int cluster_id, cpu_id, pos; 234ae8ac2d2SVarun Wadekar 235ae8ac2d2SVarun Wadekar cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; 236ae8ac2d2SVarun Wadekar cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; 237ae8ac2d2SVarun Wadekar 238ae8ac2d2SVarun Wadekar /* 239ae8ac2d2SVarun Wadekar * Validate cluster_id by checking whether it represents 240ae8ac2d2SVarun Wadekar * one of the two clusters present on the platform. 241ae8ac2d2SVarun Wadekar */ 242ae8ac2d2SVarun Wadekar if (cluster_id >= PLATFORM_CLUSTER_COUNT) 243ae8ac2d2SVarun Wadekar return PSCI_E_NOT_PRESENT; 244ae8ac2d2SVarun Wadekar 245ae8ac2d2SVarun Wadekar /* 246ae8ac2d2SVarun Wadekar * Validate cpu_id by checking whether it represents a CPU in 247ae8ac2d2SVarun Wadekar * one of the two clusters present on the platform. 248ae8ac2d2SVarun Wadekar */ 249ae8ac2d2SVarun Wadekar if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) 250ae8ac2d2SVarun Wadekar return PSCI_E_NOT_PRESENT; 251ae8ac2d2SVarun Wadekar 252ae8ac2d2SVarun Wadekar /* calculate the core position */ 253ae8ac2d2SVarun Wadekar pos = cpu_id + (cluster_id << 2); 254ae8ac2d2SVarun Wadekar 255ae8ac2d2SVarun Wadekar /* check for non-existent CPUs */ 256ae8ac2d2SVarun Wadekar if (pos == TEGRA186_CLUSTER0_CORE2 || pos == TEGRA186_CLUSTER0_CORE3) 257ae8ac2d2SVarun Wadekar return PSCI_E_NOT_PRESENT; 258ae8ac2d2SVarun Wadekar 259ae8ac2d2SVarun Wadekar return pos; 260ae8ac2d2SVarun Wadekar } 261